5C090

5C090 INTEL | Alldatasheet

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20 MHz w/Feedback m 100% Generically Tested Logie Array

Figure 1. 5C090 Pin Configurations .

intel. INTRODUCTION ‘A feature unique to the 5C090 is the ability to individ- ually program the output registers as a D-, T-, SR-, or The Intel 5CO90 PLD (Programmable Logic Device) _—_JK-type Flip-Flop without sacrificing the utilization of is a 24-macrocell, 40-pin, general-purpose device. programmable AND logic. Additionally, each output The device can be used to replace low-end gate ar- _register can be individually clocked from any of the rays, multiple programmable logic arrays and LS __ input or feedback paths available within the AND ar- TTL and 74HC (CMOS) SSI and MSI logic devices. _ray. With these features, a wide variety of logic func- With its revolutionary programmable 1/0 architec- tions can be simultaneously implemented—all on ture, the device has advanced functional capabilities the same device. beyond that of typical programmable logic. Figure 2 shows the global architecture of the device. ARCHITECTURE DESCRIPTION The 5C090 PLD uses CMOS EPROM (floating gate) calls as logic control elements instead of fuses. The | The 5C090 has 12 dedicated inputs, 24 1/O pins CMOS EPROM technology reduces power con- which may be configured for input, output, or bidirec- sumption of PLDs to less than 20% of a comparable _ tional operations, and 2 synchronous clock inputs. bipolar device without sacrificing speed perform- The 5C090 is packaged in a 40-lead windowed ce- ance. In addition, Intel's advanced CMOS lI-E — famic DIP or 44-lead plastic leaded chip carrier EPROM process technology enables greater logic © Package and contains 24 programmable registers. densities to be achieved with superior speed and low-power performance over other comparable de- The basic Macrocell architecture for the 5C090 is vices. Intel's ELPDs add the benefits of “zero” shown in Figure 3. The 5C090 has 24 of these mac- stand-by power not available on other programma. _rocells (one for each I/O pin). The Macrocell is orga- ble logic devices. EPROM technology allows these nized in the familiar sum-of-products structure with a devices to be 100% factory tested by programming programmable AND array attached to a fixed OR and erasing all the EPROM logic control elements. term. The inputs to the programmable AND array originate from the true and complement signals from The architecture of the 5CO90 is based on the “Sum —_@ach of the dedicated input pins and each of the 1/0 of Products” PLA (Programmable Logic Array) struc- control blocks. ture with a programmable AND array feeding into a fixed OR array. The device accommodates combina- The AND array for the 5CO80 has 72 inputs derived tional and sequential logic functions. A proprietary __ffom the true and complement signals at the input programmable I/O architecture provides individual and I/O pins. The AND array in the 5C090 encom- selection of either combinatorial or registered output Passes 240 product terms which are distributed and feedback signals all with selectable polarity. among the 24 Macrocells. 2-276 |

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Figure 2. 5C090 Global Architecture

Figure 3. 5C090 Macrocell Architecture

The Macrocells contain ten product terms total. Eight of the ten pr terms (AND gates) are dedi. Output Enable (OE)/Clock Selection cated for logic implementation. One product term on Two modes of operation are provided by the each Macrocell is used for RESET control to the OE/CLK Select Multiplexer as a part of each Macro- Output register associated with the Macrocell. The cell. One mode provides for three-state buffering of final product term is used for OUTPUT ENABLE/ —_— outputs while in the other mode, the outputs are al- ‘Asynchronous Clock implementation. ways enabled. The operation of the OE/CLK Select Multiplexer sets the mode within a given Macrocell. Within the AND array, there is an EPROM connec- Therefore, the output mode can be selected individ. tion at every intersection of an input signal (true and —_ually on every output. Figure 4 illustrates the two complement) and a product term to a given Macro- modes of OE/CLK operation. cell. Before programming an erased device, every EPROM connection is made at every intersection. But during the programming process, these connec- © MODE 0: THREE-STATE BUFFERING tions are opened so that only the desired connec- , tions remain. Therefore, the true or complement of Mode ge tnroe. state ouput butter is controled any input signal can be connected to any product 37. Te output ig gnabled when the product torn term. If both the true and complement connections TaY. Te aulbut is pehived 6 of any signal are left intact, a logical false results on _'8 & logical true. Conversely, the output appears as fi/J a high impedance when the product term is a logical the output of the AND gate, However, itboth the true F215 28 shown in Table 1, im Mode 0, the Macrocell and complement connections are open, then a logic Fig rion ig connacted to lis associated synchronous “don't care” results on the AND gate. Lastly, if all FOP A H clock (either CLK1 or CLK2 depending upon the {he inputs of a product term are programmed open, M42 rocei's location within the device)’ Thus, the then 4 logical tue results on the output of the AND Marrocel Pe ene Taw clocked by its respective . ‘synchronous clock but its output will not become The 5C090 has two dedicated clock inputs to pro- Valid until the output is enabled. vide synchronous clock signals to the internal regis- tors. Each of the clock signals controls half the total Table 1. Mode 0 Output Selection registers within the given device. For example, CLK1 provides synchronous clocking to the registers in Macrocells in the loft half of the array while GLK2 controls the registers associated with Macrocells in the right half of the array. The advanced 1/0 archi- tecture allows for any number of the registers to be synchronously clocked (from none to all). Both of MODE 1: OUTPUT BUFFER ENABLED the dedicated clock inputs latch the data into a given register when triggered on a positive edge. In Mode 1, the Output Butter is always enabled. In addition, the Macrocell Flip-Flop is connected to the AND array. The Macrocell Flip-Flop may now be trig- MACROCELL ARCHITECTURE gered from an asynchronous clock signal generated SELECTION by the AND array logic to the OE/CLK multiplexable term. Mode 1 allows the Macrocell Flip-Flops to be The 5C090 architecture provides each Macrocell _ individually clocked from any of the available signals with over 50 different possible 1/O register configu- in the AND array. Since both true and complement rations. Each I/O pin can be configured for combina- —_values appear in the AND array, the Flip-Flop may torial or registered output (true or complement) with _be clocked by positive-or negative-going signals at feedback. In addition, four different types of output —_any input pin. Gated clock structures can be created registers can be implemented into every 1/O pin since the Flip-Flop clock is created by a product without any additional logic requirements. The feed- term. back mechanism for each register back into the AND array can be programmed to provide for either registered feedback from the Macrocell or input —_ Invert Select EPROM Bit feedback (treating the pin as an input). Another ad- vantage of the advanced I/O capability of the 5CO90_—The Invert Select EPROM bit is used to invert the is the ability to individually clock each intemal regis- product term input into the register. This applies to ter from asynchronous clock signals. all inputs including double inputs on the JK and SR registers. | 2-279

Figure 4. Output Enable/Clock Configuration

intel ° 5C090 REGISTER SELECTION When either a JK or SR register is configured, the eight product terms are shared among two OR The advanced I/O architecture of the 5C090 allows gates (one for the J or S input and the other for four different register types along with combinatorial the K or R input). The allocation for these product output as illustrated in Figure 5a through e. The reg- terms for each of the register inputs is optimized ister types include a T, D, JK, or SR Flip-Flop and by the iPLDS || development software. each Macrocell I/O structure may be independently configured. In addition, all registers have an individu- al asynchronous RESET contro! from a dedicated OUTPUT/FEEDBACK Product term derived in the AND array. When this ; dedicated product term is a logical one, the Macro- The Output Select Multiplexer allows for either regis- cell register is immediately cleared to a logical zero __—tered, combinatorial or no output. independent of the register clock, The RESET func- tion occurs automatically on power-up. The Feedback Select Multiplexer EPROM bit en- ables registered, I/O (using the pin for bidirectional input or just input), or no feedback to the AND array. Output Register Configuration PI st 9 The Feedback Select is also important for building The four different register types shown in Figure 5 product terms with more than 8 products. The 6 [WA are described below. Product product term of a Macrocell can be fed back into the AND array and combined with still more sig- D- or T-type Flip-Flops nals to create a much larger product term (of more than 8-inputs). In addition, if the feedback product When either a D- or T-type Flip-Flop is configured _term is not to be output, then the iPLDS II will re- as part of the 1/O structure, all eight of the product serve the associated Macrocell pin and indicate it in terms into the Macrocell are ORed together and the REPORT file. A reserved pin should be left float- fed into the register input. ing (no connect) when assembled onto a circuit board. JK or SR Registers Any I/O pin may be configured as a dedicated input by selecting no output and pin feedback through the appropriate multiplexers. 2 (/O SELECTION OUTPUT/POLARITY | FEEDBACK | ‘Combinatorial/ High Pin, None Combinatorial/Low Pin, None None Pin i" vert H 290195-7 Figure 5a. Combinatorial 1/0 Configuration | 2-281

intel. souso smamonoon W/O SELECTION “ JK Register/High | JK Register, None cepa JK Register/Low | JK Register, None “Or None JK Register FUNCTION TABLE © [4] x [on [on +s] cae ofolo] o H o}ol4 1 H of1}o] o { of+]4 0 i 1}o0] 0 1 D H 1) 0 1 1 H Dap} 1] 1] 0 1 . iN > RS tiifi4 0 2 200195-10 Figure Sd. JK Flip-Flop Register Configuration Fee sua VO SELECTION = [ourput/po.ariry | FEEDBACK _ | = ‘SR Register/High | SR Register, None “eT | SR Register/Low | SR Register, None [4 None SR Register FUNCTION TABLE i ~ olo H oo H o}1 } ol1 : 1]o + D 1] 0 Pe t Seg LLL we } t KO Dep H rd 290195-11 Figure 5e. SR Flip-Flop Register Configuration | 2-283

5C090 intel . Erased-State Configuration ensures reliability as the incremental program mar- gin of each bit is continually monitored to determine Prior to programming or after erasing, the I/O struc- when the bit has been successfully programmed. ture is configured for combinatorial active low output with input (pin) feedback. FUNCTIONAL TESTING ERASURE CHARACTERISTICS Since the logical operation of the 5C090 is controlled by EPROM elements, the device is com- Erasure characteristics of the device are such that _pletely testable. Each programmable EPROM bit ‘erasure begins to occur upon exposure to light with _ controlling the internal logic is tested using applica- wavelengths shorter than approximately 4000A. It tion-independent test program patterns. After test- should be noted that sunlight and certain types of __ ing, the devices are erased before shipment to cus- flourescent lamps have wavelengths in the 3000- tomers. No post-programming tests of the EPROM 4000A. Data shows that constant exposure to room —_— array are required. level flourescent lighting could erase the typical de- vice in approximately three years, while it would take The testability and reliability of EPROM-based pro- approximately one week to cause erasure when ex- grammable logic devices is an important feature posed to direct sunlight. If the 5C090 is to be ex- over similar devices based on fuse technology. posed to these types of lighting conditions for ex- Fuse-based programmable logic devices require a tended periods of time, conductive opaque labels user to perform post-programming tests to insure should be placed over the device window to prevent Proper programming. These tests must be done at unintentional erasure. the device level because of the cummulative error effect. For example, a board containing ten devices The recommended erasure procedure for the 5CO90. each possessing a 2% device fallout translates into is exposure to shortwave ultraviolet light with a an 18% fallout at the board level (it should be noted wavelength of 2537A. The integrated dose (i.e, UV _that programming fallout of fuse-based programma- intensity x exposure time) for erasure should be a _ble logic devices is typically 2% or higher). minimum of fifteen (15) Wsec/cm?. The erasure time with this dosage is approximately 15 to 20 min- utes using an ultraviolet amp with a 12,000 »W/cem2. DESIGN RECOMMENDATIONS Power rating. The 5C090 should be placed within . ‘one inch of the lamp tubes during erasure. The maxi- For proper operation, it is recommended that all in- mum integrated dose the 5C090 can be exposed to ‘ut and output pins be constrained to the voltage without damage is 7258 Wsec/cm2 (1 week at ange GND < (Vin or Vou) < Voc. Unused inputs 12,000 »W/cm2). Exposure to high intensity UV light and I/Os should be tied to Voc or GND to minimize for longer periods may cause permanent damage to device power consumption. Reserved pins (as indi- the device. cated in the logic compiler REPORT file) should be left floating (no connect) so that the pin can attain the appropriate logic level. A power supply decou- pling capacitor of at least 0.2 »F must be connected PROGRAMMING CHARACTERISTICS directly between Voc and GND pins of the device. Initially, and after erasure, all the EPROM control bits of the 5C090 are connected (in the "1" state). As with all CMOS devices, ESD handling procedures Each of the connected control bits are selectively should be used with the 5C090 to prevent damage disconnected by programming the EPROM cells into to the device during programming, assembly and their “0” state. Programming voltage and waveform __test. specifications are available by request from Intel to support programming of the 5CO90. DESIGN SECURITY Intelligent Programming Algorithm A single EPROM bit provides a programmable de- sign security feature that controls the access to the ‘The 5C090 supports the Intelligent Programming Al. data programmed into the device. If this bit is set, a gorithm which rapidly programs Intel ELPDs using an _ proprietary design within the device cannot be cop- efficient and reliable method. The Intelligent Pro- _ ied. This EPROM security bit enables a higher de- gramming Algorithm is particularly suited to the pro- duction programming environment. This method 2-284 |

scono intel. Tools that support schematic capture and timing fation for the are available. P' rofe ORDERING INFORMATION to the “Development Tools” section of the Program- fuax} Order Operating mable Logic Handbook. (MHz)|_ Code Range The 5C090 is also supported by third-party logic Commercial compilers such as ABEL*, CUPL*, PLDesigner, [Pscoso-s0 [PoP | Log/IC*, etc. Programming support is provided by Inscoe0.50 [PLCC | third-party programmer companies such as Data N5C090-50_|PLOG \\/O, Logical Devices, STAG, etc. Please refer to the 217 {D5c090-60 |CERDIP | ‘Commercial “Third-Party Support” lists in the Programmable Logie handbook for complete information and ven- [pscose-so [PoP | dor ona [== [| 263 [rwsc2eoso[r.cc [iain *ABEL is a trademark of Data |/O, Corporation. CUPL is a trademark of Logical Devices, Inc. PLDesigner is a trademark of MING, inc. Log/IC is trademark of ISDATA, Inc.

ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- [Srmboi] Parameter [win | Max [unite] Lesvons fo stjec’ to change whew notice. * WARNING: the device bey the “Absolute cs [Say vetget) 20] ro | v | aati rennet dvs Prod tuote y, Programming v These are stress ratings only. Operation beyond the PP “Operating Conditions” is not recommended and ex- Supply Voltage(") tended exposure beyond the “Operating Conditions” [Mi [Dcimpurvoraget@ |-o5|vec+os| v | may atect device rolabity. [tng [Storage Temperature | ~65| +150 | <c | lem [Aron eneostsw|yo| ves [ec] RECOMMENDED OPERATING “8 CONDITIONS rer [Smiot[ Penman | 1. Voltages with respect to ground. Symbol [ main | Max | unit] puts may undershoot to —2.0V or overshoot to +7.0V for Borods lass than 20 ns under no load conditions. [vm | tmputvottage | 0 | Veo |v | 3. Under bias. Extended temperature i SO avaiable. vemong we 80 Tyo [oupavorage | 0 | Voo | v | I [ta | Operating Temperature | 0 | +70] + | [ta | inputrisotime || 500 | re | NOTE: 4. tg, te for CLK is 250 ns max. D.C. CHARACTERISTICS Ta = 0°C to 70°C, Voc = 5.0V +5% [Symbot| Parameter | Conditions [ min [tye] Max [uni HIGH LovelinputVotage [20 | [Voc +08] v | LowLevelinputvotge | font Toe |v | Voxl®) | HIGH Level Output Voltage [lo = —4.0mADC,Voc=Min. | 24| | | v | LOW Level Output Vottage [ig = 40mADGVoc=Min | | | 04s | v | |__| Input Leakage Curent [Voc = Max,GND<Vin<Voc | | [+100 | na | |1oz___[ Output Leakage Current [ Voc = Max.GND<Vour<Voo| | [#100 | ua | Output Short Circuit Current | Voc = Max., Vout = 0.5V [| 2 | Standby Current Voc = Max, BA (Standby) Vin = Voc or GND | 2-287

scone intel. D.C. CHARACTERISTICS Ty = 0°C to 70°C, Voc = 5.0V +5% (Continued) [Symbor] Parameter | Conations [| Min | Typ | Max | Unit Power Supply Current Voc = Max., No Load, (Active) (Turbo Bit Off) Vin = Voc or GND | Input Freq. = 1 MHz Device Prog. as Two 12-Bit Ctrs. (See Ioc vs. Freq. Graph) NOTES: 5. Absolute values with respect to device GND; all over and undershoots due to system or tester noise are included. 6. Io at CMOS levels (3.84V) = —2 mA. 7. Not more than 1 output should be tested at a time. Duration of that test must not exceed 1 second. 8. With Turbo Bit Off, device automatically enters standby mode approximately 100 ns after last input transition. AC. TESTING LOAD CIRCUIT A.C. TESTING INPUT, OUTPUT WAVEFORM wv 30: fr 7 Device To Test output SYSTEM . 290195-14 = AC. Testing: Inputs are Driven at 3.0V for a Logic “1” and OV for 290195-13 ‘a Logic “0”. Timing Measurements are made at 2.0V for a Logic C= 50 pF "1" and 0.8V for @ Logic “O" on inputs. Outputs are measured at a 1.5V point. Device input rise and fall times < 6 ns. CAPACITANCE [_Symboi [Parameter [Conditions [Min | ‘Typ | Max | Unit | Vour= ov,f= towne | |__| 90 | oF Glock Pin Gapactance | Viy=Ov.f=10wHe | |_| 20] oF | CLK2 on 50000, = 10H | | | 00 | oF A.C. CHARACTERISTICS Ta = 0°C to 70°C, Voc = 5V +5%, Turbo Bit Ont) rs To 5C090-50 scoso-60 | Nont') EP900-2 EP900 Mode | win | Typ [ Max | win | Typ | Max | [tor | input | Comb. Output ||| as [P68 [+25 [os | [toe [vo | Comb. Output | || 50 [|| 60 [+25 [ns | tea [1orVO | Ouputerabie | | | 60 | | | 60 | +25 | ne | Asynch.Reset | QReset_ [50 [|| 60 [+25 [ns | NOTES: 9. Typical Values are at Ta = 25°C, Voc = 5V, Active Mode. 10. tpzx and tpxz are measured at +0.5V from steady state voltage as driven by spec. output load. tpxz is measured with Cu = 5 pF. tf If device is operated with Turbo Bit Off (Non-Turbo Mode) and the device has been inactive for approx. 100 ns, increase time by amount shown. 2-288 |

intel. sone0 SYNCHRONOUS CLOCK MODE A.C. CHARACTERISTIC Ta = 0°C to 70°C, Voc = 5.0V +5%, Turbo Bit On(9) [bee Non-(11) 5C090-50 5C090-60 [ae [tm [mn [wn [ Ty [ne | pe lemme | | [fel | (1/tgu—No Feedback) emma [TT || (1/tonr—With Feedback) [ex | rouseuptinewcx [a | | pa] | | + [a | [sz | vosew tiwiocx [oe | | [| | | +8 [we | [x [rowvonetanercucmen | of fe] |] | [ico [eakiigninowatvans [fa [| | Pro | tent Register Output Feedback +25 to Register Input—internal al [ier [oaxnenree af |e | [ta [oaxiowtie rs [ae [rr J ASYNCHRONOUS CLOCK MODE A.C. CHARACTERISTICS Ta = 0°C to 70°C, Voc = 5.0V +5%, Turbo Bit On(8) [bee Non-(11) ora ee ae “oom | eae [i [ yp [wx [wn | ye [wa por [rece | TT [lt | (1/tacnt—With Feedback) a a Asynch. Clock ee a Asynch. Clock NF Asynch. Clock Fico | Asmen cuxroovourvas || [ae [| [oe | a | ve | vor famerememmeas TT TREE Te Te Register Input—internal Path Fics [ Amen cucitgnting [wre [ [fas | [vas Pas | Fuca Laser cxtowrine [vrs | es | [| as [ns | | 2-289

scone intel. SWITCHING WAVEFORMS. COMBINATORIAL MODE INPUT OR 1/0 INPUT S teo COMBINATORIAL OUTPUT | | be tone (FROM REGISTER | HIGH IMPEDANCE TO OUTPUT) 3= STATE t— ‘xx HIGH IMPEDANCE Yau ouput 3= STATE tour ASYNCHRONOUSLY CLEAR OUTPUT 200106-15 SYNCHRONOUS CLOCK MODE tou ta ux, cux2 su} INPUT MAY CHANGE = INPUT MAY CHANGE Leo FROM REGISTER conn «e OUTPUT) VALIO OUTPUT 29018516 2-290 |

intel. se000 SWITCHING WAVEFORMS (Continued) ASYNCHRONOUS CLOCK MODE tao hee ssn ‘su | tan cnn ame VEY wor un ounce we {mou renesten Y vauo ourrur 5C090 5C090 Current in Relation to Frequency Output Drive Current in Relation to Voltage anes 2ee 7 EEE 140 : S— > 7 =» —

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po) s y fo PEPE a : fo (uz) Vo Output Voltage (Y Conditions: T, = 0°C, Voc = 5.25V Conditions: Ta = 25°C 5C090 tpp Derating vs. Capacative Loading Eons 3 sominte Z ne 2 ane Copactonce 290195-20 CONDITIONS: Ta = 25°C, Veo = 5.0V | 2-291