41210 INTEL | Alldatasheet
Document overview
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- PDF pages: 52
Technical content
Datasheet sections
- 1 Introduction
- 1.1 About This Document
- 1.2 Product Overview
- 2 Signal Description
- 2.1 On Die Termination (ODT)
- 2.2 PCI Express Interface
- 2.3 PCI Bus Interface (Two Instances)
- 2.4 PCI Bus Interface 64-Bit Extension (Two Interfaces)
- 2.5 PCI Bus Interface Clocks and, Reset and Power Management (Two Interfaces)
- 2.6 Interrupt Interface (Two Interfaces)
- 2.7 Reset Straps
- 2.8 SMBus Interface
- 2.9 Miscellaneous Pins
- 3 Electrical and Thermal Characteristics
- 3.1 DC Voltage and Current Specifications
- 3.2 AC Specifications
- 3.3 Voltage Filter Specifications
- 3.4 VCC15 and VCC33 Voltage Requirements
- 3.5 Timing Specifications
- 3.8 Reference and Compensation Pins
- 3.9 Thermal Specifications
- 4 Package Specification and Ballout
- 4.1 Package Specification
- 4.2 Ball Map
- 4.3 Signal List, sorted by Ball Location
- 4.4 Signal List, sorted by Signal Name
- 1 Minimum Transmitter Timing and Voltage Output Compliance Specification
- 2 Compliance Test/Measurement Load
- 3 Minimum Receiver Eye Timing and Voltage Compliance Specification
- 4 Voltage Requirements VCC33 versus VCC15
- 5 PCI Output Timing
- 6 PCI Input Timing
Datasheet sections
- 1 ODT Signals
- 2 PCI Express Interface Pins
- 3 PCI Interface Pins
- 4 PCI Interface Pins: 64-Bit Extensions
- 5 PCI Clock and Reset Pins
- 6 Interrupt Interface Pins
- 7 Reset Strap Pins
- 8 SMBus Interface Pins
- 9 Miscellaneous Pins
- 10 Intel® 41210 Bridge DC Voltage Specifications
- 11 DC Characteristics Input Signal Association
- 12 DC Input Characteristics
- 13 DC Characteristic Output Signal Association
- 14 DC Output Characteristic
- 15 Differential Transmitter (TX) DC Output Specifications
- 16 Differential Receiver (RX) DC Input Specifications
- 19 DC Specification for Output Clock Signals
- 22 Differential Transmitter (TX) AC Output Specifications
- 23 Differential Receiver (RX) AC Input Specifications
- 24 PCI Interface Timing
- 26 PCI and PCI-X Clock Timings
- 31 Signal List, sorted by Ball Name
- 32 Signal List, sorted by Signal Name
Datasheet sections
Order Number: 278875-005US May 2005 Intel® 41210 Serial to Parallel PCI Bridge Datasheet Product Features ■ PCI Express Specification, Revision 1.0a ■ Support for single x8, single x4 or single x1 PCI Express operation. ■ 64-bit addressing support ■ 32-bit CRC (cyclic redundancy checking) covering all transmitted data packets. ■ 16-bit CRC on all link message information. ■ Raw bit-rate on the data pins of 2.5 Gbit/s, resulting in a raw bandwidth per pin of 250 MB/s. ■ Maximum realized bandwidth on PCI Express interface is 2 GB/s (in x8 mode) in each direction simultaneously, for an aggregate of 4 GB/s. ■ PCI Local Bus Specification, Revision 2.3. ■ PCI-to-PCI Bridge Specification, Revision 1.1. ■ PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b ■ 64-bit 66 MHz, 3.3 V , NOT 5 V tolerant. ■ On Die Termination (ODT) with 8.3KOhm pull-up to 3.3V for PCI signals. ■ Six external REQ/GNT Pairs for internal arbiter on segment A and B respectively. ■ Programmable bus parking on either the last agent or always on the 41210 Bridge ■ 2-level programmable round-robin internal arbiter with Multi-Transaction Timer (MTT) ■ External PCI clock-feed support for asynchronous primary and secondary domain operation. ■ 64-bit addressing for upstream and downstream transactions ■ Downstream LOCK# support. ■ No upstream LOCK# support. ■ PCI fast Back-to-Back capable as target. ■ Up to four active and four pending upstream memory read transactions ■ Up to two downstream delayed (memory read, I/O read/write and configuration read/ write) transaction. ■ Tunable inbound read prefetch algorithm for PCI MRM/MRL commands ■ Device hiding support for secondary PCI devices. ■ Secondary bus Private Memory support via Opaque memory region ■ Local initialization via SMBus ■ Secondary side initialization via Type 0 configuration cycles. ■ Full peer-to-peer read/write capability between the two secondary PCI segments.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY , OR INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. The Intel® 41210 Serial to Parallel PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtaine d by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile , i386, i486, i960, iCOMP, InstantIP, Intel, Intel Centrino, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, VoiceBrick, VTune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2005, Intel Corporation
Order Number: 278875-005US May 2005
Datasheet — 41210 Bridge Introduction 1
1.1 About This Document
This document provides information on the Intel® 41210 Serial to Parallel PCI Bridge, including a functional overview, signal descriptions, mechanical data, package signal location and bus functional waveforms.
1.2 Product Overview
The Intel® 41210 Serial to Parallel PCI Bridge (also called the 41210 Bridge) integrates two PCI Express-to-PCI/PCI-X bridges. Each bridge follows the PCI-to-PCI Bridge programming model. The PCI Express port is compatible with the PCI Express Specification, Revision 1.0a. The two PCI bus interfaces are compatible with the PCI Local Bus Specification, Revision 2.3 and PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.
41210 Bridge — Datasheet
The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “#” is not present after the signal name the signal is asserted when at the high voltage level. The following notations are used to describe the signal type: I: Input pin O: Output pin OD: Open-drain Output pin I/O: Bidirectional Input/Output pin I/OD: Bidirectional Input/Open-drain Output pin
2.1 On Die Termination (ODT)
The 41210 Bridge incorporates on-die termination for most of the PCI interface signals. This eliminates the need for the system designer to incorporate external pull-up resistors in the design. The following signals have an on die termination of 8.33KOhm @40%:
Table 1. ODT Signals
2.2 PCI Express Interface
Table 2. PCI Express Interface Pins
2.3 PCI Bus Interface (Two Instances)
REFCLKn I PCI Express Reference Clocks : 100 MHz differential clock pair.
Table 3. PCI Interface Pins (Sheet 1 of 2) data phases of a transaction, the initiator drives write data, or the target drives read data. No External pull-up resistors are required on the system board for these signals. transactions, the initiator drives byte enables on C/BE#[3:0] during the data phases. No External pull-up resistors are required on the system board for these signals. Bridge is the initiator of a PCI write transaction, and when it is the target of a read transaction.
41210 Bridge checks parity when it is the initiator of PCI read transactions and when it is the target of
No External pull-up resistors are required on the system board for these signals.
41210 Bridge initiated transaction on the
the 41210 Bridge until driven as a target. No External pull-up resistors are required on the system board for these signals. No External pull-up resistors are required on the system board for these signals. transaction. A data phase is completed when both IRDY# and TRDY# are sampled asserted. No External pull-up resistors are required on the system board for these signals. Target Ready: Indicates the ability of the target to complete the current data phase of the transaction. 41210 Bridge until driven as a target. No External pull-up resistors are required on the system board for these signals. B_STOP# I/O Stop: Indicates that the target is requesting an initiator to stop the current transaction. No External pull-up resistors are required on the system board for these signals.
41210 Bridge when, as a initiator it detects a parity error during a read transaction and as a target
No External pull-up resistors are required on the system board for these signals. No External pull-up resistors are required on the system board for these signals. to generate appropriate clock (33 or 66 MHz) on the PCI Bus. Use an approximately 8.2KΩ resistor to pull to VCC33 or pull-down to ground.
2.4 PCI Bus Interface 64-Bit Extension (Two Interfaces)
Bridge can switch into PCI-X mode. Use an approximately 8.2K Ω resistor to pull to VCC33. PCI Lock: Indicates an exclusive bus operation and may require multiple transactions to complete. ignored when PCI masters are granted the bus. Locked transaction do not propagate upstream. No External pull-up resistors are required on the system board for these signals. Table 4. PCI Interface Pins: 64-Bit Extensions REQ64# and ACK64# are both asserted. BE#[7:4] for both address and data phases.
41210 Bridge is
the initiator, this signal is an output. When the 41210 Bridge is the target this signal is an input. Table 3. PCI Interface Pins (Sheet 2 of 2)
2.5 PCI Bus Interface Clocks and, Reset and Power
2.6 Interrupt Interface (Two Interfaces)
standard INTA:INTD pci signals.
2.7 Reset Straps
Table 5. PCI Clock and Reset Pins corresponding X_CLKO[6] through a 22 Ω±1% series resistor. B_RST# O PCI Reset: The bridge asserts RST# to reset devices that reside on the secondary PCI bus. signal that will be converted to a PME event on PCI Express. This pin does not have on-die 8.3K pull-up. This pull-up must be provided externally. Table 6. Interrupt Interface Pins
Table 7. Reset Strap Pins segment will only run at 100 MHz when X_PCIXCAP is sampled high. must be pulled high for normal operation. B_TEST{2:1] I Internal Test Modes: These straps should be pulled high to VCC33. Use approximately an 8.2KΩ resistor to pull-up to VCC33. Cycle Retry Bit (bit 3) in the Bridge Initialization Register at Offset FC. If no local initialization is needed, this pin should be pulled low to VSS.
2.8 SMBus Interface
Table 8. SMBus Interface Pins
2.9 Miscellaneous Pins
Table 9. Miscellaneous Pins ground. Sampled at the rising edge of PERST#. internal logic (including sticky bits). high for adapter card usage. If not utilizing JTAG, this signal can be left as a no connect. If not utilizing JTAG, this signal can be left as a no connect. If not utilizing JTAG, this signal can be left as a no connect.
Test Mode Select: This signal controls the TAP controller state machine to move to different states and is sampled on the rising edge of TCK. If not utilizing JTAG, this signal can be left as a no connect. TRST# I Test Reset In: This signal is used to asynchronously reset the JTAG BSCAN logic. If not utilizing JTAG, connect this signal to ground through a 1KΩ pull-down resistor. RESERVED[8:1] I Reserved: (8 pins) These input pins should be pulled low Use an approximately 8.2KΩ resistor to pull-down to ground. A_NC[10:1] B_NC[10:1] O No Connect: (39 pins) These output pins should be left floating NC[17] O This signal requires an external pull-up, 8.2K ohm to 3.3V Total 57 Signal I/O Description
3.1 DC Voltage and Current Specifications
- Transient tolerance ±5 mV above 1 MHz at package pin under DC load conditions.
- Transient tolerance ±10 mV above 1 MHz at package pin under DC load conditions.
Table 10. Intel ® 41210 Bridge DC Voltage Specifications
3.1.2 Input Characteristic Signal Association
3.1.3 DC Input Characteristics
3.1.4 DC Characteristic Output Signal Association
Table 11. DC Characteristics Input Signal Association Table 12. DC Input Characteristics
3.3 V Signal
Table 13. DC Characteristic Output Signal Association
3.1.5 DC Output Characteristics
3.1.6 PCI Express Interface DC Specifications
3.1.6.1 Differential Transmitter (TX) DC Output Specifications
(TXs). The parameters are specified at the component pins. Table 14. DC Output Characteristic Table 15. Differential Transmitter (TX) DC Output Specifications (Sheet 1 of 2)
- Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 2,
- The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a
5 k 20k W TX DC High Impedance. All transmitters shall be AC coupled. transmitting component itself. Table 15. Differential Transmitter (TX) DC Output Specifications (Sheet 2 of 2)
3.1.6.2 Differential Receiver (RX) DC Input Specifications
parameters are specified at the component pins.
- Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 2,
not derived from the same clock chip the TX UI must be used as a reference for the eye diagram.
- The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB and a
- Impedance during all operating conditions.
- The Rx DC Common Mode Impedance that must be present when the receiver terminations are first enabled
- The Rx DC Common Mode Impedance that exists when the receiver terminations are disabled or when no
Table 16. Differential Receiver (RX) DC Input Specifications
0 V V
Impedance 80 100 120 W RX DC Differential Mode impedance.
diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit. be used as the interval for measuring the eye diagram.
3.1.6.3 Compliance Test and Measurement Load
measurement point is assumed to be the D+ and D-package pins. Figure 1. Minimum Transmitter Timing and Voltage Output Compliance Specification
3.1.6.4 PCI and PCI-X Interface DC Specifications
Table 17 summarizes the DC specifications for 3.3V signaling.
- This specification should be guarant eed by design. It is the minimum voltage to which pull-up resistors are
input buffer is conducting minimum current at this input voltage.
- Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
- Absolute maximum pin capacitance for a PCI/PCIX input except X_CLKIN and X_IDSEL.
- For conventional PCI only, lower capacitance on this input-only pin allows for non-resistive coupling to
Specification Revision 2.0a).
- For conventional PCI, this is a recommendation, not an absolute requirement. For PCI-X, this is a
- This input leakage is the maximum allowable leakage into the X_PME# open drain driver when power is
Table 17. DC Specifications for PCI and PCI-X 3.3 V Signaling
3.1.6.5 Input Clock DC Specifications
3.1.6.6 Output Clock DC Specifications
3.2 AC Specifications
3.2.1 PCI and PCI-X AC Characteristics
Table 18. DC Specification for Input Clock Signals Table 19. DC Specification for Output Clock Signals Table 20. Conventional PCI 3.3V AC Characteristics (Sheet 1 of 2)
- In conventional PCI switching, current characteristics for X_REQ# and X_GNT# are permitted to be one half
X_SERR# which is an open drain output.
- This parameter is to be interpreted as the cumulati ve edge rate across the specified range rather than the
- In conventional PCI switching, current characteristics for X_REQ# and X_GNT# are permitted to be one half
X_SERR#, which is an open drain output.
14 V / n s 2
Table 20. Conventional PCI 3.3V AC Characteristics (Sheet 2 of 2) Table 21. PCI-X 3.3V AC Characteristics
- This parameter is to be interpreted as the cumulative edge rate across the specified range rather than the
3.3 Voltage Filter Specifications
- Analog V oltage Filter (PCI-Express and PCI)
- Bandgap Filter Note: For filter specifications, refer to the 41210 Serial to Parallel PCI Bridge Design Guide.
3.4 VCC15 and VCC33 Voltage Requirements
cathode will be connected to VCC33. Figure 4. Voltage Requirements VCC33 versus VCC15
3.5 Timing Specifications
3.5.1 PCI Express Interface Timing
3.5.1.1 Differential Transmitter (TX) AC Output Specifications
(TXs). The parameters are specified at the component pins.
- No test load is necessarily associated with this value.
- Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 2,
jitter points on either side is approximately equal as opposed to the averaged time value. Table 22. Differential Transmitter (TX) AC Output Specifications Rise/Fall Time 0.125 UI See Notes 2 and 4. specifications within this time.
- Measured between 20-80% at Transmitter package pins into a test load as shown in Figure 2 for both VTX-D+
3.5.1.2 Differential Receiver (RX) AC Input Specifications
parameters are specified at the component pins.
- No test load is necessarily associated with this value.
- Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 2,
not derived from the same clock chip the TX UI must be used as a reference for the eye diagram.
- A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the
reference for the eye diagram. Table 23. Differential Receiver (RX) AC Input Specifications an unexpected idle condition. from the interconnect itself.
3.5.2 PCI and PCI-X Interface Timing
- It is important that all driven si gnal transitions drive to their Voh or Vol level within one Tcyc.
- Minimum times are measured at the package pin (not the test point) with the load circuit shown in the PCI-X
load circuit shown in the PCI-X Electrical and Mechanical Addendum, Revision 2.0a.
- X_REQ_[5:0]# and X_GNT_[5:0]# are point-to-point signals and have different input setup times than do
- See Section 3.5, “Timing Specifications” on page 28 and the measurement conditions in the PCI-X Electrical
and Mechanical Addendum, Revision 2.0a.
- If X_M66EN is asserted, CLK is stable when it meets the requirements in the PCI Local Bus Specification
Revision 2.3. RSTIN# is asserted and deasserted as ynchronously with respect to CLK.
- When X_M66EN is asserted, the minimum specification for T
to 1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when X_M66EN is deasserted.
- For purposes of active/float timing measurements, t he Hi-Z or “off” state is defined to be when the total
current delivered through the component pin is less t han or equal to the leakage current specification.
- Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at
the same time. Refer to the PCI Local Bus Specification Revision 2.3 for more details.
- Maximum value is also limited by delay to the first transaction (T rhff).
Table 24. PCI Interface Timing
66 MHz 33 MHz
- See the timing measurement conditions in Section 3.5, “Timing Specifications” on page 28.
- Minimum times are measured at the package pin (not the test point) with the load circuit shown in the PCI-X
load circuit shown in PCI-X Electrical and Mechanical Addendum, Revision 2.0a.
- See the timing measurement conditions in Section 3.5, “Timing Specifications” on page 28 and the PCI-X
Electrical and Mechanical Addendum, Revision 2.0a.
- RST# is asserted and deasserted asynchronously with respect to CLK.
- For purposes of Active/Float timing measurements, th e Hi-Z or "off" state is defined to be when the total
- Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at
- Maximum value is also limited by delay to the first transaction (T
PxFRAME# and must be floated no later than one clock before PxFRAME# is asserted.
- Device must meet this specification independent of how many outputs switch simultaneously.
Table 25. PCI-X 3.3V Signal Timing Parameters (Sheet 2 of 2)
3.5.3 PCI and PCI-X Clock Specification
spread-spectrum clocking specified in Table 26.
- For clock frequencies above 33 MHz, the clock frequency may not change beyond the spread-spectrum and
jitter limits except while RSTIN# is asserted.
- This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in the
- The minimum clock period must not be violated for any single clock cycle (i.e. accounting for all system jitter).
- Average Tcyc is measured over any 1 µs period of time and must include all sources of clock variation.
Figure 7. PCI-X 3.3V Clock Waveform Table 26. PCI and PCI-X Clock Timings
- Period jitter is the deviation between any single period of the clock, Tcyc, and the average period of the clock, Tcyc(average).
- Period, jitter, offset and skew measured on rising edge @ 1.5V for 3.3V clocks.
Table 27. 41210 Bridge Clock Timings
- The average period over any 1 us period of time must be gr eater than the minimum specified period. 3. Thigh is measured at 2.4V for non-host outputs. 4. Tlow is measured at 0.4V for all outputs. 5. For 3.3V clocks Trise and Tfall are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.4V (1 mA) JEDEC Specification. 6. Measured at crossing point. 7. Measured from V ol = 0.2V to Voh = 0.8V. 9. Determined as a fraction of 2*(T rise – Tfall) / (Trise + Tfall). 10.Period jitter is the deviation between any single period of the clock, Tcyc, and the average period of the clock, Tcyc(average).
3.5.4.1 Spread Spectrum Clocking
Spread spectrum clocking can be used on the 41210 Bridge to reduce energy. Spread Spectrum clocking is a common technique used by system designers to meet FCC emissions, where the frequency is deliberately shifted around to spread the energy off of the peak. The following is to be observed when using Spread Spectrum clocking:
- All device timings (including jitter, skew, min/max clock period, output rise/fall time) MUST meet the existing non-spread spectrum specifications
- All non-spread Host and PCI functionality must be maintained in the spread spectrum mode (includes all power management functions.)
- The minimum clock period cannot be violated. The preferred method is to adjust the spread technique to not allow for modulation above the nominal frequency. This technique is often called “down-spreading”. The modulation profile in a modulation period can be expressed as: Equations: where: f nom is the nominal frequency in the non-SSC mode fm is the modulation frequency fm is the modulation amount t is time. 3.6 41210 Bridge Power Consumption Table 28 provides details on the maximum draw from the power planes by the 41210 Bridge for use in voltage regulation. , )( ; )( mm nommnom m nommnom f 1tf2 1when tff2f1 1t0when tff2f1 f δδ δδ
Table 28. 41210 Bridge Maximum Voltage Plane Currents Bridge for use in thermal design. Table 29. 41210 Bridge Thermal Voltage Plane Currents
3.7 Power Delivery Guidelines
Please refer to the Intel® 41210 Serial to Parallel PCI Bridge Design Guide.
3.8 Reference and Compensation Pins
- PE_RCOMP[1:0] are two separate pins that provide voltage compensation for the PCI Express interface on the 41210 Bridge. The nominal compensation voltage is 0.5V . An external 24.9 ±1% pull-up resistor should be used to connect to VCC15. A single pull-up resistor can be used to for both of these signals. Power Plane Maximum Voltage Plane Current (Amps) Frequency (MHz) 133 100 66 Number of Slots 1 2 4 IVCC15 (core 1.5V) 1.68 1.61 1.55 IVCC15 (I/O 1.5V) 0.22 0.22 0.22 VCCBGPE 0.005 0.005 0.005 IVCCPE (PCI Express 1.5V) 0.70 0.70 0.70 IVCC33 (PCI/PCI-X Mode 1 3.3V) 1 1. Per PCI-X Bus segment 1.05 1.14 1.22 Power Plane Thermal Voltage Plane Current (Amps) Frequency (MHz) 133 100 66 Number of Slots 1 2 4 IVCC15 (core 1.5V) 1.24 1.18 1.11 IVCC15 (I/O 1.5V) 0.22 0.22 0.22 VCCBGPE 0.005 0.005 0.005 IVCCPE (PCI Express 1.5V) 0.69 0.69 0.69 IVCC33 (PCI/PCI-X Mode 1 3.3V) 1 1. Per PCI-X Bus segment 0.99 1.04 1.10
- RCOMP is an analog PCI interface compensation pin to the 41210 Bridge. A 100 ±1% pull- down resistor should be used to connect the RCOMP pin to ground. All three of these implementations are shown in Figure 8.
Figure 8. 41210 Bridge Reference and Compensation Circuit Implementations
3.9 Thermal Specifications
3.9.1 Power
heatsink when using the 41210 Bridge component.
3.9.2 Die Temperature
Table 30. 41210 Bridge Thermal Specifications
3.9.3 Thermal Solution Component Suppliers
3.9.3.1 Torsional Clip Heatsink Thermal Solution
directly to verify time of component availability.
4.1 Package Specification
pitch (see Figure 9 and Figure 10). Figure 9. 41210 Bridge Package Dimensions (Top View)
Figure 10. 41210 Bridge Package Dimensions (Side View) Note: Primary datum -C- and seating plane are defined by the spherical crowns of the solder balls.
4.2 Ball Map
/K42/K33/K35/K35/K32/K2D/K30/K31 /K41/K44 /K32/K33/K32/K34 /K32/K32 /K32/K31 /K32/K30 /K31/K39 /K31/K38 /K31/K37 /K31/K36 /K31/K35 /K31/K34 /K31/K33 /K32/K33/K32/K34 /K32/K32 /K32/K31 /K32/K30 /K31/K39 /K31/K38 /K31/K37 /K31/K36 /K31/K35 /K31/K34 /K31/K33 /K41/K43 /K41/K42 /K41/K41 /K59 /K57 /K56 /K55 /K54 /K52 /K50 /K4E /K4D /K4C /K4B /K4A /K48 /K47 /K46 /K45 /K44 /K43 /K42 /K41 /K52/K45/K53 /K45/K52/K56/K45/K44 /K32 /K41/K5F /K50/K43/K49/K58 /K43/K41/K50 /K50/K45/K5F /K52/K43/K4F/K4D/K50 /K5B/K30/K5D /K52/K45/K53 /K45/K52/K56/K45/K44 /K31 /K52/K45/K53 /K45/K52/K56/K45/K44 /K33 /K52/K45/K53 /K45/K52/K56/K45/K44 /K34 /K41/K5F /K43/K4C/K4B/K49/K4E /K41/K5F /K43/K4C/K4B/K4F /K5B/K34/K5D /K41/K5F /K43/K4C/K4B/K4F /K5B/K30/K5D /K41/K5F /K43/K4C/K4B/K4F /K5B/K36/K5D /K41/K5F /K43/K4C/K4B/K4F /K5B/K31/K5D /K41/K5F /K43/K4C/K4B/K4F /K5B/K32/K5D /K41/K5F /K41/K43/K4B/K36/K34/K23 /K41/K5F /K52/K45/K51/K36/K34/K23 /K41/K5F /K43/K4C/K4B/K4F /K5B/K33/K5D /K41/K5F /K43/K4C/K4B/K4F /K5B/K35/K5D /K50/K45/K54/K4E /K5B/K32/K5D /K50/K45/K54/K50 /K5B/K32/K5D /K50/K45/K54/K4E /K5B/K30/K5D /K50/K45/K54/K50 /K5B/K33/K5D /K50/K45/K54/K4E /K5B/K33/K5D /K41/K5F /K43/K42/K45/K34/K23 /K41/K5F /K4D/K36/K36/K45/K4E /K41/K5F /K43/K42/K45/K36/K23 /K41/K5F /K43/K42/K45/K35/K23 /K41/K5F /K47/K4E/K54/K31/K23 /K41/K5F /K50/K41/K52/K36/K34 /K41/K5F /K43/K42/K45/K37/K23 /K50/K45/K54/K50 /K5B/K30/K5D /K50/K45/K54/K4E /K5B/K31/K5D /K50/K45/K54/K50 /K5B/K31/K5D /K42/K5F /K53/K54/K52/K41/K50/K34 /K42/K5F /K53/K54/K52/K41/K50/K30 /K41/K5F /K53/K54/K52/K41/K50/K32 /K41/K5F /K53/K54/K52/K41/K50/K33 /K41/K5F /K53/K54/K52/K41/K50/K30 /K41/K5F /K53/K54/K52/K41/K50/K35 /K41/K5F /K53/K54/K52/K41/K50/K36 /K41/K5F /K53/K54/K52/K41/K50/K31 /K52/K45/K46 /K43/K4C/K4B/K4E /K52/K45/K46 /K43/K4C/K4B/K50 /K42/K5F /K53/K54/K52/K41/K50/K33 /K50/K45/K52/K50 /K5B/K31/K5D /K50/K45/K52/K50 /K5B/K32/K5D /K50/K45/K52/K50 /K5B/K30/K5D /K50/K45/K52/K4E /K5B/K31/K5D /K50/K45/K52/K4E /K5B/K32/K5D /K50/K45/K52/K4E /K5B/K30/K5D /K53/K4D/K42/K55/K53 /K5B/K33/K5D /K43/K46/K47 /K52/K53/K54/K23 /K53/K4D/K42/K55/K53 /K5B/K35/K5D /K53/K4D/K42/K55/K53 /K5B/K31/K5D /K52/K53/K54/K49/K4E/K23 /K53/K4D/K42/K55/K53 /K5B/K32/K5D /K9/K41 /K5F /K54/K45/K53/K54/K32 /K9/K41 /K5F /K54/K45/K53/K54/K31 /K50/K45/K52/K53/K54/K23 /K41/K5F/K4E/K43/K32 /K41/K5F/K4E/K43/K33 /K41/K5F/K4E/K43/K36 /K41/K5F/K4E/K43/K38 /K41/K5F/K4E/K43/K37 /K41/K5F/K4E/K43/K35 /K4E/K43/K31/K32 /K4E/K43/K31/K31 /K41/K5F/K4E/K43/K39/K41/K5F/K4E/K43/K34 /K4E/K43/K36 /K4E/K43/K31 /K41/K5F /K4E/K43/K31/K30 /K41/K5F/K4E/K43/K31 /K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33/K56/K43/K43/K33/K33/K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33/K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33 /K4E/K43/K33 /K41/K5F /K41/K44/K5B/K34/K39/K5D /K41/K5F /K41/K44/K5B/K36/K33/K5D /K41/K5F /K41/K44/K5B/K36/K32/K5D /K41/K5F /K41/K44/K5B/K36/K31/K5D /K41/K5F /K41/K44/K5B/K36/K30/K5D /K41/K5F /K41/K44/K5B/K35/K36/K5D /K41/K5F /K41/K44/K5B/K35/K37/K5D /K41/K5F /K41/K44/K5B/K34/K33/K5D /K41/K5F /K41/K44/K5B/K35/K38/K5D /K41/K5F /K41/K44/K5B/K33/K38/K5D /K41/K5F /K41/K44/K5B/K33/K39/K5D /K41/K5F /K41/K44/K5B/K33/K36/K5D /K41/K5F /K41/K44/K5B/K33/K37/K5D /K41/K5F /K41/K44/K5B/K35/K33/K5D /K41/K5F /K41/K44/K5B/K35/K32/K5D /K41/K5F /K41/K44/K5B/K35/K34/K5D /K41/K5F /K50/K45/K52/K52/K23 /K41/K5F /K53/K45/K52/K52/K23 /K41/K5F /K43/K42/K45/K33/K23 /K41/K5F /K43/K42/K45/K32/K23 /K41/K5F /K41/K44/K5B/K33/K34/K5D /K41/K5F /K41/K44/K5B/K33/K35/K5D /K41/K5F /K41/K44/K5B/K31/K37/K5D /K41/K5F /K41/K44/K5B/K31/K39/K5D /K41/K5F /K41/K44/K5B/K32/K32/K5D /K41/K5F /K41/K44/K5B/K32/K33/K5D /K41/K5F /K41/K44/K5B/K32/K39/K5D /K41/K5F /K41/K44/K5B/K31/K32/K5D /K41/K5F /K41/K44/K5B/K39/K5D /K41/K5F /K41/K44/K5B/K31/K31/K5D /K41/K5F /K41/K44/K5B/K31/K33/K5D /K41/K5F /K41/K44/K5B/K31/K30/K5D /K41/K5F /K41/K44/K5B/K31/K34/K5D /K41/K5F /K41/K44/K5B/K31/K35/K5D /K41/K5F /K41/K44/K5B/K32/K37/K5D /K41/K5F /K41/K44/K5B/K32/K38/K5D /K41/K5F /K41/K44/K5B/K33/K31/K5D /K41/K5F /K41/K44/K5B/K32/K36/K5D /K41/K5F /K41/K44/K5B/K32/K31/K5D /K41/K5F /K41/K44/K5B/K31/K38/K5D /K41/K5F /K41/K44/K5B/K33/K30/K5D /K41/K5F /K41/K44/K5B/K32/K35/K5D /K41/K5F /K41/K44/K5B/K31/K36/K5D /K41/K5F /K47/K4E/K54/K32/K23 /K41/K5F /K47/K4E/K54/K33/K23 /K41/K5F /K47/K4E/K54/K34/K23 /K41/K5F /K43/K42/K45/K31/K23 /K41/K5F /K43/K42/K45/K30/K23 /K41/K5F /K50/K41/K52 /K41/K5F /K47/K4E/K54/K30/K23 /K41/K5F /K41/K44/K5B/K33/K32/K5D /K41/K5F /K41/K44/K5B/K33/K33/K5D /K41/K5F /K41/K44/K5B/K35/K31/K5D /K41/K5F /K41/K44/K5B/K35/K30/K5D /K41/K5F /K4C/K4F/K43/K4B/K23 /K41/K5F /K41/K44/K5B/K35/K35/K5D /K41/K5F /K41/K44/K5B/K35/K39/K5D /K41/K5F /K41/K44/K5B/K34/K37/K5D /K41/K5F /K41/K44/K5B/K34/K36/K5D /K41/K5F /K41/K44/K5B/K34/K38/K5D /K50/K45/K5F /K52/K43/K4F/K4D/K50 /K5B/K31/K5D /K56/K53/K53 /K41/K5F /K49/K4E/K54/K44/K23 /K41/K5F /K49/K4E/K54/K42/K23 /K41/K5F /K49/K4E/K54/K41/K23 /K41/K5F /K49/K4E/K54/K43/K23 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53/K56/K53/K53/K56/K53/K53 /K4E/K43/K31/K33 /K4E/K43/K31/K35 /K4E/K43/K31/K37 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53/K56/K53/K53 /K56/K53/K53 /K56/K53/K53/K56/K53/K53 /K56/K53/K53/K56/K53/K53 /K41/K5F /K47/K4E/K54/K35/K23 /K41/K5F /K44/K45/K56 /K53/K45/K4C/K23 /K41/K5F /K54/K52/K44/K59/K23/K56/K53/K53 /K56/K53/K53 /K41/K5F /K53/K54/K4F/K50/K23 /K56/K53/K53 /K56/K53/K53 /K41/K5F /K52/K45/K51/K34/K23 /K41/K5F /K52/K45/K51/K32/K23 /K41/K5F /K52/K45/K51/K35/K23 /K41/K5F /K52/K45/K51/K30/K23 /K41/K5F /K52/K45/K51/K31/K23 /K41/K5F /K31/K33/K33/K45/K4E /K41/K5F /K50/K4D/K45/K23 /K41/K5F /K46/K52/K41/K4D/K45/K23 /K41/K5F /K49/K52/K44/K59/K23 /K41/K5F /K52/K45/K51/K33/K23 /K41/K5F /K52/K53/K54/K23 /K41/K5F /K41/K44/K5B/K34/K32/K5D /K41/K5F /K41/K44/K5B/K34/K30/K5D /K41/K5F /K41/K44/K5B/K34/K31/K5D /K56/K53/K53 /K56/K53/K53/K56/K53/K53 /K56/K53/K53 /K56/K53/K53/K56/K53/K53 /K41/K5F /K41/K44/K5B/K34/K35/K5D /K41/K5F /K41/K44/K5B/K34/K34/K5D /K56/K53/K53 /K56/K43/K43/K31/K35 /K56/K43/K43/K31/K35 /K56/K53/K53 /K56/K43/K43/K31/K35 /K56/K53/K53 /K56/K43/K43/K31/K35 /K56/K53/K53 /K56/K43/K43/K31/K35 /K56/K43/K43/K31/K35 /K56/K53/K53 /K56/K53/K53 /K56/K43/K43/K31/K35 /K56/K53/K53 /K56/K43/K43/K31/K35 /K56/K53/K53 /K56/K43/K43/K31/K35 /K56/K43/K43/K31/K35 /K56/K53/K53/K56/K53/K53/K56/K53/K53 /K56/K53/K53/K56/K43/K43/K31/K35 /K56/K53/K53 /K56/K43/K43/K31/K35 /K56/K43/K43/K31/K35 /K56/K43/K43/K31/K35 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K43/K43/K31/K35 /K56/K43/K43/K31/K35 /K56/K53/K53 /K56/K53/K53 /K56/K43/K43/K31/K35 /K56/K43/K43/K31/K35 /K56/K53/K53 /K42/K47/K50/K45 /K56/K53/K53 /K41/K50/K45 /K56/K43/K43 /K41/K50/K45 /K56/K43/K43 /K41/K50/K43/K31/K33 /K56/K43/K43 /K42/K47/K50/K45 /K56/K43/K43/K50/K45 /K56/K43/K43/K50/K45 /K56/K43/K43/K50/K45 /K56/K43/K43/K50/K45 /K41/K5F /K41/K44/K5B/K37/K5D /K41/K5F /K41/K44/K5B/K35/K5D /K41/K5F /K41/K44/K5B/K36/K5D /K41/K5F /K41/K44/K5B/K34/K5D /K41/K5F /K41/K44/K5B/K31/K5D /K41/K5F /K41/K44/K5B/K32/K5D /K41/K5F /K41/K44/K5B/K30/K5D /K41/K5F /K41/K44/K5B/K32/K34/K5D /K41/K5F /K41/K44/K5B/K38/K5D /K41/K5F /K41/K44/K5B/K32/K30/K5D /K41/K5F /K41/K44/K5B/K33/K5D
Datasheet — 41210 Bridge /K42/K33/K35/K35/K33/K2D/K30/K31 /K41/K44 /K31/K31/K31/K32 /K31/K30 /K39 /K38 /K37 /K36 /K35 /K34 /K33 /K32 /K31 /K31/K31/K31/K32 /K31/K30 /K39 /K38 /K37 /K36 /K35 /K34 /K33 /K32 /K31 /K41/K43 /K41/K42 /K41/K41 /K59 /K57 /K56 /K55 /K54 /K52 /K50 /K4E /K4D /K4C /K4B /K4A /K48 /K47 /K46 /K45 /K44 /K43 /K42 /K41 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53/K56/K53/K53/K56/K53/K53 /K42/K5F/K41/K44 /K5B/K31/K5D /K42/K5F/K41/K44 /K5B/K30/K5D /K42/K5F/K41/K44 /K5B/K32/K5D /K56/K53/K53/K56/K43/K43/K33/K33 /K56/K53/K53/K56/K53/K53 /K56/K53/K53 /K4E/K43/K31/K30 /K4E/K43/K31/K36 /K42/K5F /K47/K4E/K54/K30/K23 /K56/K53/K53 /K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33 /K54/K52/K53/K54/K23 /K56/K53/K53/K56/K43/K43/K50/K45/K56/K43/K43/K50/K45 /K56/K43/K43/K50/K45 /K56/K53/K53/K56/K53/K53/K56/K53/K53 /K56/K53/K53 /K54/K44/K49 /K42/K5F /K4E/K43/K31 /K42/K5F /K4E/K43/K34 /K42/K5F /K4E/K43/K39 /K42/K5F /K4E/K43/K32 /K42/K5F /K4E/K43/K33 /K42/K5F /K4E/K43/K36 /K42/K5F /K4E/K43/K35 /K53/K4D/K42 /K44/K41/K54 /K53/K4D/K42 /K43/K4C/K4B /K56/K53/K53/K56/K53/K53/K56/K53/K53 /K56/K53/K53 /K52/K45/K53 /K45/K52/K56/K45/K44 /K38 /K52/K45/K53 /K45/K52/K56/K45/K44 /K37 /K52/K45/K53 /K45/K52/K56/K45/K44 /K36 /K52/K45/K53 /K45/K52/K56/K45/K44 /K35 /K56/K53/K53/K56/K53/K53/K56/K53/K53 /K4E/K43/K34 /K42/K5F /K4E/K43/K37 /K4E/K43/K31/K38 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53/K56/K53/K53/K56/K53/K53 /K56/K53/K53 /K42/K5F/K41/K44 /K5B/K31/K31/K5D /K42/K5F/K41/K44 /K5B/K31/K33/K5D /K42/K5F/K41/K44 /K5B/K31/K39/K5D /K42/K5F /K52/K45/K51/K32/K23 /K56/K43/K43 /K41/K50/K43/K31/K32 /K56/K43/K43 /K41/K50/K43/K31/K31 /K42/K5F /K50/K4D/K45/K23 /K42/K5F /K43/K42/K45/K32/K23 /K42/K5F/K41/K44 /K5B/K31/K37/K5D /K42/K5F/K41/K44 /K5B/K31/K36/K5D /K42/K5F/K41/K44 /K5B/K32/K33/K5D /K42/K5F/K41/K44 /K5B/K32/K39/K5D /K42/K5F /K43/K4C/K4B/K4F/K5B/K30/K5D /K42/K5F /K43/K4C/K4B/K4F/K5B/K34/K5D /K42/K5F /K43/K4C/K4B/K4F/K5B/K32/K5D /K42/K5F /K43/K4C/K4B/K4F/K5B/K35/K5D /K42/K5F /K43/K4C/K4B/K4F/K5B/K33/K5D /K42/K5F /K43/K4C/K4B/K4F/K5B/K36/K5D /K42/K5F /K43/K4C/K4B/K49/K4E /K42/K5F /K53/K54/K52/K41/K50/K33 /K42/K5F /K43/K4C/K4B/K4F/K5B/K31/K5D /K42/K5F /K47/K4E/K54/K34/K23 /K42/K5F/K41/K44 /K5B/K32/K35/K5D /K42/K5F /K47/K4E/K54/K32/K23 /K42/K5F/K41/K44 /K5B/K33/K30/K5D /K42/K5F/K41/K44 /K5B/K32/K31/K5D /K42/K5F/K41/K44 /K5B/K32/K32/K5D /K42/K5F/K41/K44 /K5B/K32/K36/K5D /K42/K5F/K41/K44 /K5B/K32/K37/K5D /K42/K5F /K53/K54/K4F/K50/K23 /K42/K5F /K53/K45/K52/K52/K23 /K42/K5F /K44/K45/K56/K53/K45/K4C/K23 /K42/K5F /K52/K45/K51/K33/K23 /K42/K5F /K41/K44/K5B/K33/K32/K5D /K42/K5F /K41/K44/K5B/K33/K34/K5D /K42/K5F /K41/K44/K5B/K33/K33/K5D /K42/K5F /K41/K44/K5B/K33/K35/K5D /K42/K5F /K41/K44/K5B/K33/K36/K5D /K42/K5F /K41/K44/K5B/K35/K30/K5D /K42/K5F /K41/K44/K5B/K35/K31/K5D /K42/K5F /K31/K33/K33/K45/K4E /K42/K5F /K41/K44/K5B/K34/K30/K5D /K42/K5F /K41/K44/K5B/K33/K39/K5D /K42/K5F /K41/K44/K5B/K35/K35/K5D /K42/K5F /K41/K44/K5B/K35/K34/K5D /K42/K5F /K52/K45/K51/K30/K23 /K42/K5F /K47/K4E/K54/K35/K23 /K42/K5F /K41/K44/K5B/K35/K36/K5D /K42/K5F /K41/K44/K5B/K34/K32/K5D /K42/K5F /K41/K44/K5B/K34/K31/K5D /K42/K5F /K41/K44/K5B/K35/K38/K5D /K42/K5F /K41/K44/K5B/K35/K39/K5D /K42/K5F /K47/K4E/K54/K31/K23 /K42/K5F /K41/K44/K5B/K34/K35/K5D /K42/K5F /K41/K44/K5B/K34/K36/K5D /K42/K5F /K41/K44/K5B/K36/K30/K5D /K42/K5F /K41/K44/K5B/K36/K31/K5D /K42/K5F /K41/K44/K5B/K34/K33/K5D /K42/K5F /K41/K44/K5B/K34/K34/K5D /K42/K5F /K41/K44/K5B/K34/K39/K5D /K42/K5F /K41/K44/K5B/K34/K38/K5D /K42/K5F /K41/K44/K5B/K36/K32/K5D /K42/K5F /K41/K44/K5B/K36/K33/K5D /K42/K5F /K43/K42/K45/K35/K23 /K50/K45/K52/K50 /K5B/K33/K5D /K42/K5F /K41/K44/K5B/K34/K37/K5D /K42/K5F /K49/K4E/K54/K42/K23 /K42/K5F /K49/K4E/K54/K41/K23 /K42/K5F /K49/K4E/K54/K43/K23 /K42/K5F /K4E/K43/K35 /K42/K5F /K4E/K43/K38 /K42/K5F /K4E/K43/K31/K30 /K42/K5F /K4E/K43/K37 /K42/K5F /K4E/K43/K39 /K42/K5F /K4E/K43/K38 /K50/K45/K52/K50 /K5B/K37/K5D /K50/K45/K52/K4E /K5B/K36/K5D /K50/K45/K54/K4E /K5B/K37/K5D /K50/K45/K54/K50 /K5B/K37/K5D /K42/K5F /K43/K42/K45/K36/K23 /K42/K5F /K43/K42/K45/K37/K23 /K42/K5F /K43/K42/K45/K34/K23 /K50/K45/K52/K4E /K5B/K37/K5D /K50/K45/K52/K4E /K5B/K33/K5D /K42/K5F /K41/K44/K5B/K35/K37/K5D /K50/K45/K54/K4E /K5B/K36/K5D /K50/K45/K54/K4E /K5B/K34/K5D /K42/K5F /K54/K45/K53/K54/K32 /K42/K5F /K54/K45/K53/K54/K31 /K50/K45/K54/K50 /K5B/K36/K5D /K50/K45/K54/K50 /K5B/K34/K5D /K50/K45/K54/K4E /K5B/K35/K5D /K50/K45/K54/K50 /K5B/K35/K5D /K42/K5F /K50/K43/K49/K58 /K43/K41/K50 /K50/K45/K52/K4E /K5B/K35/K5D /K50/K45/K52/K50 /K5B/K34/K5D /K50/K45/K52/K4E /K5B/K34/K5D /K42/K5F /K49/K4E/K54/K44/K23 /K50/K45/K52/K50 /K5B/K35/K5D /K42/K5F /K41/K44/K5B/K33/K35/K5D /K42/K5F /K41/K44/K5B/K33/K35/K5D /K42/K5F /K41/K44/K5B/K35/K32/K5D /K52/K5F /K52/K53/K54/K23 /K42/K5F /K41/K44/K5B/K35/K33/K5D /K42/K5F /K50/K45/K52/K52/K23 /K42/K5F /K46/K52/K41/K4D/K45/K23 /K42/K5F /K49/K52/K44/K59/K23 /K42/K5F /K4D/K36/K36/K45/K4E /K42/K5F /K4C/K4F/K43/K4B/K23 /K42/K5F /K54/K52/K44/K59/K23 /K42/K5F/K41/K44 /K5B/K32/K34/K5D /K42/K5F/K41/K44 /K5B/K32/K38/K5D /K42/K5F/K41/K44 /K5B/K33/K31/K5D /K42/K5F /K47/K4E/K54/K33/K23 /K42/K5F /K52/K45/K51/K35/K23 /K42/K5F /K52/K45/K51/K34/K23 /K42/K5F/K41/K44 /K5B/K36/K5D /K42/K5F/K41/K44 /K5B/K37/K5D /K42/K5F/K41/K44 /K5B/K31/K30/K5D /K42/K5F/K41/K44 /K5B/K31/K32/K5D /K42/K5F/K41/K44 /K5B/K31/K35/K5D /K42/K5F /K50/K41/K52 /K42/K5F /K50/K41/K52/K36/K34 /K42/K5F/K41/K44 /K5B/K31/K34/K5D /K42/K5F/K41/K44 /K5B/K34/K5D /K42/K5F /K43/K42/K45/K30/K23 /K42/K5F /K52/K45/K51/K36/K34/K23 /K42/K5F /K41/K43/K4B/K36/K34/K23 /K42/K5F/K41/K44 /K5B/K35/K5D /K42/K5F/K41/K44 /K5B/K39/K5D /K42/K5F/K41/K44 /K5B/K33/K5D /K42/K5F /K52/K45/K51/K31/K23 /K42/K5F /K43/K42/K45/K31/K23 /K42/K5F/K41/K44 /K5B/K38/K5D /K56/K53/K53/K56/K53/K53 /K56/K43/K43/K31/K35/K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K43/K43/K31/K35 /K56/K43/K43/K31/K35/K56/K43/K43/K31/K35 /K56/K53/K53 /K42/K5F /K53/K54/K52/K41/K50/K34 /K42/K5F /K53/K54/K52/K41/K50/K31 /K42/K5F /K53/K54/K52/K41/K50/K36 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53/K56/K53/K53/K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K43/K46/K47 /K52/K45/K54/K52/K59 /K4E/K43/K31/K39 /K4E/K43/K32 /K54/K43/K4B /K42/K5F /K53/K54/K52/K41/K50/K35 /K56/K43/K43/K50/K45 /K56/K43/K43/K50/K45 /K50/K45/K52/K50 /K5B/K36/K5D /K56/K53/K53 /K56/K53/K53 /K56/K43/K43/K31/K35 /K56/K43/K43/K31/K35 /K56/K43/K43/K31/K35 /K4E/K43/K31/K34/K56/K43/K43/K31/K35 /K56/K43/K43/K31/K35/K56/K43/K43/K31/K35 /K56/K43/K43/K31/K35 /K56/K43/K43/K31/K35/K56/K43/K43/K31/K35 /K56/K43/K43/K31/K35 /K56/K53/K53 /K56/K53/K53 /K54/K44/K4F /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K54/K4D/K53/K56/K53/K53/K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K53/K53 /K56/K43/K43/K31/K35/K56/K43/K43/K33/K33 /K42/K5F/K41/K44 /K5B/K32/K30/K5D /K42/K5F/K41/K44 /K5B/K31/K38/K5D /K42/K5F /K69/K33/K23 /K56/K43/K43/K33/K33/K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33/K56/K43/K43/K31/K35 /K52/K43/K4F/K4D/K50 /K56/K43/K43/K33/K33/K56/K43/K43/K31/K35/K56/K53/K53 /K56/K43/K43/K31/K35 /K56/K43/K43/K33/K33 /K56/K43/K43/K33/K33
4.3 Signal List, sorted by Ball Location
Table 31. Signal List, sorted by Ball Name (Sheet 1 of 4)
Table 31. Signal List, sorted by Ball Name (Sheet 2 of 4)
Table 31. Signal List, sorted by Ball Name (Sheet 3 of 4)
Table 31. Signal List, sorted by Ball Name (Sheet 4 of 4)
4.4 Signal List, sorted by Signal Name
Table 32. Signal List, sorted by Signal Name (Sheet 1 of 4)
Table 32. Signal List, sorted by Signal Name (Sheet 2 of 4)
Table 32. Signal List, sorted by Signal Name (Sheet 3 of 4)
Table 32. Signal List, sorted by Signal Name (Sheet 4 of 4)
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