410 INTEL | Alldatasheet
Document overview
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- PDF pages: 71
Technical content
Datasheet sections
- 1.1 Terminology
- 1.2 References
- 2 Low Power Features
- 2.1 Clock Control and Low Power States
- 2.1.1 Core Low-Power States
- 2.1.2 Package Low Power States
- 2.2 FSB Low Power Enhancements
- 2.3 Processor Power Status Indicator (PSI#) Signal
- 3 Electrical Specifications
- 3.1 FSB (Front Side Bus) and GTLREF
- 3.2 Power and Ground Pins
- 3.3 Decoupling Guidelines
- 3.3.1 VCC
- 3.3.2 FSB AGTL+ Decoupling
- 3.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking
- 3.4 Voltage Identification and Power Sequencing
- 3.5 Catastrophic Thermal Protection
- 3.6 Signal Terminations and Unused Pins
- 3.7 FSB Frequency Select Signals (BSEL[2:0])
- 3.8 FSB Signal Groups
- 3.9 CMOS Signals
- 3.10 Maximum Ratings
- 3.11 Processor DC Specifications
- 4 Package Mechanical Specific ations and Pin Information
- 4.1 Processor Component Keep-Out Zones
- 4.2 Package Loading Specifications
- 4.3 Processor Mass Specifications
- 4.4 Processor Pinout and Pin List
- 4.5 Alphabetical Signals Reference
- 5 Thermal Specifications and Design Considerations
- 5.1 Thermal Specifications
- 5.1.1 Thermal Diode
- 5.1.2 Thermal Diode Offset
- 5.1.3 Intel® Thermal Monitor
- 5.1.4 Digital Thermal Sensor
- 5.1.5 Out of Specification Detection
- 5.1.6 PROCHOT# Signal Pin
Document Number: 312726-004 Intel® Celeron® M Processor on 65 nm Process Datasheet January 2007
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Celeron® M processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Intel, Celeron, Pentium, MMX, and the Intel logo are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States and other countries. * Other brands and names are the property of their respective owners. Copyright © 2006 – 2007, Intel Corporation. All rights reserved.
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1 Coordination of Core-Level Low Power States at the Package Level for the Celeron M
21 Thermal Diode n
Revision History
-001 Initial release April 2006 -002
- Chapter 3, “Electrical Specifications” — Added 440 and 450 processor specifications to Table 6.
- Chapter 5, “Thermal Specifications and Design Considerations” — Added power specifications for the 440 and 450 processor to Table 16. September 2006 -003 • Corrected page numbering in Chapter 5 September 2006 -004
- Chapter 3, “Electrical Specifications” — Added 443 ULV processor specifications to Table 7.
- Chapter 5, “Thermal Specifications and Design Considerations”
- Added power specifications for the 443 ULV processor to Table 17. January 2007
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1 Introduction
The Intel® Celeron® M processor based on 65 nm process technology is a high- performance, low-power mobile processor with several enhancements over previous mobile Celeron processors. Throughout this document, the term “Celeron M processor” refers to the Intel® Celeron® M processor based on 65 nm process technology. This document contains specifications for both the Intel® Celeron® M processor 450, 440, 430, 420, 410 and Intel® Celeron® M processor Ultra Low Voltage 443 and 423Δ. Note: ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. The following list provides some of the key features on this processor:
- On-die, 1-MB second level cache with Advanced Transfer Cache Architecture
- Supports Intel Architecture with Dynamic Execution
- On-die, primary 32-kB instruction cache and 32-kB write-back data cache
- Data Prefetch Logic
- Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3)
- The Celeron M processor and the Celeron M processor Ultra Low Voltage are offered at 533-MHz FSB
- Digital Thermal Sensor
- The Celeron M is a single core processor offered in both Micro-FCPGA and Micro- FCBGA packages
- The Celeron M processor Ultra Low Voltage is a single core processor offered only in a Micro-FCBGA package
- Execute Disable Bit support for enhanced security The Celeron M processor will be manufactured on Intel’s 65 nanometer process technology with copper interconnect. The processor maintains support for MMX™ technology, Streaming SIMD instructions, and full compatibility with IA-32 software. The Celeron M processor features on-die, 32-kB level 1 instruction and data caches and a 1-MB level 2 cache with Advanced Transfer Cache Architecture. The processor’s Data Prefetch Logic speculatively fetches data to the L2 cache before the L1 cache requests occurs, resulting in reduced bus cycle penalties. The Celeron M processor includes the Data Cache Unit Streamer which enhances the performance of the L2 prefetcher by requesting L1 warm-ups earlier. In addition, the Writer Order Buffer depth is enhanced to help with the write-back latency performance. In addition to supporting the existing Streaming SIMD Extensions 2 (SSE2), there are 13 new instructions which further extend the capabilities of Intel processor technology. These new instructions are called Streaming SIMD Extensions 3 (SSE3). 3D graphics and other entertainment applications such as gaming will have the opportunity to take advantage of these new instructions as platforms with the Celeron M processor based on 65 nm process and SSE3 become available in the market place. The Celeron M processor’s front side bus (FSB) utilizes a split-transaction, deferred reply protocol. The FSB uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock. The 4X data bus can deliver data four times per bus clock and is referred as “quad-pumped” or 4X data
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bus, the address bus can deliver addresses two times per bus clock and is referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and the 2X address bus provide a data bus bandwidth of up to 4.26 GB/second. The FSB uses Advanced Gunning Transceiver Logic (AGTL+) signaling technology, a variant of GTL+ signaling technology with low power enhancements. The processor features the Auto Halt, Stop Grant and Deep Sleep low power C-states. The Celeron M processor utilizes socketable Micro Flip-Chip Pin Grid Array (Micro- FCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount, Zero Insertion Force (ZIF) socket, which is referred to as the mPGA479M socket. Celeron M processor supports the Execute Disable Bit capability. This feature combined with a support operating system allows memory to be marked as executable or non executable. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the IA-32 Intel® Architecture Software Developer's Manual for more detailed information.
1.1 Terminology
A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level). XXXX means that the specification or value is yet to be determined. Front Side Bus (FSB) Refers to the interface between the processor and system core logic (also known as the chipset components). AGTL+ Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+ signaling technology on some Intel processors.
1.2 References
Intel® Celeron® M Processor Specification Update 300303 Mobile Intel® 945 Express Chipset Family Datasheet 309219 Mobile Intel® 945 Express Chipset Family Specification Update 309220 Intel® I/O Controller Hub 7 (ICH7) Family Datasheet 307013 Intel® I/O Controller Hub 7 (ICH7) Family Specification Update 307014 IA-32 Intel® Architecture Software Developer's Manual http:// www.intel.com/ design/ pentium4/ manuals/ index_new.htm Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A- M Volume 2B: Instruction Set Reference. N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide AP-485, Intel® Processor Identification and CPUID Instruction Application Note 241618
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2 Low Power Features
2.1 Clock Control and Low Power States
system logic that the processor should return to the Normal state. Table 1. Coordination of Core-Level Low Power States at the Package Level for the Figure 1. Package-Level Low Power States
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2.1.1 Core Low-Power States
2.1.1.1 C0 State
This is the normal operating state for the core of the Celeron M processor.
2.1.1.2 C1/AutoHALT Powerdown State
processor to immediately initialize itself. Developer's Manual, Volume 3A/3B: System Programmer's Guide for more information. will return execution to the HALT state. process the snoop and then return to the AutoHALT Powerdown state. Figure 2. Core Low Power States † — STPCLK# assertion and de-assertion have no affect if a core is in C2, or C3.
2.1.1.3 C1/MWAIT Powerdown State
MWAIT is a low power state entered when the processor core executes the MWAIT instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that there is an additional event that can cause the processor core to return to the C0 state: the Monitor event. See the IA-32 Intel® Architecture Software Developer's Manual, Volume 2A/2B: Instruction Set Reference for more information.
2.1.1.4 Core C2 State
The core of the Celeron M processor can enter the C2 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the processor will not issue a Stop Grant Acknowledge special bus cycle unless the STPCLK# pin is also asserted. While in C2 state, the Celeron M processor will process only the bus snoops. The processor core will enter a snoopable sub-state (not shown in Figure 2) to process the snoop and then return to the C2 state.
2.1.1.5 Core C3 State
Core C3 state is a very low power state the processor core can enter while maintaining context. The core of the Celeron M processor can enter the C3 state by initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering the C3 state the processor core flushes the contents of its L1 caches into the processor’s L2 cache. Except for the caches, the processor core maintains all its architectural state in the C3 state. The Monitor remains armed if it is configured. All of the clocks in the processor core are stopped in the C3 state. Because the core’s caches are flushed the processor keeps the core in the C3 state when the processor detects a snoop on the FSB. The processor core will transition to the C0 state upon the occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor core to immediately initialize itself.
2.1.2 Package Low Power States
The package level low power states are applicable for the Celeron M processor. All package level low power states are described as follows:
2.1.2.1 Normal State
This is the normal operating state for the processor. The Celeron M processor enters the Normal state when the core is in the C0, C1/AutoHALT, or C1/MWAIT state.
2.1.2.2 Stop-Grant State
When the STPCLK# pin is asserted the core of the Celeron M processor enters the Stop- Grant state within 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. When the STPCLK# pin is deasserted the core returns to the previous core low-power state. Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to VCCP) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. When RESET# is asserted by the system the STPCLK#, SLP#, DPSLP#, and DPRSTP# pins must be deasserted more than 480 µs prior to RESET#
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deassertion (AC Specification T45). When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted ten or more bus clocks after the deassertion of SLP# (AC Specification T75). While in the Stop-Grant State, the processor will service snoops and latch interrupts delivered on the FSB. The processor will latch SMI#, INIT#, LINT[1:0] interrupts and will serviced only upon return to the Normal state. While in Stop-Grant state, the processor will process snoops on the FSB and it will latch interrupts delivered on the FSB. The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be asserted if there is any pending interrupt or monitor event latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that the processor should return to the Normal state. A transition to the Stop Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see Section 2.1.2.4) will occur with the assertion of the SLP# signal.
2.1.2.3 Stop Grant Snoop State
The processor will respond to snoop or interrupt transactions on the FSB while in Stop- Grant state by entering the Stop-Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. The processor will return to the Stop-Grant state once the snoop has been serviced or the interrupt has been latched.
2.1.2.4 Sleep State
The Sleep state is a low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior. Any transition on an input signal before the processor has returned to the Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence. While in the Sleep state, the processor is capable of entering an even lower power the processor is in the Sleep state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur.
2.1.2.5 Deep Sleep State
Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings on appropriate chipset based platforms with the CK410M clock chip are as follows:
- Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.
- Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK periods. To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re- started after DPSLP# deassertion as described above. A period of 15 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state. While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
2.2 FSB Low Power Enhancements
The Celeron M processor incorporates FSB low power enhancements:
- Dynamic FSB Power Down
- BPRI# control for address and control input buffers
- Dynamic Bus Parking
- Dynamic On Die Termination disabling
- L o w V CCP (I/O termination voltage) The Celeron M processor incorporates the DPWR# signal that controls the data bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. BPRI# control also allows the processor address and control input buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows a reciprocal power reduction in chipset address and control input buffers when the processor deasserts its BR0# pin. The On Die Termination on the processor FSB buffers is disabled when the signals are driven low, resulting in additional power savings. The low I/O termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low I/O switching power at all times.
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2.3 Processor Power Status Indicator (PSI#) Signal
The Celeron M processor incorporates the PSI# signal that is asserted when the processor is in a reduced power consumption state. PSI# can be used to improve intermediate and light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life. The algorithm that the Celeron M processor uses for determining when to assert PSI# is different from the algorithm used in previous Celeron M processors. For more information, contact your Intel Representative.
3 Electrical Specifications
3.1 FSB (Front Side Bus) and GTLREF
Most Celeron M processor FSB signals use Advanced Gunning Transceiver Logic (AGTL+) signalling technology. This signalling technology provides improved noise margins and reduced ringing through low-voltage swings and controlled edge rates. The termination voltage level for the Celeron M processor AGTL+ signals is VCCP = 1.05 V (nominal). Due to speed improvements to data and address bus, signal integrity and platform design methods have become more critical than with previous processor families. Contact your Intel representative for more information on design guidelines for the Celeron M processor FSB. The AGTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board. Termination resistors are provided on the processor silicon and are terminated to its I/O voltage (V CCP). Intel® 945GMS and 940GML Express Chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the system board for most AGTL+ signals. Refer to your Intel representative for board level termination resistor requirements. The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the FSB, including trace lengths, is highly recommended when designing a system.
3.2 Power and Ground Pins
For clean, on-chip power distribution, the Celeron M processor will have a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. Please contact your Intel representative for more details. The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins.
3.3 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Caution: Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 6. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and design guidelines, contact your Intel representative.
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3.3.1 V CC Decoupling
Regulator solutions need to provide bulk capacitance with a low effective series resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low-power states, must be provided by the voltage regulator solution. It is strongly recommended that the layout and decoupling recommendations be followed - for more details, contact your Intel representative.
3.3.2 FSB AGTL+ Decoupling
Celeron M processors integrate signal termination on the die as well as incorporate high frequency decoupling capacitance on the processor package. Decoupling must also be provided by the system motherboard for proper AGTL+ bus operation. For more information, contact your Intel representative.
3.3.3 FSB Clock (BCLK[1:0] ) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the Celeron M processor core frequency is a multiple of the BCLK[1:0] frequency. The Celeron M processor bus ratio multiplier will be set at its default ratio at manufacturing. The Celeron M processor uses a differential clocking implementation. For more information on Celeron M processor clocking, contact your Intel representative.
3.4 Voltage Identification and Power Sequencing
Information regarding the VID specification for the Celeron M processor is available from your Intel representative. The Celeron M processor uses seven voltage identification pins, VID[6:0], to support automatic selection of power supply voltages. The VID pins for Celeron M processor are CMOS outputs driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding to the state of VID[6:0]. For more details about VR design to support the Celeron M processor power supply requirements, please contact your Intel representative. Power source characteristics must be stable whenever the supply to the voltage regulator is stable. Refer to the Figure 3 for timing details of the power-up sequence. Figure 4 shows the power-down sequencing requirements.
Table 2. Voltage Identification Definition (Sheet 1 of 4)
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Table 2. Voltage Identification Definition (Sheet 2 of 4)
Table 2. Voltage Identification Definition (Sheet 3 of 4)
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3.5 Catastrophic Thermal Protection
prevent permanent silicon damage due to thermal runaway of the processor.
3.6 Signal Terminations and Unused Pins
the processor and the location of all RSVD pins. signal termination requirements. representative for further information on BIOS VID programming. Table 2. Voltage Identification Definition (Sheet 4 of 4)
3.7 FSB Frequency Select Signals (BSEL[2:0])
3.8 FSB Signal Groups
Table 3. BSEL[2:0] Encoding for BCLK Frequency
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- Refer to Chapter 4 for signal descriptions and termination requirements.
- In processor systems where there is no de bug port implemented on the system board,
implemented on the system board, these signals are no connects.
- BPM[2:1]# and PRDY# are AG TL+ output only signals.
- PROCHOT# signal type is open drain output and CMOS input.
Table 4. FSB Pin Groups
3.9 CMOS Signals
3.10 Maximum Ratings
operation limits, can functionality and long-term reliability be expected. exposure to conditions exceeding the functional operation condition limits.
- This rating applies to any processor pin.
- Contact Intel for storage requir ements in excess of one year.
3.11 Processor DC Specifications
signal pin assignments. Most of the signals on the FSB are in the AGTL+ signal group. CMOS group are listed in Table 10. Table 5. Processor DC Ab solute Maximum Ratings
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notes associated with each parameter.
- Each processor is programmed with a maximum valid vo ltage identification value (VID), which is set at
- The voltage specifications are a ssumed to be measured across VCCSENSE and VSSSENSE pins at socket with a
system is not coupled in the scope probe.
- Specified at the VID voltage.
CCDES(max) specification of 36 A comprehends only Celeron M processor on 65 nm process.
- Based on simulations and averaged over the durati on of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
- Measured at the bulk capacitors on the motherboard.
- V CC, BOOT tolerance is shown in Figure 3.
- This is a steady-state I CCP current specification, which is applicable when both VCCP and VCC_CORE are high.
- This is a power-up peak current spec ification, which is applicable when VCCP is high and VCC_CORE is low.
- Specified at the nominal V CC.
Table 6. Voltage and Current Specifications for the Celeron M Processor Standard
2.00 GHz and V
1.86 GHz and VCC
1.73 GHz and VCC
1.60 GHz and VCC
1.46 GHz and VCC
- Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
- The voltage specifications are as sumed to be measured across VCCSENSE and VSSSENSE pins at socket with a
system is not coupled in the scope probe.
- Specified at the VID voltage.
based on pre-silicon estimates.
- Based on simulations and averaged over the durati on of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
- Measured at the bulk capa citors on the motherboard.
- V CC, BOOT tolerance is shown in Figure 3.
- This is a steady-state I CCP current specification, which is applicable when both VCCP and VCC_CORE are high.
- This is a power-up peak current spec ification, which is applicable when VCCP is high and VCC_CORE is low.
Table 7. Voltage and Current Specifications for the Celeron M Processor Ultra Low
1.20 GHz at V
1.06 GHz at VCC
8.2 A3 , 4
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Figure 3. Active V CC and ICC Loadline for the Celeron M Processor Standard Voltage Figure 4. Active V CC and ICC Loadline for the Celeron M Processor Ultra Low Voltage Differential Remote Sense required. Differential Remote Sense required.
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- Crossing Voltage is defined as abso lute voltage where rising edge of BCLK0 is equal to the falling edge of
- Threshold Region is defined as a re gion entered about the crossing voltage in which the differential receiver
switches. It includes input threshold hysteresis.
- For Vin between 0 V and V IH.
- Cpad includes die capacitance only. No package parasitics are included.
- ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2.
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- V IL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
- V IH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
- V IH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the
signal quality specifications.
- This is the pull down driver re sistance. Refer to processor I/O Buffer Models for I/V characteristics.
- GTLREF should be generated from V CCP with a 1% tolerance resistor divider. Tolerance of resistor divider
decides the tolerance of GTLREF. The VCCP referred to in these specifications is the instantaneous VCCP.
- R TT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at
0.31*VCCP. RTT is connected to VCCP on die. Refer to processor I/O buffer models for I/V characteristics.
- Specified with on die R TT and RON are turned off.
- Cpad includes die capacitance only. No package parasitics are included.
Table 8. FSB Differential BCLK Specifications Table 9. AGTL+ Signal Group DC Specifications
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- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
CCP referred to in these specifications refers to instantaneous VCCP.
- Refer to the processor I/O Buffe r Models for I/V characteristics.
- For Vin between 0 V and V CCP. Measured when the driver is tristated.
- Cpad1 includes die capa citance only for DPSLP#,PWRGOOD. No package parasitics are included.
- Cpad2 includes die capaci tance for all other CMOS input signals. No package parasitics are included.
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- V OH is determined by value of the external pull-up resistor to VCCP. Please contact your Intel representative
- For Vin between 0 V and V OH.
- Cpad includes die capacitance only. No package parasitics are included.
Table 10. CMOS Signal Group DC Specifications Table 11. Open Drain Signal Group DC Specifications
Package Mechanical Specifications and Pin Information
4 Package Mechanical
The Celeron M processor is available in 478-pin Micro-FCPGA and 479-ball Micro-FCBGA packages. The package mechanical dimensions, keep-out zones, loading specifications, and mass specifications are shown in Figure 5 through Figure 8. Table 12 shows a top- view of package pinout with their functionalities. Caution: The Micro-FCBGA package incorporates land-side capacitors. Avoid contacting the capacitors with other electrically conductive materials on the motherboard. Doing so may short the capacitors, and possibly damage the device or render it inactive.
4.1 Processor Component Keep-Out Zones
The processor may contain components on the substrate that define component keep- out zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. The location and quantity of capacitors may change, but will remain within the component keep-in.
4.2 Package Loading Specifications
Maximum package loading specifications are static compressive loading in the direction normal to the processor. This maximum load limit should not be exceeded during shipping conditions, standard use condition, or by thermal solution. In addition, there are additional load limitations against transient bend, shock, and tensile loading, all of which can be obtained by contacting your field support. Moreover, the processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solution.
4.3 Processor Mass Specifications
The typical mass of the processor is given in Figure 5 and Figure 8. This mass includes all the components that are included in the package.
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Figure 5. Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)
Figure 6. Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)
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Figure 7. Micro-FCBGA Processor Package Drawing (Sheet 1 of 2)
Figure 8. Micro-FCBGA Processor Package Drawing (Sheet 2 of 2)
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4.4 Processor Pinout and Pin List
two different formats is shown in the following pages. Table 12. The Coordinates of the Processor Pi ns As Viewed from the Top of the Package
Table 12. The Coordinates of the Processor Pins As Viewed from the Top of the Package
Package Mechanical Specifications and Pin Information
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Table 13. Pin Listing by Pin Name
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Table 14. Pin Listing by Pin Number
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4.5 Alphabetical Signals Reference
Table 15. Signal Description (Sheet 1 of 8) straps which are sampled before RESET# is deasserted. Output Write bus transaction. ID match operations associated with the new transaction. outputs and latch their inputs. stall, the current bus owner cannot issue any new transactions. debug or performance monitoring tools.
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the FSB. It must connect the appropriate pins of both FSB agents. the bus by deasserting BPRI#. (133-MHz BCLK[1:0] frequency). indicate a valid data transfer. data signals correspond to a pair of one DSTBP# and one DSTBN#. group is inverted and therefore sampled active high. connect in the system. DBR# is not a processor signal. Table 15. Signal Descript ion (Sheet 2 of 8)
connect the appropriate pins on both FSB agents. within the covered group, would change level in the next cycle. DPRSTP# Not used DPRSTP# is not us ed by the Celeron M processor. driven by the ICH7-M chipset. clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents. Data strobe used to latch in D[63:0]#. Table 15. Signal Description (Sheet 3 of 8)
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Data strobe used to latch in D[63:0]#. when the processor detects an unmasked floating-point error. indicates that the processor should be returned to the Normal state. when STPCLK# is active will also cause an FERR# break event. and CPUID Instruction application note. GTLREF determines the signal reference level for AGTL+ input pins. receivers to determine if a signal is a logical 0 or logical 1. be continued by reasserting HIT# and HITM# together. Table 15. Signal Descript ion (Sheet 4 of 8)
when the NE bit in control register 0 (CR0) is set. Output Write bus transaction. connect the appropriate pins of both FSB agents. RESET#, then the processor executes its Built-in Self-Test (BIST). processor. Both signals are asynchronous. locked operation and ensure the atomicity of lock. Table 15. Signal Description (Sheet 5 of 8)
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PROCHOT# must be enabled via the BIOS. This signal may require voltage translation on the motherboard. the processor is in a lower state (Deep Sleep). transition monotonically to a high state. should be driven high throughout boundary scan operation. source synchronous to ADSTB[0]#. There is a 55-Ω (nominal) on die pull-up resistor on this signal. must connect the appropriate pins of both FSB agents. pins on the board be kept open for possible future use. Table 15. Signal Descript ion (Sheet 6 of 8)
will exit the Sleep state and transition to the Deep Sleep state. processor begins program execution from the SMM handler. signals to all processor core units except the FSB and APIC units. STPCLK# is an asynchronous input. (also known as the Test Access Port). requirements and implementation details. provides the serial input needed for JTAG specification support. requirements and implementation details. TDO (Test Data Out) transfers serial test data out of the processor. requirements and implementation details. TEST2 must have a 51-Ω ±5% pull-down resistor to VSS. THERMDA Other Thermal Diode Anode. THERMDC Other Thermal Diode Cathode. Table 15. Signal Description (Sheet 7 of 8)
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THERMTRIP# (Thermal Trip) pin. requirements and implementation details. must connect the appropriate pins of both FSB agents. requirements and implementation details. must be driven low during power on Reset. requirements and implementation details. CC Input Processor core power supply. VCCA provides isolated power for the internal processor core PLL’s. VCCP Input Processor I/O Power Supply. termination requirements and routing recommendations. be disabled until the voltage supply for the VID pins becomes valid. requirements and routing recommendations. Table 15. Signal Descript ion (Sheet 8 of 8)
Thermal Specifications and Design Considerations
5 Thermal Specifications and
The Celeron M processor requires a thermal solution to maintain temperatures within operating limits as set forth in Section 5.1. Any attempt to operate that processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions include active or passive heatsinks or heat exchangers attached to the processor exposed die. The solution should make firm contact to the die while maintaining processor mechanical specifications such as pressure. A typical system level thermal solution may consist of a processor fan ducted to a heat exchanger that is thermally coupled to the processor via a heat pipe or direct die attachment. A secondary fan or air from the processor fan may also be used to cool other platform components or to lower the internal ambient temperature within the system. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum junction temperature (Tj) specifications at the corresponding thermal design power (TDP) value listed in Table 16 and Table 17. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. Contact your Intel representative for more details on processor and system level cooling approaches. The maximum junction temperature is defined by an activation of the processor Intel® Thermal Monitor. Refer to Section 5.1.3 for more details. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the TDP indicated in Table 16 and Table 17. The Intel Thermal Monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more details on the usage of this feature, refer to Section 5.1.3. In all cases the Intel Thermal Monitor feature must be enabled for the processor to remain within specification.
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- The TDP specification should be used to design the processor thermal solution. The TDP is
not the maximum theoretical power the processor can generate.
- Not 100% tested. These power specifications are determined by characterization of the
- As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal
Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.
- The Intel Thermal Monitor automatic mode mu st be enabled for the processor to operate
Table 16. Power Specifications for the Celeron M Processor Standard Voltage
2.00 GHz & HFM V
1.86 GHz & HFM VCC
1.73 GHz & HFM VCC
1.60 GHz & HFM VCC
1.46 GHz & HFM VCC
- The TDP specification should be used to design the processor thermal solution. The TDP is
not the maximum theoretical power the processor can generate.
- Not 100% tested. These power specifications are determined by characterization of the
- As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal
Monitor’s automatic mode is used to indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.
- The Intel Thermal Monitor automatic mode must be enabled for the processor to operate
5.1 Thermal Specifications
maximum specified processor junction temperature has been reached.
5.1.1 Thermal Diode
diode usage recommendation when the PROCHOT# signal is not asserted. Table 17. Power Specifications for the Celeron M Processor Ultra Low Voltage
1.20 GHz & HFM VCC
1.06 GHz & HFM VCC
5.5 W 1, 4
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location on the die, and time based variations in the die temperature measurement. thermal sensor) is slower than the rate at which the TJ temperature can change. Core Duo and Intel Core Solo processors’ MSR. Table 20. The Diode Model parameters (Table 19) apply to traditional thermal sensors thermal sensor and cannot be used to predict the behavior of the Intel Thermal Monitor.
- Intel does not support or re commend operation of the thermal diode under reverse bias.
power supplies are not within their specified tolerance range.
- Characterized across a temperature range of 50 – 100°C.
- Not 100% tested. Specified by design characterization.
- The ideality factor, n, represents the deviat ion from ideal diode behavior as exemplified by
Boltzmann Constant, and T = absolute temperature (Kelvin). Table 18. Thermal Diode Interface Table 19. Thermal Diode Parameters using Diode Model
- The series resistance, R T, is provided to allow for a more accurate measurement of the
- Intel does not support or recommend operation of the thermal diode under reverse bias.
- Characterized across a temperature range of 50 - 100 °C.
- Not 100% tested. Specified by design characterization.
- The ideality factor, nQ, represents the devi ation from ideal transistor model behavior as
- The series resistance, R T, provided in the Diode Model Table (Table 19) can be used for
more accurate readings as needed. Table 20. Thermal Diode Parameters using Transistor Mode
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5.1.2 Thermal Diode Offset
particular processor will be calculated. ntrim as defined in the temperature sensor manufacturers' datasheet. The ntrim used to calculate the Diode Correction Toffset are listed in Table 21. definition and recommended offset implementation.
5.1.3 Intel® Thermal Monitor
the TCC is active continuously. Automatic mode takes precedence. processor to be operating within specifications. the maximum allowed value for operation. Table 21. Thermal Diode n
Thermal Specifications and Design Considerations When Intel Thermal Monitor 1 is enabled while a high temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. Once the temperature has returned to a non- critical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance will be decreased by the same amount as the duty cycle when the TCC is active. The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC will be activated immediately, independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be On-demand mode may be used at the same time automatic mode is enabled, however, if the system tries to enable the TCC via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode will take precedence. An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active. Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three MSRs, and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Note: PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep and Deep Sleep low power states (internal clocks stopped), hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification. If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above low power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point. Contact your Intel representative for more details on the Intel Thermal Monitor register and programming details. If Intel Thermal Monitor automatic mode is disabled, the processor will be operating out of specification. Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125°C. At this point the THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified in Chapter 3.5.
Thermal Specifications and Design Considerations
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5.1.4 Digital Thermal Sensor
The Celeron M processor also contains an on die digital thermal sensor that can be read via a MSR (no I/O interface). The digital thermal sensor is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation via the Intel Thermal Monitor. The digital thermal sensor is only valid while the processor is in the normal operating state (C0 state). Unlike traditional thermal devices, the Digital Thermal sensor will output a temperature relative to the maximum supported operating temperature of the processor (T J,max). It is the responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the digital thermal sensor will always be at or below TJ,max. Over temperature conditions are detectable via an Out Of Spec status bit. This bit is also part of the Digital Thermal sensor MSR. When this bit is set, the processor is operating out of specification and immediate shutdown of the system should occur. The processor operation and code execution is not guaranteed once the activation of the Out of Spec status bit is set. The Digital Thermal Sensor (DTS) relative temperature readout corresponds to the Intel Thermal Monitor (TM1) trigger point. When the DTS indicates maximum processor core temperature has been reached TM1 hardware thermal control mechanism will activate. The DTS and Intel Thermal Monitor (TM1) temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and thermal gradient between the individual core DTS. Additionally, the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power, mechanical and thermal attach and software application. The system designer is required to use the DTS to guarantee proper operation of the processor within its temperature operating specifications. Changes to the temperature can be detected via two programmable thresholds located in the processor MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. Refer to the IA-32 Intel® Architecture Software Developer's Manual and your Intel representative for specific register and programming details.
5.1.5 Out of Specification Detection
Overheat detection is performed by monitoring the processor temperature and temperature gradient. This feature is intended for graceful shut down before the THERMTRIP# is activated. If the processor’s TM1 is triggered and the temperature remains high, an “Out Of Spec” status and sticky bit are latched in the status MSR register and generates thermal interrupt. For more details on the interrupt mechanism, contact your Intel representative.
5.1.6 PROCHOT# Signal Pin
An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If the Intel Thermal Monitor 1 is enabled (note that the Intel Thermal Monitor 1 must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Refer to the IA-32 Intel® Architecture Software Developer's Manuals and your Intel representative for specific register and programming details. The Celeron M processor implements a bi-directional PROCHOT# capability to allow system designs to protect various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor has
Thermal Specifications and Design Considerations reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components. When PROCHOT# is driven by an external agent, TM1 is enabled and the processor core will have their core clocks modulated. One application is the thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR can cool down as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP. With a properly designed and characterized thermal solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. An under- designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. Contact your Intel representative for details on implementing the bi-directional PROCHOT# feature.