390 INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.1 Terminology
- 1.2 References
- 2 Low Power Features
- 2.1 Clock Control and Low Power States
- 2.1.1 Normal State
- 2.1.2 AutoHALT Power-Down State
- 2.1.3 Stop-Grant State
- 2.1.4 HALT/Grant Snoop State
- 2.1.5 Sleep State
- 2.1.6 Deep Sleep State
- 2.2 FSB Low Power Enhancements
- 2.3 Processor Power Status Indicator (PSI#) Signal
- 3 Electrical Specifications
- 3.1 Power and Ground Pins
- 3.1.1 FSB Clock (BCLK[1:0]) and Processor Clocking
- 3.2 Voltage Identification and Power Sequencing
- 3.3 Catastrophic Thermal Protection
- 3.4 Signal Terminations and Unused Pins
- 3.5 FSB Frequency Select Signals (BSEL[1:0])
- 3.6 FSB Signal Groups
- 3.7 CMOS Signals
- 3.8 Maximum Ratings
- 3.9 Processor DC Specifications
- 4 Package Mechanical Specific ations and Pin Information
- 4.1 Processor Pinout and Pin List
- 4.2 Alphabetical Signals Reference
- 5 Thermal Specifications and Design Considerations
- 5.1 Thermal Specifications
- 5.1.1 Thermal Diode
- 5.1.2 Thermal Diode Offset
- 5.1.3 Intel® Thermal Monitor
Document Number: 303110-008 Intel® Celeron® M Processor on 90 nm Process Datasheet January 2007
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IINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Celeron® M processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Δ Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See www.intel.com/products/processor_number for details. Intel, Celeron, MMX, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright© 2004–2007, Intel Corporation. All rights reserved.
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2 Illustration of Deep Sleep State VCC Static and Ripple Tolerances
3 Illustration of Active State VCC Static and Ripple Tolerances
4 Illustration of Deep Sleep State VCC Static and Ripple Tolerances
5 Active VCC and ICC Loadline for the Celeron M Processor:
6 Deep Sleep VCC and ICC Loadline for Celeron M Processors:
Revision History
-001 Initial release July 2004 -002 Updates include:
- Document Title from “Intel® Celeron® M Processor Ultra Low Voltage on 90 nm Process” to “Intel® Celeron® M Processor on 90 nm Process”
- Added Micro-FCPGA package information throughout Chapter 4
- Celeron® M Processor 360 and 350 DC and Thermal and Power Specifications (Updated Table 4 and Table 17) August 2004 -003 Updates include:
- Added resources to the Reference Table 1
- BSEL[1:] literature updated
- Celeron M processor 370 and 373 DC and Thermal and Power Specifications (Updated Table 4 and Table 17)
- Execute Disable bit and Le ad Free feature referenced January 2005 -004 • Celeron M processor 383 DC and Thermal and Power Specifications (Updated Table Table 4 and Table 17) April 2005 -005 • Added Celeron M processor 380 specifications July 2005 -006
- Updated Celeron M processor 370, 360J, 350J and Celeron M processor ULV 383, 373 specifications for optimized VID (T Table 4 and Table 17)
- Updated Celeron M processor ULV 383, 373 TDP specification (Table 17) July 2005 -007 • Added Celeron M processor 390 specifications January 2006 -008 • Updated Celeron M 390 Ther mal Specifications January 2007
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1 Introduction
The Intel® Celeron® M processor based on 90 nm process technology is a high- performance, low-power mobile processor with several enhancements over previous mobile Celeron processors. Throughout this document, the term Celeron M processor signifies Intel Celeron M processor based on 90 nm technology. This document contains specification for the Celeron M processor 390, 380, 370, 360J, 360, 350J, 350Δ and the Celeron M processor Ultra Low Voltage 383, 373, 353Δ. Note: ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See www.intel.com/products/processor_number for details. The following list provides some of the key features on this processor:
- Manufactured on Intel’s advanced 90 nanometer process technology with copper interconnect.
- Supports Intel Architecture with Dynamic Execution
- On-die, primary 32-KB instruction cache and 32-KB write-back data cache
- On-die 1-MB (512-KB for Celeron M processor Ultra Low Voltage 373 and 353) second level cache with Advanced Transfer Cache Architecture, 8-way set associativity and ECC (Error Correcting Code) Support.
- Data Prefetch Logic
- Streaming SIMD extensions 2 (SSE2)
- 400-MHz, source-synchronous front side bus (FSB)
- Micro-FCPGA and Micro-FCBGA (ULV parts available only in Micro-FCBGA) packaging technologies (including lead free technology for the Micro-FCBGA package for Celeron M processors 390, 380, 370, 383, 373, and 353).
- Execute Disable Bit support for enhanced security (available on processors with CPU Signature=06D8h and recommended for implementation on Intel® 915/910 Express Chipset-based platforms only) The Celeron M processor maintains support for MMX™ technology and Internet Streaming SIMD instructions and full compatibility with IA-32 software. The on-die, 32-KB Level 1 instruction and data caches and the 1-MB (512-KB for Celeron M processor Ultra Low Voltage 373 and 353) Level 2 cache with advanced transfer cache architecture enable significant performance improvement over existing mobile processors. The processor’s data prefetch logic speculatively fetches data to the L2 cache before an L1 cache requests occurs, resulting in reduced bus cycle penalties and improved performance. The streaming SIMD extensions 2 (SSE2) enable break-through levels of performance in multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition. The new packed double-precision floating-point instructions enhance performance for applications that require greater range and precision, including scientific and engineering applications and advanced 3-D geometry techniques, such as ray tracing. The Celeron M processor’s 400-MHz FSB utilizes a split-transaction, deferred reply protocol. The 400-MHz FSB uses source-synchronous transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data
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transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3.2 GB/second. The FSB uses Advanced Gunning Transceiver Logic (AGTL+) signalling technology, a variant of (GTL+) signaling technology with low power enhancements. The Celeron M processor utilizes socketable Micro Flip-Chip Pin Grid Array (Micro- FCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount, zero insertion force (ZIF) socket, which is referred to as the mPGA479M socket.
1.1 Terminology
1.2 References
Material and concepts available in the following documents may be beneficial when reading this document. Term Definition A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level). XXXX means that the specification or value is yet to be determined. Front Side Bus (FSB) Refers to the interface between the processor and system core logic (also known as the chipset components). Document Document Location 1 Intel® Celeron® M Processor Specification Update http://www.intel.com/ design/mobile/specupdt/ 300303.htm Mobile Intel® 915PM/GM/GMS and 910GML Express Chipset Datasheet http://www.intel.com/ design/mobile/datashts/ 305264.htm Mobile Intel® 915PM/GM/GMS and 910GML Express Chipset Specification Update http://www.intel.com/ design/mobile/specupdt/ 307167.htm Intel® I/O Controller Hub 6 (ICH6) Family Datasheet http://www.intel.com/ design/chipsets/datashts/ 301473.htm Intel® I/O Controller Hub 6 (ICH6) Family Specification Update http://www.intel.com/ design/chipsets/specupdt/ 301474.htm Intel® 855PM Chipset Memory Controller Hub (MCH) Datasheet http://www.intel.com/ design/chipsets/datashts/ 252613.htm
Intel® 855PM Chipset MCH DDR 333/200/266 MHz Specification Update http://www.intel.com/ design/chipsets/specupdt/ 253488.htm Intel® 855GM/GME Chipset Graphics and Memory Controller Hub (GMCH) Datasheet http://www.intel.com/ design/chipsets/datashts/ 252615.htm Intel® 855GM/GME Chipset Graphics and Memory Controller Hub (GMCH) Specification Update http://www.intel.com/ design/chipsets/specupdt/ 253572.htm Intel® 82801DBM I/O Controller Hub 4 Mobile (ICH4-M) Datasheet http://www.intel.com/ design/mobile/datashts/ 252337.htm Intel® 82801DBM I/O Controller Hub 4 Mobile (ICH4-M) Datasheet Specification Update http://www.intel.com/ design/chipsets/specupdt/ 252663.htm IA-32 Intel® Architecture Software Developer's Manuals http://www.intel.com/ design/pentium4/manuals/ index_new.htm Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A- M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide Document Document Location
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2 Low Power Features
2.1 Clock Control and Low Power States
the processor low-power states.
2.1.1 Normal State
This is the normal operating state for the processor.
2.1.2 AutoHALT Power-Down State
the processor to immediately initialize itself. will process bus snoops and interrupts.
2.1.3 Stop-Grant State
Figure 1. Clock Control States
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Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to VCCP) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted ten or more bus clocks after the deassertion of SLP#. A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 2.1.4). A transition to the Sleep state (see Section 2.1.5) will occur with the assertion of the SLP# signal. While in the Stop-Grant state, SMI#, INIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process snoops on the FSB, and it will latch interrupts delivered on the FSB. The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be asserted if there is any pending interrupt latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that it should return the processor to the Normal state.
2.1.4 HALT/Grant Snoop State
The processor will respond to snoop or interrupt transactions on the FSB while in Stop- Grant state or in AutoHALT Power-Down state. During a snoop or interrupt transaction, the processor enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. After the snoop is serviced or the interrupt is latched, the processor will return to the Stop-Grant state or AutoHALT Power-Down state, as appropriate.
2.1.5 Sleep State
A low power state in which the processor maintains its context, maintains the phase- locked loop (PLL), and has stopped all internal clocks. The Sleep state can be entered only from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is in the Stop Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation. Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will cause unpredictable behavior. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant State. If RESET# is driven active while the processor
is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the reset sequence. While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state by asserting the DPSLP# pin. (See Section 2.1.6.) While the processor is in the Sleep state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur.
2.1.6 Deep Sleep State
Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings on 855PM chipset family based platforms with compatible clock generator chips are as follows:
- Deep Sleep entry - DPSLP# and CPU_STP# are asserted simultaneously. The clock chip will stop/tristate BCLK within two BCLKs +/- a few nanoseconds.
- Deep Sleep exit - DPSLP# and CPU_STP# are deasserted simultaneously. The clock chip will drive BCLK to differential DC levels within 2-3 ns and starts toggling BCLK 2-6 BCLK periods later. To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted after DPSLP# deassertion as described above. A period of 30 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep State. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop- Grant state. While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions.
2.2 FSB Low Power Enhancements
The Celeron M processor incorporates the FSB low power enhancements:
- Dynamic FSB Power Down
- BPRI# control for address and control input buffers
- Dynamic On Die Termination disabling
- Low VCCP (I/O termination voltage) The Celeron M processor incorporates the DPWR# signal that controls the data bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. BPRI# control also allows the processor address and control input buffers to be turned off when the BPRI# signal is inactive. The on-die termination on the processor FSB buffers is disabled when the signals are driven low, resulting in additional power savings. The low I/O termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low I/O switching power at all times.
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2.3 Processor Power Status Indicator (PSI#) Signal
The Celeron M processor incorporates the PSI# signal that is asserted when the processor is in a low power (Deep Sleep) state. This signal is asserted upon Deep Sleep entry and deasserted upon exit. PSI# can be used to improve the light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life.
3 Electrical Specifications
3.1 Power and Ground Pins
For clean, on-chip power distribution, the Celeron M processor has a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. Please refer to the platform design guides for more details. The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins.
3.1.1 FSB Clock (BCLK[1:0] ) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the Celeron M processor core frequency is a multiple of the BCLK[1:0] frequency. The Celeron M processor uses a differential clocking implementation.
3.2 Voltage Identification and Power Sequencing
The Celeron M processor uses six voltage identification pins, VID[5:0], to support automatic selection of power supply voltages. The VID pins for Celeron M processor are CMOS outputs driven by the processor VID circuitry. Table 1 specifies the voltage level corresponding to the state of VID[5:0].
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Table 1. Voltage Identification Definition
3.3 Catastrophic Thermal Protection
The Celeron M processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. If the external thermal sensor detects a catastrophic processor temperature of 125°C (maximum), or if the THERMTRIP# signal is asserted, the V CC supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor.
3.4 Signal Terminations and Unused Pins
All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future Celeron M processors. See Section 4.2 for a pin listing of the processor and the location of all RSVD pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected. The TEST1 and TEST2 pins must have a stuffing option connection to VSS separately via 1-kΩ, pull-down resistors.
3.5 FSB Frequency Select Signals (BSEL[1:0])
The BSEL[1:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). These signals should be connected to the clock chip and Intel 915PM/GM/ GMS and 910GML Express Chipset on the platform. These signals must be left unconnected on platforms designed with the Celeron M processor and the Intel 852/ 855 chipset families.
3.6 FSB Signal Groups
In order to simplify the following discussion, the FSB signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependant upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 2 identifies which signals are common clock, source synchronous, and asynchronous.
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- BPM[2:0}# and PRDY# are AG TL+ output only signals.
- In processor systems where there is no debug port implemented on the system board, these signals are
board, these signals are no connects. Table 2. FSB Pin Groups
3.7 CMOS Signals
3.8 Maximum Ratings
always take precautions to avoid high static voltages or electric fields.
- This rating applies to any processor pin.
- Contact Intel for storage requir ements in excess of one year.
3.9 Processor DC Specifications
signal pin assignments. Most of the signals on the FSB are in the AGTL+ signal group. CMOS group are listed in Table 10. notes associated with each parameter. Table 3. Processor DC Ab solute Maximum Ratings
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Table 4. Voltage and Current Sp ecifications (Sheet 1 of 2)
1.260 V 1,2,9
373 Core VCC
0.940 V 1,2,9
1.575 V2 , 1 0
21.0 A 3,9,11
7.0 A 3,9,11,
16.4 A 4,9,11
3.4 A 4,9,11,
16.1 A 4,9,11
3.3 A 4,9,11,
15.5 A 4,9,11
- The typical values shown are the VID encoded voltag es. Static and ripple tolerances (for minimum and
maximum voltages) are defined in the loadline tables i.e., Table 5 through Table 7.
- The voltage specifications are assumed to be measured at a via on the motherboard’s opposite side of the
less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.
- Specified at V CC,STATIC (nominal) under maximum signal loading conditions.
- Specified at the VID voltage.
designed to this specification.
- Based on simulations and averaged over the durati on of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
- Measured at the bulk capa citors on the motherboard.
- Adherence to loadline specificatio n for the Celeron M processor is required to ensure reliable processor
- Intel processor numbers are not a measure of perf ormance. Processor numbers differentiate features
processor_number for details.
- The Celeron M processor will support V CCA supply voltage of either 1.8 V ±5% or 1.5 V ±5%. Either one of
these voltages can be used on the platform.
- These are VID values. Individual processor VID values may be calibrated during manufacturing such that
required to ensure reliable processor operation.
- For 350J and 360J, CPU signature = 06D8h.
3.0 A 4,9,11,
Table 4. Voltage and Current Sp ecifications (Sheet 2 of 2)
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Table 5. Voltage Tolerances for the Ce leron M Processor (Deep Sleep State) Figure 2. Illustration of Deep Sleep State V CC Static and Ripple Tolerances
Table 6. Voltage Tolerances for the Celeron M Processor ULV (Active State)
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Figure 3. Illustration of Active State V CC Static and Ripple Tolerances Table 7. Voltage Tolerances for the Celeron M Processor ULV (Deep Sleep State)
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- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- Crossing Voltage is defined as abso lute voltage where rising edge of BCLK0 is equal to the falling edge of
- Threshold Region is define d as a region entered about the crossing voltage in which the differential receiver
switches. It includes input threshold hysteresis.
- For Vin between 0 V and V
- Cpad includes die capacitance only. No package parasitics are included.
- ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2.
Figure 6. Deep Sleep V CC and ICC Loadline for Celeron M Processors: Table 8. FSB Differential BCLK Specifications
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- V IL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
- V IH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
- V IH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the
signal quality specifications in Chapter 3.
- This is the pull-down driver resi stance. Refer to processor I/O buffer models for I/V characteristics.
- GTLREF should be generated from V CCP with a 1% tolerance resistor divider. The VCCP referred to in these
specifications is the instantaneous VCCP.
- R TT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at
0.31*VCCP. RTT is connected to VCCP on die. Refer to processor I/O buffer models for I/V characteristics.
- Specified with on die R TT and RON are turned off.
- Cpad includes die capacitance only. No package parasitics are included.
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- The V CCP referred to in these specifications refers to instantaneous VCCP.
- For Vin between 0 V and V CCP. Measured when the driver is tristated.
- Cpad includes die capacitance only. No package parasitics are included.
Table 9. AGTL+ Signal Group DC Specifications Table 10. CMOS Signal Group DC Specifications
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- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
OH is determined by value of the external pull-up resistor to VCCP.
- For Vin between 0 V and V OH.
- Cpad includes die capacitance only. No package parasitics are included.
Table 11. Open Drain Signal Group DC Specifications
4 Package Mechanical
The Micro-FCBGA package may have capacitors placed in the area surrounding the die. capacitors and any thermal solution should be considered to prevent capacitor shorting. Figure 7. Micro-FCPGA Package To p and Bottom Isometric Views
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only. Refer to Table 12 for details. Figure 8. Micro-FCPGA Package - Top and Side Views
1.25 MAX
Figure 9. Micro-FCPGA Package - Bottom View
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- Overall height with socket is based on desi gn dimensions of the Micro-FCPGA package with
no thermal solution attached. Values are based on design specifications and tolerances. Table 12. Micro-FCPGA Package Dimensions
Figure 10. Micro-FCBGA Package Top and Bottom Isometric Views
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only. Refer to Table 13 for details. Figure 11. Micro-FCBGA Package Top and Side Views
- Overall height as delivered. Values are based on design specifications and tolerances. This
Table 13. Micro-FCPGA Package Dimensions
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Figure 12. Micro-FCBGA Package Bottom View
Package Mechanical Specifications and Pin Information
4.1 Processor Pinout and Pin List
Figure 13 shows the top view pinout of the Celeron M processor. The pin list arranged in two different formats is shown in the following pages.
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Figure 13. The Coordinates of the Processor Pins As Viewed from the Top of the Package
Table 14. Pin Listing by Pin Name
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Table 15. Pin Listing by Pin Number
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4.2 Alphabetical Signals Reference
Table 16. Signal Description (Sheet 1 of 8) straps which are sampled before RESET# is deasserted. Output Write bus transaction. ID match operations associated with the new transaction. The differential pair BCLK (Bus Clock) determines the FSB frequency. stall, the current bus owner cannot issue any new transactions. performance monitoring tools.
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FSB. It must connect the appropriate pins of both FSB agents. the bus by deasserting BPRI#. indicate a valid data transfer. group is inverted and therefore sampled active high. connect in the system. DBR# is not a processor signal. Table 16. Signal Descript ion (Sheet 2 of 8)
connect the appropriate pins on both FSB agents. the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of both FSB agents. within the covered group, would change level in the next cycle. power on the Celeron M data bus input buffers. clock data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both FSB agents. Data strobe used to latch in D[63:0]#. Table 16. Signal Description (Sheet 3 of 8)
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Data strobe used to latch in D[63:0]#. indicates that the processor should be returned to the Normal state. when STPCLK# is active will also cause an FERR# break event. CPUID Instruction application note. GTLREF determines the signal reference level for AGTL+ input pins. receivers to determine if a signal is a logical 0 or logical 1. be continued by reasserting HIT# and HITM# together. when the NE bit in control register 0 (CR0) is set. Output Write bus transaction. Table 16. Signal Descript ion (Sheet 4 of 8)
appropriate pins of both FSB agents. RESET#, then the processor executes its Built-in Self-Test (BIST). systems where no debug port is implemented on the system board. compatible with the signals of those names on the Celeron processor. Both signals are asynchronous. locked operation and ensure the atomicity of lock. the processor Thermal Control Circuit has been activated, if enabled. See Chapter 5 for more details. Section 2.1.4 for more details. Table 16. Signal Description (Sheet 5 of 8)
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monotonically to a high state. be driven high throughout boundary scan operation. valid within the specified setup time before RESET# is deasserted. must connect the appropriate pins of both FSB agents. pins on the board be kept open for possible future use. will exit the Sleep state and transition to the Deep Sleep state. processor begins program execution from the SMM handler. Table 16. Signal Descript ion (Sheet 6 of 8)
STPCLK# is an asynchronous input. (also known as the Test Access Port). provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. THERMDA Other Thermal Diode Anode. THERMDC Other Thermal Diode Cathode. THERMTRIP# (Thermal Trip) pin. must connect the appropriate pins of both FSB agents. must be driven low during power on Reset. CC Input Processor core power supply. VCCA[3:0] Input V CCA provides isolated power for the internal processor core PLL’s. VCCP Input Processor I/O power supply. enable addition of decoupling on the VCCQ lines if necessary. Table 16. Signal Description (Sheet 7 of 8)
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be disabled until the voltage supply for the VID pins becomes valid. Table 16. Signal Descript ion (Sheet 8 of 8)
Thermal Specifications and Design Considerations
5 Thermal Specifications and
The Celeron M processor requires a thermal solution to maintain temperatures within operating limits as set forth in Table 17. Any attempt to operate that processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions include active or passive heatsinks or heat exchangers attached to the processor exposed die. The solution should make firm contact to the die while maintaining processor mechanical specifications such as pressure. A typical system level thermal solution may consist of a processor fan ducted to a heat exchanger that is thermally coupled to the processor via a heat pipe or direct die attachment. A secondary fan, or air from the processor fan, may also be used to cool other platform components or lower the internal ambient temperature within the system. To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor must remain within the minimum and maximum junction temperature (Tj) specifications at the corresponding thermal design power (TDP) value listed in Table 17. Thermal solutions not design to provide this level of thermal capability may affect the long-term reliability of the processor and system. The maximum junction temperature is defined by an activation of the processor Intel® Thermal Monitor. Refer to Section 5.1.3 for more details. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the TDP indicated in Table 17. The Intel Thermal Monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more details on the usage of this feature, refer to Section 5.1.3. In all cases, the Intel Thermal Monitor feature must be enabled for the processor to remain within specification.
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Table 17. Power Specifications for th e Celeron M Processor (Sheet 1 of 2)
- The Thermal Design Power (TDP) specification should be used to design the processor thermal solution.
The TDP is not the maximum theoretical power the processor can dissipate.
- Not 100% tested. These power specifications are dete rmined by characterization of the processor currents
at higher temperatures and extrapolating the values for the temperature indicated.
- As measured by the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to
indicate that the maximum TJ has been reached. Refer to Section 5.1 for more details.
- The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within
- Intel processor numbers are not a measure of perf ormance. Processor numbers differentiate features
processor_number for details.
- See Table 4 for VCC2 and VCC3.
5.1 Thermal Specifications
5.1.1 Thermal Diode
provide the diode interface and specifications. location on the die, and time based variations in the die temperature measurement. thermal sensor) is slower than the rate at which the TJ temperature can change. Table 17. Power Specifications for th e Celeron M Processor (Sheet 2 of 2)
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5.1.2 Thermal Diode Offset
sensors, will have to be made before the above offset is applied.
- Intel does not support or re commend operation of the thermal diode under reverse bias.
power supplies are not within their specified tolerance range.
- Not 100% tested. Specified by design/characterization.
- The ideality factor, n, represents the deviat ion from ideal diode behavior as exemplified by
Boltzmann Constant, and T = absolute temperature (Kelvin). reference value used to calculate the Celeron M thermal diode temperature offset.
- The series resistance, R T, is provided to allow for a more accurate measurement of the
- Offset value is programmed in processor Model Specific Register.
Table 18. Thermal Diode Interface Table 19. Thermal Diode Specification
1.0022 Notes 2,
Thermal Specifications and Design Considerations
5.1.3 Intel® Thermal Monitor
The Intel Thermal Monitor helps control the processor temperature by activating the TCC when the processor silicon reaches its maximum operating temperature. The temperature at which Intel Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would not be detectable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously. The Intel Thermal Monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks when the processor silicon reaches its maximum operating temperature. The Intel Thermal Monitor uses two modes to activate the TCC: Automatic mode and On-Demand mode. If both modes are activated, Automatic mode takes precedence. The Intel Thermal Monitor Automatic mode must be enabled via BIOS for the processor to be operating within specifications. The automatic mode called Intel Thermal Monitor 1 This mode is selected by writing values to the model specific registers (MSRs) of the processor. After Automatic mode is enabled, the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation. When Intel Thermal Monitor 1 is enabled, and a high temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. Once the temperature has returned to a non- critical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance will be decreased by the same amount as the duty cycle when the TCC is active, however, with a properly designed and characterized thermal solution the TCC most likely will never be activated, or only will be activated briefly during the most power intensive applications. The TCC may also be activated via On-Demand mode. If bit 4 of the ACPI Intel Thermal Monitor Control Register is written to a 1, the TCC will be activated immediately, independent of the processor temperature. When using On-Demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor Control Register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in On-Demand mode, the duty cycle can be On-Demand mode may be used at the same time Automatic mode is enabled, however, if the system tries to enable the TCC via On-Demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode will take precedence. An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active. Note: PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep, Deep Sleep, and Deeper Sleep low power states (internal clocks stopped), hence the thermal diode reading must be used as a safeguard to maintain the processor junction
Thermal Specifications and Design Considerations
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temperature within the 100°C (maximum) specification. If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above low power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the Low Power state and the processor junction temperature drops below the thermal trip point. If automatic mode is disabled, the processor will be operating out of specification. Regardless of enabling the automatic or On-Demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125°C. At this point the FSB signal THERMTRIP# will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within a time specified in Chapter 3.