IXFR30N50 IXYS | Alldatasheet

Document overview

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Technical content

Features

  • Silicon chip on Direct-Copper-Bond substrate - High power dissipation - Isolated mounting surface - 2500V electrical isolation  Low drain to tab capacitance(<50pF)  Low R DS (on) HDMOS TM process  Rugged polysilicon gate cell structure  Unclamped Inductive Switching (UIS) rated  Fast intrinsic Rectifier

Applications

 Battery chargers  Switched-mode and resonant-mode power supplies  DC choppers  AC motor control Advantages  Easy assembly  Space savings  High power density G = Gate D = Drain S = Source * Patent pending Isolated back surface* VDSS ID25 R DS(on) IXFR 30N50Q 500 V 29 A 0.16 /G87 IXFR 32N50Q 500 V 30 A 0.15 /G87 trr /G163/G32250 ns HiPerFETTM Power MOSFETs ISOPLUS247 TM (Electrically Isolated Back Surface) N-Channel Enhancement Mode High dV/dt, Low trr, HDMOS TM Family E 153432 IXYS reserves the right to change limits, test conditions, and dimensions. Preliminary data

2 - 4© 2000 IXYS All rights reserved Symbol Test Conditions Characteristic Values (TJ = 25/G176C, unless otherwise specified) min. typ. max. gfs VDS = 10 V; ID = IT Note 2 18 28 S C iss 3950 pF C oss VGS = 0 V, VDS = 25 V, f = 1 MHz 640 pF C rss 210 pF td(on) 35 ns tr VGS = 10 V, VDS = 0.5  VDSS , ID = IT 42 ns td(off) R G = 1/G32/G87 (External), 75 ns tf 20 ns Q g(on) 150 nC Q gs VGS = 10 V, VDS = 0.5  VDSS , ID = IT 26 nC Q gd 85 nC R thJC 0.40 K/W R thCK 0.15 K/W Source-Drain Diode Characteristic Values (TJ = 25/G176C, unless otherwise specified) Symbol Test Conditions min. typ. max. IS VGS = 0 V 32 A ISM Repetitive; pulse width limited by TJM 128 A VSD IF = IS, VGS = 0 V, Note 1 1.5 V trr 250 ns Q RM 0.75 /G109C IRM 7.5 A IF = Is, -di/dt = 100 A/ms, V R = 100 V Note: 1. IT test condition: IXFR30N50: IT = 15A IXFR32N50: IT = 16A IXFR 30N50Q IXFR 32N50Q Note: 2. Pulse test, t /G163/G32300 /G109s, duty cycle d/G32/G163 2 % ISOPLUS 247 (IXFR) OUTLINE Dim. Millimeter Inches Min. Max. Min. Max. A 4.83 5.21 .190 .205 A1 2.29 2.54 .090 .100 A2 1.91 2.16 .075 .085 b 1.14 1.40 .045 .055 b1 1.91 2.13 .075 .084 b2 2.92 3.12 .115 .123 C 0.61 0.80 .024 .031 D 20.80 21.34 .819 .840 E 15.75 16.13 .620 .635 e 5.45 BSC .215 BSC L 19.81 20.32 .780 .800 L1 3.81 4.32 .150 .170 Q 5.59 6.20 .220 .244 R 4.32 4.83 .170 .190 S 13.21 13.72 .520 .540 T 15.75 16.26 .620 .640 U 1.65 3.03 .065 .080

1 Gate, 2 Drain (Collector)

3 Source (Emitter)

IXYS MOSFETS and IGBTs are covered by one or more of the following U.S. patents: 4,835,592 4,881,106 5,017,508 5,049,961 5,187,117 5,486,715 4,850,072 4,931,844 5,034,796 5,063,307 5,237,481 5,381,025