3242 INTEL | Alldatasheet
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. t I COUNTER FOR 16K DYNAMIC RAMs = Ideal For 2116 = Single Power Supply: ses, . +! +10 «= Simplifies System Design 5 Volts +10% = Address Input to Output Delay: = Reduces Package Count [np tp y 9ns Driving 15 pF, = Standard 28-Pin DIP 25ns Driving 250pF «= Suitable For Either Distributed Or Burst Refresh ‘The Intel® 3242 is an address multiplexer and refresh counter for multiplexed address dynamic RAMs requiring refresh of 640r 128 cycles, It multiplexes 14 bits of system supplied address to 7 output address pins. The device aiso contains a7 bit refresh counter which is externally controlied so. that either distributed or burst refresh may be used. The high performance of the 3242 makes it especially suitable for use with high speed N-channel RAMs like the 2116. The 3242 operates from a single +5 volt power supply and is specified for operation over a0 to +75°C ambient temperature range. It is fabricated by means of Intel's highly reliable Schottky bipolar process and is packaged in a hermetically sealed 28 pin Type D package. PIN CONFIGURATION LOGIC DIAGRAM court C> Estes fa ecrnesu ensoie 2 apa SSS > row enapie C]s PAs n6 | a neo Os apa ; ee | 7 1 ne : | ' \\ “= “ps ' | \\rotat rorat | ae way \\ | | | 1 a» spa | : \\ a ssfo, ay | ee 1 oe ‘Po, | i | \\ i ono] =P zero ever i} iT { NOTE: Ay THROUGH Ag ARE ROW ADDRESSES | \\ | TRUTH TABLE AND DEFINITIONS: mean ren [RermesnT Row son sroraL [ow [x | ftowinrenwac counters | ee {UR _ ADVANCES INTERNAL REERESH COUNTER SRS aiBY Reacaresveno ov ye ina o OLA ant nernesn COUNTER Semicon wast AePmest MODE? 2-26
A.C. Characteristics All Limits Apply for Vcc = +5.0V +10%, Ta = 0°C to 75°C, Load = 1 TTL, C1 = 250pF, Unless Otherwise Specified. SYMBOL PARAMETER [ min. [Tye] max. | unit | CONDITIONS tho ‘Address Input to Output Delay | [| 6 | 9 | as | Refresh Enable = Low) taor ‘Address input to Output Delay [| 16 i= | Refresh Enable = Low = too Row Enable to Output Delay 7 12 | ns | Refresh Enable = Low2)!3) : too Row Enable to Output Delay 12 28 Refresh Enable = Low = teo Refresh Enable to Output Delay | 7 | 14 | 27 | ns | Notes2,3 ‘eon Refresh Enable to Output Delay | 12) 30 | 45 | ns | fc Counting Frequency _ 5 | Mz terw Count Pulse Width | ns | tez Count to Zero Detect 70 ns_| Note3 Notes: 1. Typical values are for Ta = 25°C and Vc = 5.0V. 2. Ta = 28°C, Voc = 5.0V. 3. CL= 18 pF. A.C. TIMING WAVEFORMS (Typically used with 2116) NORMAL CYCLE ROW ENABLE ‘ 15v Me i N | | Vor AeA 15v ; . le t05—— Ww— RernesH Nase REFRESH CYCLE Yin thas uv Mu | | Fo tenw cor” [ 13v be 0-4} eo ‘cz —- Yow ERD DETECT av Myo nt 2-27
a Absolute Maximum Ratings* “COMMENT: All Input, Output, or is a stress rating only and functional operation of the device extended periods may affect device reliability. ce D.C. and Operating Characteristics All Limits Apply for Vec = 5.0V +10%, T, = 0°C to + 75°C SYMBOL | PARAMETER LuMITs UNIT | TEST CONDITIONS _ MIN TYP.(i)| MAK. h Input Load Current | 004 [0.25 | ma_| Vix = 0.48V, Note 2 le Input Leakage Current __ 0.01 10 Vis = 5.5V Yin Input High Voltage _ 20 Ws Input Low Voltge en Vor ‘Output Low Voltage [028 [ 040 [| V [bu = 8mA Vout Output High Voltage (Gv-O«) 30 | 40 a Tou = —1mA Vow Output High Voltage 24 | 33 Vv | ton = —1ma | (Zero Detect) le Power Supply Current | 105 | 165 | mA | Vic =55V Notes: 1. Typical values are for Ta = 25°C and Veg = §.0V. 2. Inputs are high impedance, TTL compatible, and suitable for bus operation. a Packaging Information
28 LEAD HERMETIC DUAL IN-LINE PACKAGE
1.470 (37.238) l 4490 (96.322) ! 1530 (12.462) S10 (12964) 22s wax. i Muse “| — —— x00 14.5721 PLANE” 300 feo VV Tovesam 18 (oxen un 5 cae ‘oa (e205 ayo arse) | [790 OTB), celle oes osen [00 | 080 (2.286) yas) “O14 (0.356) ae 1820 2-28
PIN NAMES AND FUNCTIONS 2. Row addresses (Ap through Ag). Pin Pin 3. Column addresses (A7 through Ay3). sount tive low input increments internal 7- . . Input’ bit counter by one for each count pulse When refresh is requested, the refresh enable input is high.
2 Refresh Active high input which determines one, sequencing the outputs (Oo—Og) through 128 row ad-
11,1312, Go-Hg Address outputs to memories. Inverted flip-flop must be driven by the Zero Detect. 18,17,16, Outouts with respect to address inputs.
19 Distributed Refresh Mode
The inputs are high impedance, TTL compatible, and suitable for bus device address hold time.
- Row, Column and Refresh Address multiplexing. (wih Retesh Enable su tow input addresses A7—Ay3 are
- Address Counting for burst or distributed refresh. ba an e outpu ° applies © the ven memories
- Refresh addresses (from internal counter). bered when checking out the memory system.
Figure 1. Typical Connection of 3242 and 2116 Memories.