317697-001 INTEL | Alldatasheet
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Technical content
Datasheet sections
- 82575 Gigabit Ethernet Controller Datasheet
- 1.0 Introduction
- 1.1 Document Scope
- 1.2 Reference Documents
- 1.3 Block Diagram
- 2.0 Features of the 82575 Gigabit Ethernet Controller
- 2.1 PCI Express Features
- 2.2 MAC-Specific Features
- 2.3 PHY-Specific Features
- 2.4 Host Offloading Features
- 2.5 Manageability Features
- 2.6 Additional Device Features
- 2.7 Technology Features
- 3.0 Signal Descriptions and Pinout List
- 3.1 Signal Type Definitions
- 3.2 PCI Express Interface
- 3.3 Power Management Signals
- 3.4 System Management Interface Signals
- 3.5 MDIO Signals
- 3.6 SPI EEPROM and FLASH Signals
- 3.7 LED Signals
- 3.8 Other Signals
- 3.9 Crystal Signals
- 3.10 PHY Analog Signals
- 3.11 Serializer/Deserializer Signals
- 3.12 Test Interface Signals
- 3.13 Power Supply Connections
- 3.13.1 Digital and Analog Supplies
- 3.13.2 Grounds, Reserved Pins and No Connects
- 4.0 Pinout/Signal Name
- 5.0 Power Requirements
- 5.1 Targeted Absolute Maximum Ratings
- 5.2 Targeted Recommended Operating Conditions
- 6.0 Thermal
- 7.0 Electrical Specification
- 7.1 DC Specifications
- 7.2 Resets
- 7.3 Pull-up and Pull-down Specifications and Signal s
- 7.4 Targeted AC Characteristics
- 8.0 Crystal Requirements
- 9.0 LED Configuration
- 10.0 Mechanical Information
- 10.1 Targeted Package Information
- 10.2 Visual Pin Assignments
Intel® 82575 Gigabit Ethernet Controller Datasheet v1.00 June 2007 317697-001
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82575 Gigabit Ethernet Controller Datasheet
Revision History
August 2005 0.10 Initial Release January 2006 0.25 Added general in formation, updated pins list July 2006 0.50 Removed information regarding Fast Management Link; added general information February 2007 0.75 Added measured power values; corrected Visual Pin Assignment Diagrams (RBIAS0_N and RBIAS1_N corrected to VSS). June 2007 1.0 Updated classification, changed RMII to NC-SI, updated pin list, updated NC-SI timing specs. changed LAN_PWR_GOOD to Internal_Power_On_Reset.
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1.0 Introduction
The Intel® 82575 Gigabit Ethernet Controller is a single, compact component with two fully integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) ports. The device uses the PCI Express Base Specification, Rev.1.1RD. The Intel 82575 provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3z, 802.3u, and 802.3ab). Ports also contain a Serializer-Deserializer (SERDES) to support 1000Base-SX/LX (optical fiber) and Gigabit backplane applications. In addition to managing MAC and PHY Ethernet layer functions, the controller manages PCI Express packet traffic across its transaction, link, and physical/logical layers. The SERDES can be used in SGMII mode to connect to external PHY, either on-board or via the SFP connector. The Intel 82575’s on-board System Management Bus (SMB) ports enable network manageability implementations required by information technology personnel for remote control and alerting via the LAN. With SMB, management packets can be routed to or from a management processor. Enhanced pass-through capabilities also allow system remote control over standardized interfaces. Also included is a new manageability interface, NC-SI that supports the DMTF preOS sideband protocol. An internal management interface called MDIO enables the MAC (and software) to monitor and control the PHY. Both ports support the Wake on LAN feature. The 82575 Gigabit Ethernet Controller with PCI Express architecture is designed for high performance and low memory latency. The device is optimized to connect to a system Memory Control Hub (MCH) using four PCI Express lanes. Alternatively, the 82575 controller can connect to an I/O Control Hub that has a PCI Express interface. Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. Combining a parallel and pipe-lined logic architecture optimized for Gigabit Ethernet and independent transmit and receive queues, the 82575 controller efficiently handles packets with minimum latency. The 82575 controller includes advanced interrupt handling features, including MSI-X support. The 82575 uses efficient ring buffer descriptor data structures, with up to 64 packet descriptors cached on chip. A large 48 KByte per port on-chip packet buffer maintains superior performance. In addition, using hardware acceleration, the controller offloads tasks from the host, such as TCP/UDP/IP checksum calculations and TCP segmentation. The 82575 operation can be configured using EEPROM and FLASH; it can be also be used in EEPROM-less configurations. The 82575 is packaged in a 25mm X 25mm, 576-pin flip chip ball grid array (FCBGA).
1.1 Document Scope
This document contains targeted datasheet specifications for the 82575 Gigabit Ethernet Controller, including signal descriptions, DC and AC parameters, packaging data, and pinout information.
1.2 Reference Documents
This application assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide additional information: 82575 Gigabit Ethernet Controller Design Guide. Intel Corporation. Intel Ethernet Controllers Timing Device Selection Guide. Intel Corporation. PCI Express Base Specification, Revision 1.1.
PCI Express Card Electromechanical Specification, Revision 1.0a. PCI Special Interest Group. PCI Bus Power Management Interface Specification, Revision 1.1. PCI Special Interest Group. IEEE Standard 802.3, 2002 Edition. Institute of Electrical and Electronics Engineers (IEEE). This version incorporates various IEEE standards previously published separately. System Management Bus (SMBus) Specification, SBS Implementers Forum, Ver. 2.0, August 2000. INF-8074i Specification for SFP (Small Form factor Pluggable) Transceiver.
1.3 Block Diagram
Figure 1. 82575 Gigabit Ethernet Controller Block Diagram
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2.0 Features of the 82575 Gigabit Ethernet Controller
2.1 PCI Express Features
2.2 MAC-Specific Features
Uses x4 PCI Express interface on MCH device
- Bus sharing not required
- Low latency path to memory
- Relieves congestion for IO devices connected to ICH Peak bandwidth 2 GB/s in each direction per PCI Express lane • Supports Gigabit Ethernet at full wire speed PCI Express Power Management
- Compatible extensions to PCI power management and ACPI
- PE_WAKE_N available for wakeup event High bandwidth density per pin • Less congested board routing 64-bit address support for systems using more than 4 GB of physical memory • Features Benefits I/O Acceleration Technology2 (IOAT2) • Accelerated TCP I/O. Four optimized transmit and receive queues • Network packets handled without waiting or buffer overflow. IEEE 802.3x compliant flow control support with software controllable pause times and threshold values
- Control over the transmissions of pause frames through software or hardware triggering
- Frame loss reduced from receive overruns Caches up to 64 packet descriptors (per queue) • Efficient use of PCI Express bandwidth Separate transmit and receive queues per port • Efficient packet prioritization Programmable host memory receive buffers (256 Bytes to 16 KBytes) and cache line size (64 Bytes to 128 Bytes)
- Efficient use of PCI Express bandwidth Wide, pipelined internal data path architecture • Low latency data handling
- Superior DMA transfer rate performance Dual 8 KByte configurable Transmit and Receive FIFO buffers
- No external FIFO memory requirements
- FIFO size adjustable to application Descriptor ring management hardware for transmit and receive • Simple software programming model Optimized descriptor fetching and write-back mechanisms
- Efficient system memory and use of PCI Express bandwidth
2.3 PHY-Specific Features
2.4 Host Offloading Features
Mechanism available for reducing interrupts generated by transmit and receive operations • Maximizes system performance and throughput Support for transmission and reception of packets up to 9.5 kB
- Enables jumbo frames MSI-X Support
- Part of the PCI standard, enables sending interrupt messages to specific CPUs in a multiple- cores platform Features Benefits Features Benefits IEEE 802.3x compliant flow control support with software controllable pause times and threshold values Control over the transmissions of pause frames through software or hardware triggering Frame loss reduced from receive overruns Line Length >140m Reliable op eration at greater distances Operates with worst-case cable Reliability Supports carrier extension and packet bursting (half duplex) Improves performance Auto-negotiation with support for Next Page Improves performance and reliability PMA loopback capable (No echo cancel) Facillitates testing/troubleshooting Advanced Power Management -
- Low power link up
- "Smart Power Down - Link disconnect Improves power capabilities Support for limited auto MDIO register init - limited number of registers Improves performance Fiber/Copper switch support Ease of design SERDES Signal Detect and support of non-AN partner Smart Speed Auto crossover for MDI Smart Power Down Advanced Cable Diagnostics Features Benefits Transmit and receive IP, TCP and UDP checksum off-loading capabilities • Lower CPU utilization Transmit TCP segmentation
- Increased throughput and lower CPU utilization
- Large send offload feature (in Microsoft* Windows* XP) compatible IPv6 Offloading • Checksum and segmentation capability extended to new standard packet type
2.5 Manageability Features
Header split replication in receive • Helps the driver to focus on the relevant part of the packet without the need to parse it. Advanced packet filtering
- 16 exact matched packets (unicast or multicast)
- 4096-bit hash filter for multicast frames
- Promiscuous (unicast and multicast) transfer mode support
- Optional filtering of invalid frames IEEE 802.1q VLAN support with VLAN tag insertion, stripping and packet filtering for up to 4096 VLAN tags
- Ability to create multiple virtual LAN segments Double Vlan • Insert in Tx and extract in Rx Descriptor ring management hardware for transmit and receive
- Optimized fetching and write-back mechanisms for efficient system memory and PCI bandwidth usage 9.5 kByte jumbo frame support • High throughput for large data transfers on networks supporting jumbo frames Receive Side Scaling (RSS) • Multiple Rx queues VMDq
- Virtualization environment. In this environment, packets dedicated to different virtual machines can be routed to different queues, thus easing the routing of these packets to the target machine. Direct Cache Access (DCA)
- The IO device activates a pre-fetch engine in the CPU that loads the data into the CPU cache ahead of time, before use, eliminating cache misses and reducing CPU load. Fragmented UDP checksum offload for packet reassembly • Features Benefits Features Benefits Advance Pass Through-compatible management packet Tx/Rx support ASF 1.0 and Alert on LAN 2.0 Both ports support Wake on LAN (WoL) SMBus port Network management flexibility NC-SI high-bandwidth interface Manageability DMTF preOS sideband protocol support On-board microcontroller Promotes customized designs Allows packets routing to and from either LAN port and a server management processor Preboot eXecution Environment (PXE) Flash interface support (32-bit and 64-bit) Local Flash interface for PXE image iSCSI Boot Network Management Feature
2.6 Additional Device Features
Compliance with PCI Power Management 1.1 and ACPI 2.0 register set compliant including:
- D0 and D3 power states
- Network Device Class Power Management Specification 1.1 PCI power management capability requirements for PC and embedded
applications
SNMP and RMON statistic counters Easy system monitoring with industry standard consoles SDG 3.0, WfM 3.0, and PC2001 compliance Remote network management capabilities through DMI 2.0 and SNMP software Watchdog Timer Used to give an indication to the manageability firmware or external devices that the 82575 or the driver is not functioning. SGMII interface for embedded applications with an I2C or MDC/MDIO control interface. Ease of embedded designs Features Benefits Features Benefits Two complete Gigabit Ethernet connections in a single device
- Inherent dual port teaming ability
- High availability using one port for failover
- Higher throughput than single Gigabit Ethernet port
- Lower latency due to one electrical load on the bus
- Saves critical board space
- Reduced multi-port Gigabit Ethernet costs Integrated SERDES • Supports backplane and fiber applications as well as copper-based Gigabit via the SGMII interface Four activity and link indication outputs (per port) that directly drive LEDs
- Link and activity indications (10, 100, and 1000 Mbps) on each port Programmable LED functionality
- Software definable function (speed, link, and activity) and blinking allowing flexible LED implementations Internal PLL for clock generation can use a 25 MHz crystal • Lower component count and system cost JTAG (IEEE 1149.1) Test Access Port built in silicon
- Simplified testing using boundary scan
- Supports the IDCODE instruction Four software definable pins per port • Additional flexibility for LEDs or other low speed I/O devices Provides loopback capabilities • Validates silicon integrity Four-wire SPI EEPROM interface •S t a n d a r d
2.7 Technology Features
- For information about operating the 82575 outside of this range, please refer to the 82575 Thermal Management Application Note. Features Benefits 576-pin Flip-Chip Ball Grid Array (FC-BGA) package • 25 mm X 25 mm Operating temperature: 1000BASE-T, 0 °C to 55 °C* 1000BASE-SX/LX (or SERDES backplane), 0 °C to 70 °C Storage temperature 65 °C to 140 °C
- Simple thermal design Typical targeted power dissipation:
2.43 W @ D0 1000 Mbps
0.79 W @ D3cold 100 Mbps (wakeup enabled)
0.29 W @ D3cold (wakeup disabled)
- Conditions: FF materials, nominal voltage, 115 °C
- Minimizes impact of incorporating Gigabit instead of Fast Ethernet. Maxmum Payload Size: 128 and 256 • Max number of transactions (TLP) supported on PCIe: Four TX DMA requests + 1 TX descriptor + 1 RX descriptor
3.0 Signal Descriptions and Pinout List
The targeted signal names are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design.
3.1 Signal Type Definitions
The signals of the 82575 controller are electrically defined as follows:
3.2 PCI Express Interface
Name Definition DC specification I Input Standard input only digital signal. See Table 9 O Output Standard output only digital signal. See Table 9 TS Tri-state Bi-directional three-state digital input/ output signal. See Table 9 OD Open Drain Wired-OR with other agents. The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully restore the signal to the de- asserted state. See Table 10 A Analog PCI Express*, SERDES, or PHY analog signal. See Table 10 P Power Power connection, voltage reference, or other reference connection. See Table 10 Symbol Type Name and Function PER_0_N PER_0_P PER_1_N PER_1_P PER_2_N PER_2_P PER_3_N PER_3_P A(I) High Speed Serial Receive Data These signals connect to corresponding PETn and PETp signals on a system motherboard or a PCI Express connector. Series AC coupling capacitors are required at the transmitter end. The PCI Express differential inputs are clocked at 2.5 Gb/s.
3.3 Power Management Signals
PET_0_N PET_0_P PET_1_N PET_1_P PET_2_N PET_2_P PET_3_N PET_3_P A(0) High Speed Serial Transmit Data These signals connect to corresponding PERn and PERp signals on a system motherboard or a PCI Express connector. Series AC coupling capacitors are required at the 82575 controller end. The PCI Express differential outputs are clocked at 2.5 Gb/s. PE_RCOMP A High Speed Serial Impedance Compensation Connect the recommended resistor value 1.4K Ω from this ball to ground. PE_CLK_P PE_CLK_N A
100 MHz Differential Clock for the PCI Express Interface
The reference clock is furnished by the system and has a 300 ppm frequency tolerance. PE_RST_N I PCI Express Reset When the signal is low, all PCI Express functions are held in reset. When the signal is high, it denotes that main power is available to the 82575 controller and the reference clock is running. In systems with a PCI Express add-in card, this signal routes to the connector. PE_WAKE_N OD Wake The device drives this signal low when it receives a wake-up event and either the PME Enable bit in the Power Management Control/Status Register or the Advanced Power Management Enable (APME) bit of the Wake-up Control Register (WUC) is 1b. Symbol Type Name and Function Symbol Type Name and Function AUX_PWR I Auxiliary Power Present. If the Auxiliary Power signal is high, then auxiliary power is present and the 82575device should support the D3cold power state. LAN0_DIS_N LAN1_DIS_N I LAN Disables 0 and 1 Disables individual Ethernet ports. State is latched upon a rising edge of PERST_N or a PCI Express reset event. This pin has an internal pull-up resistor. DEV_OFF_N I Device Off Asynchronously disables Ethernet controller. MAIN_PWR_OK I Main Power OK Indicates that platform main power is up. Must be connected externally.
3.4 System Management Interface Signals
3.5 MDIO Signals
Symbol Type Name and Function SMBCLK OD SMB Clock The SMB Clock signal is an open drain signals for the serial SMB interface. SMBD OD SMB Data The SMB Data signal is an open drain signal for the serial SMB interface. SMBALRT_N OD SMB Alert The SMB Alert signal is an open drain signal for serial SMB Port A. In ASF mode, this signal acts as a power good input. It acts as an alert input in 82559 compatible mode. NCSI_CLK_IN I NCSI Reference Clock Input. Synchronous clock reference for receive, transmit and control interface. It is a 50MHz clock /- 50 ppm. NCSI_CLK_OUT O NCSI Reference Clock Output. Synchronous clock reference for receive, transmit and control interface. It is a 50MHz clock /- 50 ppm. Serves as a clock source to the BMC and Zoar (when configured so). NCSI_CRS_DV O Carrier Sense / Receive Data Valid NCSI_RXD[1] NCSI_RXD[0] O Receive Data. Data signals from the device to the BMC NCSI_TX_EN I Transmit Enable NCSI_TXD[1] NCSI_TXD[0] I Transmit Data. Data signals from BMC to the device Symbol Type Name and Function MDC I Management Data Clock. Used by the PHY as a clock timing reference for information transfer on the MDIO signal. The MDC is not required to be a continuous signal and can be frozen when no management data is transferred. The MDC signal has a maximum operating frequency of 2.5MHz. MDIO I/O Management Data I/O. This internal signaling between the MAC and PHY logically represents a bi-directional data signal used to transfer control information and status to and from the PHY (to read and write the PHY management registers ). Asserting and interpreting value(s) on this interface requires knowledge of the special MDIO protocol to avoid possible internal signal contention or miscommunication to/from the PHY
3.6 SPI EEPROM an d FLASH Signals
3.7 LED Signals
Note: The LED signals are push-pull (active-high) outputs. They are fully programmable through the EEPROM interface Symbol Type Name and Function EE_DI TS EEPROM Data Input The EEPROM Data Input pin is used for output to the SPI EEPROM memory device. EE_DO I EEPROM Data Output The EEPROM Data Output pin is used for input from the SPI EEPROM memory device. The EE_DO includes an internal pull-up resistor. EE_CS_N TS EEPROM Chip Select The EEPROM Chip Select signal is used to enable the device. EE_SK TS EEPROM Serial Clock The EEPROM Shift Clock provides the clock rate for the SPI EEPROM interface, which is approximately 2 MHz. FLSH_CE_N TS FLASH Chip Enable Output. Used to enable FLASH device. FLSH_SCK TS FLASH Serial Clock Output. FLSH_SI TS FLASH Serial Data Input. This pin is an output to the memory device. FLSH_SO I FLASH Serial Data Output This pin is an input from the memory device. Symbol Type Name and Function LED0_0 O LED0_0. Programmable LED output for Port A. As the Link LED, it indicates link connectivity on Port A. LED0_1 O LED0_1. Programmable LED output for Port A. As the Activity LED, it flashes to indicate receive activity on Port A for packets destined for this node. LED0_2 O LED0_2 Programmable LED output for Port A. As the Link 100 LED, it indicates link at 100 Mbps for Port A. LED0_3 O LED0_3 Programmable LED output for Port A. As the Link 1000 LED, it indicates link at 1000 Mbps for Port A. LED1_0 O LED1_0. Programmable LED output for Port B. As the Link LED, it indicates link connectivity on Port B.
3.8 Other Signals
3.9 Crystal Signals
LED1_1 O LED1_1 Programmable LED output for Port B. As the Activity LED, it flashes to indicate receive activity on Port B for packets destined for this node. LED1_2 O LED1_2 Programmable LED output for Port B. As the Link 100 LED, it indicates link at 100 Mbps for Port B. LED1_3 O LED1_3 Programmable LED output for Port B. As the Link 1000 LED, it indicates link at 1000 Mbps for Port B. Symbol Type Name and Function Symbol Type Name and Function SDP0_0 SDP0_1 SDP0_2 SDP0_3 SDP1_0 SDP1_1 SDP1_2 SDP1_3 TS Software Defined Pin (SDP) The Software Defined Pins are programmable with respect to input and output capability. These pins also can optionally be configured as interrupt inputs. SDP signals default to inputs upon power-up, but can be configured differently by the EEPROM. Symbol Type Name and Function XTAL1 AI Crystal One The Crystal One pin is a 25 MHz input signal. It should be connected to a parallel resonant crystal with a frequency tolerance of 30 ppm or better. The other end of the crystal should be connected to XTAL2. XTAL2 AO Crystal Two Crystal Two is the output of an internal oscillator circuit used to drive a crystal into oscillation.
3.10 PHY Analog Signals
Symbol Type Name and Function RBIAS0_P/RBIAS1_P A Compensation Reference Resistor. A 1.4 KΩ, 1% tolerance resistor should be used. RBIAS_N should also be connected to ground (VSS). MDI0_P_0 MDI0_N_0 MDI1_P_0 MDI1_N_0 A Media Dependent Interface [0] 1000BASE-T: In MDI configuration, these correspond to BI_DA+/-, and in MDI-X configuration, MDIp0/MDIn0 corresponds to BI_DB+/-. 100BASE-TX: In MDI configuration, MDIp0/MDIn0 is used for the transmit pair, and in MDI-X configuration, MDIp0/MDIn0 is used for the receive pair. 10BASE-T: In MDI configuration, MDIAp0/MDI_MINUS0_0 is used for the transmit pair, and in MDI-X configuration, MDIp0/ MDIn0 is used for the receive pair. MDI0_P_1 MDI0_N_1 MDI1_P_1 MDI1_N_1 A Media Dependent Interface [1] 1000BASE-T: In MDI configuration, MDIp1/MDIn1 corresponds to BI_DB+/-, and in MDI-X configuration, MDIp1/ MDIn1 corresponds to BI_DA+/-. 100BASE-TX: In MDI configuration, MDIp1/MDIn1 is used for the receive pair, and in MDI-X configuration, MDIp1/MDIn1 is used for the transit pair. 10BASE-T: In MDI configuration, MDIp1/MDIn1 is used for the receive pair, and in MDI-X configuration, MDIp1/MDIn1 is used for the transit pair. MDI0_P_2 MDI0_N_2 MDI1_P_2 MDI1_N_2 A Media Dependent Interface [2] 1000BASE-T: In MDI configuration, MDIp2/MDIn2 corresponds to BI_DC+/-, and in MDI-X configuration, MDIp2/ MDIn2 corresponds to BI_DD+/-. 100BASE-TX: Unused. 10BASE-T: Unused. MDI0_P_3 MDI0_N_3 MDI1_P_3 MDI1_N_3 A Media Dependent Interface [3] 1000BASE-T: In MDI configuration, MDIp3/MDIn3 corresponds to BI_DD+/-, and in MDI-X configuration, MDIp3/ MDIn3 corresponds to BI_DC+/-. 100BASE-TX: Unused. 10BASE-T: Unused.
3.11 Serializer/Deserializer Signals
3.12 Test Interface Signals
Note: Pull-up resistors are needed on these signals as shown in the reference schematic. Symbol Type Name and Function SRDSI_0_P SRDSI_0_N SRDSI_1_P SRDSI_1_N AI SERDES Receive Pairs A and B These signals make the differential receive pair for the 1.25 GHz serial interface. For serializer/deserializer operation, the inputs should be coupled to ECL voltage levels. If the SERDES interface is not used, these pins should not be connected. SRDSO_0_P SRDSO_0_N SRDSO_1_P SRDSO_1_N AO SERDES Transmit Pairs A and B These signals make the differential transmit pair for the 1.25 GHz serial interface. For serializer/deserializer operation, the outputs drive the LVPECL voltage levels. If the SERDES interface is not used, these pins should not be connected. SRDS0_SIG_DET/ SRDS1_SIG_DET I Signal Detects A and B These pins indicate whether the SERDES signals (connected to the
1.25 GHz serial interface) have been detected by the optical
transceivers. If the SERDES interface is not used with copper media, these can be left with no connection (NC). If the SERDES interface is not used with fiber media, the SIG_DET inputs should be tied high to VCC. SER_RCOMP A SERDES Impedance Compensation. Connect the recommended resistor (1.4K Ω) from this ball to ground. SFP0_I2C_CLK O Port 0 SFP I2C clock. Connects to Mod-Def1 input of SFP. Can also be used as MDC pin. SFP0_I2C_DATA TS/ OD Port 0 SFP I2C data. Connects to Mod-Def2 pin of SFP. Can also be used as MDIO pin SFP1_I2C_CLK O Port 1 SFP I2C clock. Connects to Mod-Def1 input of SFP. Can also be used as MDC pin. SFP1_I2C_DATA TS/ OD Port 1 SFP I2C data. Connects to Mod-Def2 pin of SFP. Can also be used as MDIO pin Symbol Type Name and Function JTCK I JTAG Test Access Port Clock JTDI I JTAG Test Access Port Test Data In JTDO OD JTAG Test Access Port Test Data Out JTMS I JTAG Test Access Port Mode Select
3.13 Power Supply Connections
3.13.1 Digital and Analog Supplies
3.13.2 Grounds, Reserved Pins and No Connects
4.0 Pinout/Signal Name
Table 1. Pinout VCC3P3 P 3.3 V Digital Power Supply.
1.8 V Analog Power Supply
Connect all 1.8 V pins to a single power supply.
1.0 V Digital Power Supply
all 1.0 V pins to a single power supply. pull-up or pull-down resistors. This pin is not connected internally.
PET_0_P D2 PET_0_N D1 PET_1_P H2 PET_1_N H1 PET_2_P R2 PET_2_N R1 PET_3_P W2 PET_3_N W1 PER_0_P F2 PER_0_N F1 PER_1_P K2 PER_1_N K1 PER_2_P U2 PER_2_N U1 PER_3_P AA2 PER_3_N AA1 PE_WAKE_N AC20 PE_RST_N AC9 PE_RCOMP L1 RSVDM3_NC M3 RSVDM2_NC M2 FLSH_SI AC14 FLSH_SO AD14 FLSH_SCK AD15 FLSH_CE_N AC15
EE_DI A21 EE_DO A20 EE_SK B20 EE_CS_N B21 SMBD AD21 SMBCLK AC21 SMBALRT_N AD20 RSVDAD17_NC AD17 RSVDAC17_NC AC17 RSVDAC16_NC AC16 RSVDAD16_NC AD16 NCSI_CLK_IN B5 NCSI_CLK_OUT B4 NCSI_CRS_DV A4 NCSI_RXD_1 A6 NCSI_RXD_0 B7 NCSI_TX_EN B6 NCSI_TXD_1 A7 NCSI_TXD_0 B8 SDP0_0 A16 SDP0_1 B16 SDP0_2 B17
SDP0_3 B15 SDP1_0 AD10 SDP1_1 A12 SDP1_2 A13 SDP1_3 AC10 RSVDAB19_NC AB19 RSVDAB18_NC AB18 RSVDAD9_3P3 AD9 MAIN_PWR_OK AD4 DEV_OFF_N B9 RSVDL14_1P0 L14 RSVDP14_1P0 P14 XTAL1 N23 XTAL2 N24 SRDSI_0_P J23 SRDSI_0_N J24 SRDSO_0_P K23 SRDSO_0_N K24 SRDS0_SIG_DET A9 SRDSI_1_P T23 SRDSI_1_N T24 SRDSO_1_P R23 SRDSO_1_N R24
SRDS1_SIG_DET A10 SER_RCOMP L22 RSVDM23_NC M23 RSVDM24_NC M24 SFP0_I2C_CLK/ MDC0 AD19 SFP0_I2C_DATA/ MDIO0 AD18 SFP1_I2C_CLK/ MDC1 AC19 SFP1_I2C_DATA/ MDIO1 AC18 LED0_0 A19 LED0_1 B19 LED0_2 B18 LED0_3 A18 LED1_0 AD13 LED1_1 AC11 LED1_2 AC13 LED1_3 AC12 MDI0_P_0 C24 MDI0_N_0 C23 MDI0_P_1 D24 MDI0_N_1 D23 MDI0_P_2 F24 MDI0_N_2 F23 MDI0_P_3 G24
MDI0_N_3 G23 RBIAS0_P E22 VSS F22 IEEE_TEST0_P A22 IEEE_TEST0_N B22 MDI1_P_0 AB24 MDI1_N_0 AB23 MDI1_P_1 AA24 MDI1_N_1 AA23 MDI1_P_2 W24 MDI1_N_2 W23 MDI1_P_3 V24 MDI1_N_3 V23 RBIAS1_P Y22 VSS W22 IEEE_TEST1_P AD22 IEEE_TEST1_N AC22 RSVDAD8_VSS AD8 JTCK AC6 JTDI AD7 JTDO AC8 JTMS AC7 RSVDAC5_NC AC5 AUX_PWR B14 LAN1_DIS_N A15
RSVDB12_NC B12 LAN0_DIS_N B13 RSVDA8_3P3 A8 RSVDA11_3P3 A11 RSVDB10_3P3 B10 RSVDB11_3P3 B11 RSVDA14_VSS A14 NCB3 B3 NCAC3 AC3 NCAD3 AD3 VCC3P3 AD6 VCC3P3 AD12 VCC3P3 A5 VCC3P3 A17 VCC1P8 P5 VCC1P8 P4 VCC1P8 N9 VCC1P8 N8 VCC1P8 N5 VCC1P8 N4 VCC1P8 M9 VCC1P8 M8 VCC1P8 M5 VCC1P8 M4 VCC1P8 L9 VCC1P8 L8 VCC1P8 L5 VCC1P8 L4 VCC1P8 L15 VCC1P8 K15
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5.0 Power Requirements
5.1 Targeted Absolute Maximum Ratings
5.2 Targeted Recommended Operating Conditions
5.2.1 General Operating Conditions
Table 2. Absolute Maximum Ratings 1
3.3 V I/O Voltage
1.8 V I/O Voltage
1.0 V I/O Voltage
- Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings
- During normal device power up and power down, the 1.8 V and 1.0 V supplies must not ramp before the 3.3
Table 3. Recommended Operating Conditions 1
- Sustained operation of the device at conditions exceeding these values, even if they are within the absolute
not guaranteed, if conditions exceed recommended operating conditions.
5.2.2 Voltage Ramp and Sequencing Recommendations
Table 4. 3.3 V Supply Voltage Ramp Table 5. 1.8 V Supply Voltage Ramp Table 6. 1.0 V Supply Voltage Ramp
- Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.
- Excessive overshoot can affect long term reliability.
- Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.
- Excessive overshoot can affect long term reliability.
Table 7. Power Supply Sequencing Figure 2. Voltage Power Sequencing Options capacitors of 3.3 V, 1.8 V and 1.0 V rails.
- Good design practices achieve volt age ramps to within the regulation bands in approximately 20 ms or less.
- Excessive overshoot can affect long term reliability.
3.3 V core to GIO_PWR_GOOD
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6.0 Thermal
7.0 Electrical Specification
7.1 DC Specifications
Table 8. DC Characteristics Table 9. I/O Characteristics
- The input buffer also has hysteresis > 160 mV.
Table 10. Open Drain I/O
- Applies to SMBD0, SMBCLK0, , SMBALRT _N, PE_WAKE_n, SFP1_I2C_Data, SFP0_I2C_Data pads.
- Device meets this whether powered or not.
- Characterized, not tested.
Table 11. Power Consumption
- C in= 2.5 pF(maximum input capacitance), C out = 16 pF (characterized max output load capacitance per 160
- Typical conditions: operating temperature (T A) = 25 C, nominal voltages
and moderate network traffic at full duplex.
- Maximum conditions: maximum operating temperature (T J) values,
typical voltage values and continuous network traffic at full duplex.
3.3 V 18 18 18 23 19 19
1.8 V 344 312 841 856 142 203
1.0 V 304 388 856 1184 354 492
Typ Icc (mA)1 1. Typical conditions: room temperature (TA)=25C, nominal voltages and idle network (no traffic) at full duplex
3.3 V 18
1.8 V 129
1.0 V 264
- Known errata on LOs & L1 states might impact devide power consumption 0.56 D0a--Idle Link @10Mbps LOs only Typ Icc (mA)1 1. Typical conditions: room temperature (TA)=25C, nominal voltages and idle network (no traffic) at full duplex 3.3 V
1.8 V 140
1.0 V 302
- Known errata on LOs & L1 states might impact devide power consumption 0.61 W D0a--Idle Link @100Mbps (Copper) LOs only Typ Icc (mA)1
1.8 V 837
1.0 V 755
2.32 W 1. Typical conditions: room temperature (TA)=25C, nominal voltages and idle network (no traffic) at full duplex 2. Known errata on LOs & L1 states might impact devide power consumption D0a--Idle Link @1000Mbps (SERDES) Typ Icc (mA) 1. Typical conditions: room temperature (TA)=25C, nominal voltages and idle network (no traffic) at full duplex 3.3 V
1.8 V 142
1.0 V 341
- Known errata on LOs & L1 states might impact devide power consumption 0.65 W D3cold - wake-up enabled D3cold- wake disabled@10 Mbps @100 Mbps Typ Icc (mA) Typ Icc (mA) Typ Icc (mA)
3.3 V 18 18 18
@100Mbps (Copper) LOs only Typ Icc (mA)1
7.2 Resets
Power-on Reset (internal): The 82575 has an internal mechanism for sensing the power pins. Once the power is up and stable, it creates an internal reset, this reset acts as a master reset of the entire chip. It is level sensitive, and while it is 0, will hold all of the registers in reset. Power-on Reset is interpreted to be an indication that device power supplies are all stable. Power-on Reset changes state during system power-up. In-band PCIe Reset: The 82575 will generate an internal reset in response to a physical layer message from the PCIe or when the PCIe link halts (entry to Polling or Detect state). This reset is equivalent to PCI reset in previous (PCI) gigabit LAN controllers. Main_Power_Good: Used by the device to detect the D3Cold condition and activate part of the power saving scheme. Also used to change the state of the ASF manageability firmware.
1.8 V 98 269 83
1.0 V 168 249 70
0.40 W 0.79 W 0.29 W D(r) Uninitialized Disabled through DEV_OFF_N Typ Icc (mA)
3.3 V 11
1.8 V 179
1.0 V 283
Power 0.64 D3cold - wake-up enabled D3cold- wake disabled@10 Mbps @100 Mbps Typ Icc (mA) Typ Icc (mA) Typ Icc (mA)
7.3 Pull-up and Pull-down Specifications and Signals
Table 12. Internal and External Pull-up and Pull-down Values For external Pull-up requirements, see the 82575 reference schematics. ranging from 2.7KΩ to 8.6KΩ. Table 13. Internal Pull-up and Ex ternal Pull Up Requirements
NCSI_CLK_IN N N N N NCSI_CLK_OUT Y N N N NCSI_CRS_DV N N N Y Pull down only if NCSI is NOT being used or configured for multi drop NCSI_RXD[1:0] N N N Y Pull Up only if NCSI is NOT being used or configured for multi drop NCSI_TX_EN N N N N Should be connected to external PD if NCSI is NOT used NCSI_TXD[1:0] N N N N Should be connected to external PD if NCSI is NOT used SDP0[3:0] Y Y N N SDP1[3:0] Y Y N N DEV_OFF_N Y N N Must be connected on board MAIN_PWR_OK Y N N Must be connected on board SRDS_0_SIG_DET Y N N Must be connected externally SRDS_1_SIG_DET Y N N Must be connected externally SFP0_I2C_CLK Y N Y Y if active If used. SFP0_I2C_DATA Y N N Y If used. SFP1_I2C_CLK Y N Y Y if active If used. SFP1_I2C_DATA Y N N Y If used. LED0_0 Y N N LED0_1 Y N N LED0_2 Y N N LED0_3 Y N N LED1_0 Y N N LED1_1 Y N N LED1_2 Y N N LED1_3 Y N N JTCK Y N N N
7.4 Targeted AC Characteristics
Table 14. 25 MHz Clock Input Requirements Table 15. Link Interface Clock Requirements
7.4.1 EEPROM Interface
V, Cload = 1 TTL Gate and 16pF (unless otherwise noted). least 105 clock edges, filtered by HPF with cut off frequency of 5000 Hz).
- GTX_CLK is used externally for test purposes only. See signals IEEE_TEST1_p and IEEE_TEST1_n.
Figure 3. EEPROM Interface Time Diagram
7.4.2 FLASH Interface
Table 16. FLASH Parameters Figure 4. FLASH Timing Diagram
7.4.3 NC-SI Interface
Table 17. NC-SI AC Specification
- Clock Duty cycle measurement: High interval measured from Vih to Vil points, Low from Vil to next Vih
- Clock interval measurement from Vih to Vih
- The input delay test conditions: Ma ximum input level = VIN = 2.7V; Inpu t rise/fall time (0.2VIN to 0.8VIN)
- The NC-SI specification defines a ho ld time of 1.0 ns. In order to wo rk with the 82575, the board designer
should guarantee a hold time of 1.5 ns.
7.4.4 SMBus Interface
Table 18. SMBus AC Characteristics (master mode)
Table 19. SMBus AC Charac teristics (slave mode) Table 20. AC Test Loads for General Output Pins Figure 5. AC Test Loads for General Output Pins
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8.0 Crystal Requirements
Table 21. Reference Crystal Specification Requirements
9.0 LED Configuration
- Mode: Defines which information is reflected by this LED. The encoding is described
- Polarity: Defines the polarity of the LED.
- Blink mode: should the LED blink or be stable.
10.0 Mechanical Information
This section describes the 82575 device physical characteristics. The targeted signal names are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design.
10.1 Targeted Package Information
The 82575device is a 576-lead flip-chip ball grid array (FC-BGA) measuring 25 mm by 25 mm. The nominal ball pitch is 1 mm. See Figure 9. 0.43 mm Solder Resist Opening 0.62 mm Metal Diameter Detail Area
39-"/, -),,)-%4%23 ;).#(%3= #/--%.43 -). -!8 ;= 0/342%&,/7 "!3)# "!3)# "!3)# "!3)# "!3)# "!3)# . "!3)# # ! " 3#!,% "!,,3 0!#+!'% 3%%$%4!),! $%4!),! 3#!,% %0/895.$%2&),, $)% # " # ( 2%02/$5#%$ 3(%%4/& 88¼ $7'./ 3(4 2%6
Figure 6. 82575 Mechanical Specifications
10.2 Visual Pin Assignments
This section contains the illustrations of the pin outs. Figure 7. 82575 Visual Pin As signment Part 1 (Top View)
Figure 8. 82575 Visual Pin A ssignment Part 2 (Top View)
Figure 9. 82575 Visual Pin As signment Part 3(Top View)
Figure 10. 82575 Visual Pin Assignment Part 4 (Top View)