316963-002 INTEL | Alldatasheet
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Technical content
Datasheet sections
- 1.1 Terminology
- 1.1.1 Processor Packaging Terminology
- 1.2 References
- 2 Electrical Specifications
- 2.1 Power and Ground Lands
- 2.2 Decoupling Guidelines
- 2.2.1 Vcc Decoupling
- 2.2.2 Vtt Decoupling
- 2.2.3 FSB Decoupling
- 2.3 Voltage Identification
- 2.4 Market Segment Identification (MSID)
- 2.5 Reserved, Unused and TESTHI Signals
- 2.6 Voltage and Current Specification
- 2.6.1 Absolute Maximum and Minimum Ratings
- 2.6.2 DC Voltage and Current Specification
- 2.6.3 Vcc Overshoot
- 2.6.4 Die Voltage Validation
- 2.7 Signaling Specifications
- 2.7.1 FSB Signal Groups
- 2.7.2 CMOS and Open Drain Signals
- 2.7.3 Processor DC Specifications
- 2.7.3.1 GTL+ Front Side Bus Specifications
- 2.8 Clock Specifications
- 2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
- 2.8.2 FSB Frequency Select Signals (BSEL[2:0])
- 2.8.3 Phase Lock Loop (PLL) and Filter
- 2.8.4 BCLK[1:0] Specifications (CK505 based Platforms)
- 2.8.5 BCLK[1:0] Specifications (CK410 based Platforms)
- 2.9 PECI DC Specifications
- 3 Package Mechanical Specifications
- 3.1 Package Mechanical Drawing
- 3.2 Processor Component Keep-Out Zones
- 3.3 Package Loading Specifications
- 3.4 Package Handling Guidelines
- 3.5 Package Insertion Specifications
- 3.6 Processor Mass Specification
- 3.7 Processor Materials
- 3.8 Processor Markings
- 3.9 Processor Land Coordinates
- 4 Land Listing and Signal Descriptions
- 4.1 Processor Land Assignments
- 4.2 Alphabetical Signals Reference
- 5 Thermal Specifications and Design Considerations
- 5.1 Processor Thermal Specifications
- 5.1.1 Thermal Specifications
- 5.1.2 Thermal Metrology
- 5.2 Processor Thermal Features
- 5.2.1 Thermal Monitor
Document Number: 316963-002 Intel® Celeron® Processor 400Δ Series Datasheet — Supporting the Intel ® Celeron® processor 420Δ, 430Δ, 440Δ, and 450Δ August 2008
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/ processor_number for details. Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or consult with your system vendor for more information. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® Celeron® processor 400 series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Celeron, Pentium, Intel Core, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007–2008 Intel Corporation.
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Revision History
-001 • Initial release June 2007 -002 • Added Intel ® Celeron® processor 450 August 2008
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Intel® Celeron® Processor 400 Series Features The Intel Celeron processor 400 series delivers Intel's advanced, powerful processors for desktop PCs. The processor is designed to deliver performance across applications and usages where end-users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multitasking user environments. Intel® 64 architecture enables the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. The Intel Celeron processor 400 series also include the Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as executable or non-executable.
- Available at 1.60 GHz, 1.8 GHz, 2.00 GHz,
2.2 GHz
- S u p p o r t s I n t e l® 64 architecture
- Supports Execute Disable Bit capability
- Binary compatible with applications running on previous members of the Intel microprocessor line
- FSB frequency at 800 MHz
- Advance Dynamic Execution
- Very deep out-of-order execution
- Enhanced branch prediction
- Optimized for 32-bit applications running on advanced 32-bit operating systems
- Two 32-KB Level 1 data caches
- 1 MB and 512KB Advanced Smart Cache
- Advanced Digital Media Boost
- Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance
- Power Management capabilities
- System Management mode
- Multiple low-power states
- 8-way cache associativity provides improved cache hit rate on load/store operations
- 775-land Package
1 Introduction
The Intel® Celeron® processor 400 series is a desktop processor that combines the performance of the previous generation of Desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems. Intel Celeron Processor 400 is a 64-bit processor that maintain compatibility with IA-32 software. The Intel Celeron processor 400 series uses a Flip-Chip Land Grid Array (FC-LGA6) package technology, and plugs into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the LGA775 socket. Note: In this document the Intel Celeron processor 400 series will be referred to as "the processor." Note: In this document the Intel Celeron processor 400 series refers to the Intel Celeron processors 420, 430, 440, and 450. Based on 65 nm process technology, the Intel Celeron processor 400 series is a single- core processor that features an 800 MHz front side bus (FSB), 1 MB or 512 KB L2 cache, and a thermal design power (TDP) of 35 W. The processor also supports the Execute Disable Bit and Intel® 64 architecture. The processor front side bus (FSB) uses a split-transaction, deferred reply protocol like the Intel® Pentium® 4 processor. The FSB uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "double-clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 6.4 GB/s. Intel will enable support components for the processor including heatsink, heatsink retention mechanism, and socket. Supported platforms may need to be refreshed to ensure the correct voltage regulation (VRD11) and that PECI support is enabled. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling. The processor includes an address bus power-down capability which removes power from the address and data signals when the FSB is not in use. This feature is always enabled on the processor.
1.1 Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level). Front Side Bus” refers to the interface between the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O.
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1.1.1 Processor Packaging Terminology
Commonly used terms are explained here for clarification:
- Intel Celeron Processor 400 Series — Single core processor in the FC-LGA6 package with a 1 MB or 512 KB L2 cache.
- Processor — For this document, the term processor is the generic form of the Intel Celeron processor 400 series. The processor is a single package that contains one exectution unit.
- Keep-out zone — The area on or near the processor that system design can not use.
- Processor core — Processor core die with integrated L2 cache.
- LGA775 socket — The Intel Celeron processor 400 series mates with the system board through a surface mount, 775-land, LGA socket.
- Integrated heat spreader (IHS) —A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.
- Retention mechanism (RM) — Since the LGA775 socket does not include any mechanical features for heatsink attach, a retention mechanism is required. Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket.
- FSB (Front Side Bus) — The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB.
- Storage conditions — Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks. Upon exposure to “free air”(i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.
- Functional operation — Refers to normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical and thermal are satisfied.
- Execute Disable Bit — The Execute Disable bit allows memory to be marked as executable or non-executable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system. See the Intel ® Architecture Software Developer's Manual for more detailed information.
- I n t e l® 64 Architecture — An enhancement to Intel's IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of the Intel® 64 architecture. Further details on Intel® 64 architecture and programming model can be found in the Intel Extended Memory 64 Technology Software Developer Guide at http://developer.intel.com/technology/ 64bitextensions/.
1.2 References
Table 1. References
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2 Electrical Specifications
This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided.
2.1 Power and Ground Lands
The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to V CC, while all VSS lands must be connected to a system ground plane. The processor VCC lands must be supplied the voltage determined by the Voltage IDentification (VID) lands. The signals denoted as VTT, provide termination for the front side bus and power to the I/O buffers. A separate supply must be implemented for these lands, that meets the VTT specifications outlined in Table 5.
2.2 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings. This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic or aluminum-polymer capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 5. Failure to do so can result in timing violations or reduced lifetime of the component.
2.2.1 V CC Decoupling
VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications. This includes bulk capacitance with low effective series resistance (ESR) to keep the voltage rail within specifications during large swings in load current. In addition, ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity. Consult the Voltage Regulator-Down (VRD) 11 Design Guide For Desktop and Transportable LGA775 Socket for further information.
2.2.2 V TT Decoupling
Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. To ensure compliance with the specifications, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors.
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2.2.3 FSB Decoupling
The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation.
2.3 Voltage Identification
The Voltage Identification (VID) specification for the processor is defined by the Voltage Regulator-Down (VRD) 11 Design Guide For Desktop and Transportable LGA775. The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor VCC pins (see Chapter 2.6.3 for VCC overshoot specifications). Refer to Table 13 for the DC specifications for these signals. Voltages for each processor frequency is provided in Table 5. Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings. This is reflected by the VID Range values provided in Table 5. Refer to the Intel ® Celeron® Processor 400 Series Specification Update for further details on specific valid core frequency and VID values of the processor. Please note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2). The processor uses six voltage identification signals, VID[6:1], to support automatic selection of power supply voltages. Table 2 specifies the voltage level corresponding to the state of VID[6:1]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[6:1] = 111111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. The Voltage Regulator-Down (VRD) 11 Design Guide For Desktop and Transportable LGA775 defines VID [7:0], VID7 and VID0 are not used on the processor; VID0 and VID7 is strapped to V SS on the processor package. VID0 and VID7 must be connected to the VR controller for compatibility with future processors. The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (VCC). This will represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage. Transitions above the specified VID are not permitted. Table 5 includes VID step sizes and DC shift ranges. Minimum and maximum voltages must be maintained as shown in Table 6 and Figure 1 as measured across the VCC_SENSE and VSS_SENSE lands. The VRM or VRD utilized must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 5 and Table 6. Refer to the Voltage Regulator-Down (VRD) 11 Design Guide For Desktop and Transportable LGA775 for further details.
Table 2. Voltage Identification Definition
1 VCC_MAX
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2.4 Market Segment Identification (MSID)
2.5 Reserved, Unused and TESTHI Signals
processor and the location of all RESERVED lands. should be left as no connects as GTL+ termination is provided on the processor silicon. However, see Table 8 for details on GTL+ signals that do not include on-die termination. Unused active high inputs, should be connected through a resistor to ground (VSS). TT). For details see Table 14. which matches the nominal trace impedance. Table 3. Market Segment Select ion Truth Table for MSID[1:0]1, 2, 3, 4
- The MSID[1:0] signals are provided to indicate the Market Segment for the processor and may be used for
- These signals are not connected to the processor die.
- A logic 0 is achieved by pulling th e signal to ground on the package.
- A logic 1 is achieved by leaving the signal as a no connect on the package.
00 Intel® Core™2 Duo desktop processor E6000 and E4000 series, Intel ®
01 R e s e r v e d
10 R e s e r v e d
11 Intel
The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group:
- TESTHI[1:0]
- TESTHI[7:2]
- TESTHI8/FC42 – cannot be grouped with other TESTHI signals
- TESTHI9/FC43 – cannot be grouped with other TESTHI signals
- TESTHI10 – cannot be grouped with other TESTHI signals
- TESTHI11 – cannot be grouped with other TESTHI signals
- TESTHI12/FC44 – cannot be grouped with other TESTHI signals
- TESTHI13 – cannot be grouped with other TESTHI signals However, using boundary scan test will not be functional if these lands are connected together. For optimum noise margin, all pull-up resistor values used for TESTHI[13:0] lands should have a resistance value within ± 20% of the impedance of the board transmission line traces. For example, if the nominal trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω should be used.
2.6 Voltage and Current Specification
2.6.1 Absolute Maximum and Minimum Ratings
Table 4 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded. Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields.
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- For functional operation, all processor electrical, signal quality, mechanical and thermal
specifications must be satisfied.
- Excessive overshoot or undersh oot on any signal will likely result in permanent damage to
- Storage temperature is applicable to stor age conditions only. In this scenario, the
processor must not receive a clock, and no lands can be connected to a voltage bias. functional operation, refer to the processor case temperature specifications.
- This rating applies to the processor an d does not include any tray or packaging.
- Failure to adhere to this specification can a ffect the long term reliability of the processor.
Table 4. Absolute Maximum and Minimum Ratings
2.6.2 DC Voltage and Cu rrent Specification
- Unless otherwise noted, all specification in this table are based on estimates and
from silicon measurements at a later date.
- Adherence to the voltage specification for th e processor are required to ensure reliable
- Each processor is programmed with a maximum valid voltage identification value (VID),
the processor during a power management event (Thermal Monitor 2).
- These voltages are targets only. A variable vo ltage source should exist on systems in the
- The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE
- Refer to Table 6 and Figure 1 for the minimum, typical, and maximum VCC allowed for a
wherein VCC exceeds VCC_MAX for a given current.
- I CC_MAX specification is based on the VCC_MAX loadline. Refer to Figure 1f or details.
Table 5. Voltage and Current Specifications
2.0 GHz
1.8 GHz
1.6 GHz
4.6 A1 0
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- V TT must be provided via a separate voltage source and not be connected to VCC. This
specification is measured at the land.
- Baseboard bandwidth is limited to 20 MHz.
- This is maximum total current drawn from V TT plane by only the processor. This
based on design characterization and is not tested.
- This is maximum total current drawn from V TT plane by only the processor. This
characterization and is not tested.
- Adherence to the voltage specifications for th e processor are required to ensure reliable
- The loadline specification includes both static and transient limits except for overshoot
allowed as shown in Section 2.6.3.
- This table is intended to aid in reading discrete points on Figure 1.
- The loadlines specify voltage limits at the die measured at the VCC_SENSE and
- Adherence to this loadline specification is re quired to ensure reliable processor operation.
Table 6. V CC Static and Transient Tolerance
- The loadline specification includes both static and transient limits except for overshoot
allowed as shown in Section 2.6.3.
- This loadline specification shows the deviation from the VID set point.
- The loadlines specify voltage limits at the die measured at the VCC_SENSE and
2.6.3 V CC Overshoot
cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage). processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands. Figure 1. V CC Static and Transient Tolerance Table 7. V CC Overshoot Specifications
- Adherence to these specifications is requir ed to ensure reliable processor operation.
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- V OS is measured overshoot voltage.
- T OS is measured time duration above VID.
2.6.4 Die Voltage Validation
2.7 Signaling Specifications
critical than with previous processor families. the bus on the motherboard for most GTL+ signals. Figure 2. V CC Overshoot Example Waveform
2.7.1 FSB Signal Groups
group as well as the GTL+ I/O group when driving. Table 8. FSB Signal Groups (Sheet 1 of 2)
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- Refer to Section 4.2 for signal descriptions.
- In processor systems where no debug port is implemented on the system board, these
implemented on the system board, these signals are no connects.
- The value of these signals during the acti ve-to-inactive edge of RESET# defines the
processor configuration options. See Section 6.1 for details.
- PROCHOT# signal type is open drain output and CMOS input.
- Signals that do not have R
TT, nor are actively driven to their high-voltage level.
- These signals also have hysteresis added to the reference voltage. See Table 12 for more
Table 8. FSB Signal Groups (Sheet 2 of 2) Table 9. Signal Characteristics Table 10. Signal Reference Voltages
2.7.2 CMOS and Open Drain Signals
asserted for at least four BCLKs for the processor to recognize the proper signal state. requirements for entering and leaving the low power states.
2.7.3 Processor DC Specifications
and cache sizes unless otherwise stated.
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- V IL is defined as the voltage range at a receiving agent that will be interpreted as a logical
- V IH is defined as the voltage range at a receiving agent that will be interpreted as a logical
- V IH and VOH may experience excursions above VTT. However, input signal drivers must
comply with the signal quality specifications.
- The V TT referred to in these specifications is the instantaneous VTT.
- Leakage to V SS with land held at VTT.
- Leakage to V TT with land held at 300 mV.
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- For Vin between 0 and V OH
Table 11. GTL+ Signal Group DC Specifications Table 12. Open Drain and TAP Output Signal Group DC Specifications
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- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- V IL is defined as the voltage range at a receiving agent that will be interpreted as a logical
- The V TT referred to in these specifications refers to instantaneous VTT.
- V IH is defined as the voltage range at a receiving agent that will be interpreted as a logical
- V IH and VOH may experience excursions above VTT. .
- All outputs are open drain.
- Leakage to V SS with land held at VTT.
- Leakage to V TT with land held at 300 mV
Table 13. CMOS Signal Group DC Specifications
2.7.3.1 GTL+ Front Side Bus Specifications
generated on the system board using high precision voltage divider circuits.
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- GTLREF is to be generated from V TT by a voltage divider of 1% resistors (one divider for
- R TT is the on-die termination resistance measured at VTT/3 of the GTL+ output driver.
- COMP resistance must be provided on the sy stem board with 1% resistors. COMP[3:0] and
Table 14. GTL+ Bus Voltage Definitions
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2.8 Clock Specifications
2.8.1 Front Side Bus Clock (BCL K[1:0]) and Processor Clocking
Clock Synthhesizer/Driver should comply with the specifications in Section 2.8.4.
- Individual processors operate only at or below the rated frequency.
- Listed frequencies are not necessar ily committed production frequencies.
Table 15. Core Frequency to FSB Multiplier Configuration
2.8.2 FSB Frequency Select Signals (BSEL[2:0])
2.8.3 Phase Lock Loop (PLL) and Filter
used for the PLL. Refer to Table 5 for DC specifications. Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]
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2.8.4 BCLK[1:0] Specificatio ns (CK505 based Platforms)
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- Crossing voltage is defined as the instantaneous voltage value when the rising edge of
BCLK0 equals the falling edge of BCLK1.
- V Havg is the statistical average of the VH measured by the oscilloscope.
- "Steady state" voltage, not including overshoot or undershoot.
- Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined
as the absolute value of the minimum voltage.
- Measurement taken from differential waveform.
- The crossing point must meet the absolute and relative crossing point specifications
- Cpad includes die capacitance only. No package parasitics are included.
Table 17. Front Side Bus Diffe rential BCLK Specifications Figure 3. Differential Clock Waveform
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2.8.5 BCLK[1:0] Specificatio ns (CK410 based Platforms)
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- Crossing voltage is defined as the instantaneous voltage value when the rising edge of
BCLK0 equals the falling edge of BCLK1.
- V Havg is the statistical average of the VH measured by the oscilloscope.
- Overshoot is defined as the absolu te value of the maximum voltage.
- Undershoot is defined as the absolute value of the minimum voltage.
- Ringback Margin is defined as the abso lute voltage difference between the maximum
Rising Edge Ringback and the maximum Falling Edge Ringback.
- Threshold Region is defined as a region entered around the crossing point voltage in which
the differential receiver switches. It includes input threshold hysteresis.
- The crossing point must meet the absolute and relative crossing point specifications
- V Havg can be measured directly using “Vtop” on Agilent* oscilloscopes and “High” on
Table 18. Front Side Bus Diffe rential BCLK Specifications
0 N/A V 3 -
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2.9 PECI DC Specifications
- V TT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications.
- The leakage specification applies to powered devices on the PECI bus.
- The input buffers use a Schm itt-triggered input design for improved noise immunity.
- One node is counted for each client and on e node for the system host. Extended trace
lengths might appear as additional nodes. Table 19. PECI DC Electrical Limits
3 Package Mechanical
LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket.
- Integrated Heat Spreader (IHS)
- Thermal Interface Material (TIM)
- Processor core (die)
- Package substrate
- Capacitors NOTE: 1. Socket and motherboard are included for refe rence and are not part of processor package.
3.1 Package Mechanical Drawing
- Package reference with tolerances (total height, length, width, etc.)
- IHS parallelism and tilt
- Land dimensions
- Top-side and back-side component keep-out dimensions
- Reference datums
- All drawing dimensions are in mm [in].
- Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and Mechanical Design Guidelines.
Figure 8. Processor Package Assembly Sketch
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Figure 9. Processor Package Drawing Sheet 1 of 3
Figure 10. Processor Package Drawing Sheet 2 of 3
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Figure 11. Processor Package Drawing Sheet 3 of 3
3.2 Processor Component Keep-Out Zones
manufacturing efficiencies but will remain within the component keep-in.
3.3 Package Loading Specifications
Table 20 provides dynamic and static load specifications for the processor package. maintained by any thermal and mechanical solutions.
- These specifications apply to uniform compre ssive loading in a direction normal to the
- This is the maximum force that can be applie d by a heatsink retention clip. The clip must
also provide the minimum specified load on the processor package.
- These specifications are based on limited test ing for design characterization. Loading limits
are for the package only and do not include the limits of the processor socket.
- Dynamic loading is defined as an 11 ms dura tion average load superimposed on the static
3.4 Package Handling Guidelines
handling loads may be experienced during heatsink removal.
- A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top
- A tensile load is defined as a pulling load a pplied to the IHS in a direction normal to the
- A torque load is defined as a twisting load a pplied to the IHS in an axis of rotation normal
- These guidelines are based on limite d testing for design characterization.
Table 20. Processor Lo ading Specifications Table 21. Package Handling Guidelines
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3.5 Package Insertion Specifications
3.6 Processor Mass Specification
the components that are included in the package.
3.7 Processor Materials
Table 22 lists some of the package components and associated materials.
3.8 Processor Markings
identification of the processor. Table 22. Processor Materials Figure 12. Processor Top-Side Marking Example
3.9 Processor Land Coordinates
referred to throughout the document to identify processor lands. Figure 13. Processor La nd Coordinates and Quadrants, Top View
Package Mechanical Specifications
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Land Listing and Signal Descriptions
4 Land Listing and Signal
This chapter provides the processor land assignment and signal descriptions.
4.1 Processor Land Assignments
This section contains the land listings for the processor. The land-out footprint is shown in Figure 14 and Figure 15. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view). Table 23 is a listing of all processor lands ordered alphabetically by land (signal) name. Table 24 is also a listing of all processor lands; the ordering is by land number.
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Figure 14. land-out Diagram (Top View – Left Side)
6 RESET# D47# D44# DSTBN2# DSTBP2# D35# D36# D32# D31#
7 RSVD VSS D43# D41# VSS D38# D37# VSS D30#
Figure 15. land-out Diagram (Top View – Right Side)
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Table 23. Alphabetical Land
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Table 24. Numerical Land
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4.2 Alphabetical Signals Reference
Table 25. Signal Description ( (Sheet 1 of 9)) configuration. See Section 6.1 for more details. Output Write bus transaction. operations associated with the new transaction. drive their outputs and latch their inputs. current bus owner cannot issue any new transactions.
appropriate pins/lands of all processor FSB agents. for termination requirements. completed, then releases the bus by de-asserting BPRI#. signal is sampled to determine the agent ID = 0. including termination recommendations refer to Section 2.8.2. board using precision resistors. Table 25. Signal Description ( (Sheet 2 of 9))
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DRDY# to indicate a valid data transfer. data signals correspond to a pair of one DSTBP# and one DSTBN#. group is inverted and therefore sampled active high. signals for that particular sub-phase for that 16-bit group. connect in the system. DBR# is not a processor signal. Table 25. Signal Description ( (Sheet 3 of 9))
clock data transfer, DRDY# may be de-asserted to insert idle clocks. DSTBN[3:0]# are the data strobes used to latch in D[63:0]#. DSTBP[3:0]# are the data strobes used to latch in D[63:0]#. indicates that the processor should be returned to the Normal state. and the CPUID Instruction application note. signal is a logical 0 or logical 1. Table 25. Signal Description ( (Sheet 4 of 9))
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be continued by reasserting HIT# and HITM# together. for termination requirements. effect when the NE bit in control register 0 (CR0) is set. Output Write bus transaction. appropriate pins/lands of all processor FSB agents. systems where no debug port is implemented on the system board. Pentium processor. Both signals are asynchronous. Table 25. Signal Description ( (Sheet 5 of 9))
end of the last transaction. the processor FSB, it will wait until it observes LOCK# de-asserted. system de-asserts PROCHOT#. See Section 5.2.4 for more details. before a subsequent rising edge of PWRGOOD. should be driven high throughout boundary scan operation. signals are source synchronous to ADSTB0#. asserted for more than 10 ms while PWRGOOD is asserted. configuration options are described in the Section 6.1. terminated on the system board. Table 25. Signal Description ( (Sheet 6 of 9))
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if the processor is present. processor begins program execution from the SMM handler. processor will tri-state its outputs. signals to all processor core units except the FSB and APIC units. STPCLK# is an asynchronous input. (also known as the Test Access Port). provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. Section 2.4 for more details. Table 25. Signal Description ( (Sheet 7 of 9))
(provided VTT and VCC are valid). must connect the appropriate pins/lands of all FSB agents. must be driven low during power on Reset. these pins is determined by the VID[6:0] pins. VCCPLL Input VCCPLL provides isolated po wer for internal processor FSB PLLs. the silicon with little noise. 11 Design Guide For Desktop and Transportable LGA775 Socket. LGA775 Socket for more information. Table 25. Signal Description ( (Sheet 8 of 9))
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VSSA Input VSSA is the isolated ground for internal PLLs. 11 Design Guide For Desktop and Transportable LGA775 Socket. VTT Miscellaneous voltage supply. Table 25. Signal Description ( (Sheet 9 of 9))
Thermal Specifications and Design Considerations
5 Thermal Specifications and
5.1 Processor Thermal Specifications
The processor requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of system fans combined with ducting and venting. For more information on designing a component level thermal solution, refer to the Intel® Celeron® Processor 400 Series Thermal and Mechanical Design Guidelines. Note: The boxed processor will ship with a component thermal solution. Refer to Chapter 7 for details on the boxed processor.
5.1.1 Thermal Specifications
To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (T specifications when operating at or below the Thermal Design Power (TDP) value listed per frequency in Table . Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, refer to the Intel® Celeron® Processor 400 Series Thermal and Mechanical Design Guidelines. The processor uses a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control. Selection of the appropriate fan speed is based on the relative temperature data reported by the processor’s Platform Environment Control Interface (PECI) bus as described in Section 5.4.1.1. The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT# (see Section 5.2). Systems that implement fan speed control must be designed to take these conditions in to account. Systems that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications. To determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions. Refer to the Intel ® Celeron® Processor 400 Series Thermal and Mechanical Design Guidelines for the details of this methodology. The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that
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remain within specification. Table 26. Processor Thermal Specifications
- Specification is at 35 °C T C and typical voltage loadline.
- 775_VR_CONFIG_06 guidelines provide a design targ et for meeting future thermal requirements.
- Thermal Design Power (TDP) should be used for processor ther mal solution design targets. The TDP is not the maximum power
that the processor can dissipate.
- This table shows the maximum TDP for a given frequency range. Individual processors may have a lower TDP. Therefore, the
the allowed combinations of power and TC.
Table 27. Thermal Profile Figure 16. Thermal Profile
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5.1.2 Thermal Metrology
Table 26. This temperature specification is meant to help ensure proper operation of
5.2 Processor Thermal Features
5.2.1 Thermal Monitor
Figure 17. Case Temperature (T
Thermal Specifications and Design Considerations periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the Intel® Celeron® Processor 400 Series Thermal and Mechanical Design Guidelines for information on designing a thermal solution. The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and cannot be modified. The Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines.
5.2.2 Thermal Monitor 2
The processor also supports an additional power reduction capability known as Thermal Monitor 2. This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor. When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust its operating frequency (via the bus multiplier) and input voltage (via the VID signals). This combination of reduced frequency and VID results in a reduction to the processor power consumption. A processor enabled for Thermal Monitor 2 includes two operating points, each consisting of a specific operating frequency and voltage. The first operating point represents the normal operating condition for the processor. Under this condition, the core-frequency-to-FSB multiple used by the processor is that contained in the CLK_GEYSIII_STAT MSR and the VID is that specified in Table 2. These parameters represent normal system operation. The second operating point consists of both a lower operating frequency and voltage. When the TCC is activated, the processor automatically transitions to the new frequency. This transition occurs very rapidly (on the order of 5 μs). During the frequency transition, the processor is unable to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency. Once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator. The voltage regulator must support dynamic VID steps in order to support Thermal Monitor 2. During the voltage change, it will be necessary to transition through multiple VID codes to reach the target operating voltage. Each step will likely be one VID table entry (see Table 2). The processor continues to execute instructions during the voltage transition. Operation at the lower voltage reduces the power consumption of the processor. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the operating frequency and voltage transition back to the normal system operating point. Transition of the VID code will occur first, in order to insure proper operation once the processor reaches its normal operating frequency. Refer to Figure 18 for an illustration of this ordering.
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regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled.
5.2.3 On-Demand Mode
TCC will override the duty cycle selected by the On-Demand mode. Figure 18. Thermal Monitor 2 Frequency and Voltage Ordering
Thermal Specifications and Design Considerations
5.2.4 PROCHOT# Signal
An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or de- assertion of PROCHOT#. As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled, for both cores. The TCC will remain active until the system de-asserts PROCHOT#. PROCHOT# allows for some protection of various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor (either core) has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components. PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power. With a properly designed and characterized thermal solution, it is anticipated that PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. Refer to the Voltage Regulator-Down (VRD) 11 Design Guide For Desktop and Transportable LGA775 Socket for details on implementing the bi-directional PROCHOT# feature.
5.2.5 THERMTRIP# Signal
Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 25). At this point, the FSB signal THERMTRIP# will go active and stay active as described in Table 25. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles.
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5.3 Thermal Diode
The value of TCONTROL may vary from 00h to 1Eh (0 to 30 °C). TCONTROL (or lower) as measured by the thermal diode.
- Intel does not support or re commend operation of the thermal diode under reverse bias.
- Preliminary data. Will be characterized across a temperature range of 50–80 °C.
- Not 100% tested. Specified by design characterization.
- The ideality factor, n, represents the deviat ion from ideal diode behavior as exemplified by
k = Boltzmann Constant, and T = absolute temperature (Kelvin).
- The series resistance, R T, is provided to allow for a more accurate measurement of the
Constant, q = electronic charge. Table 28. Thermal “Diode” Pa rameters using Diode Model
Thermal Specifications and Design Considerations NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Same as I FW in Table 28. 3. Preliminary data. Will be characterize d across a temperature range of 50–80 °C. 4. Not 100% tested. Specified by design characterization. 5. The ideality factor, nQ, represents the devi ation from ideal transistor model behavior as exemplified by the equation for the collector current: IC = IS * (e qVBE/nQkT –1) Where IS = saturation current, q = electronic charge, VBE = voltage across the transistor base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute temperature (Kelvin). 6. The series resistance, R T, provided in the Diode Model Table (Table 28) can be used for more accurate readings as needed. The Intel® Celeron® processor 400 Series does not support the diode correction offset that exists on other Intel processors. Table 29. Thermal “Diode” Parame ters using Transistor Model Table 30. Thermal Diode Interface
Description
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5.4 Platform Environment Control Interface (PECI)
5.4.1 Introduction
5.4.1.1 Key Difference with Legacy Diode-Based Thermal Management
fan control diagram using PECI temperatures. Figure 19. Processor PECI Topology
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5.4.2 PECI Specifications
5.4.2.1 PECI Device Address
refer to the Platform Environment Control Interface Specification.
5.4.2.2 PECI Command Support
5.4.2.3 PECI Fault Handling Requirements
however, certain scenarios where the PECI is know to be unresponsive. data is not available via PECI. event of a critical or continuous fault condition.
5.4.2.4 PECI GetTemp0() Error Code Support
Table 31. GetTemp0() Error Codes
Features
6 Features
6.1 Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 32. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor; for reset purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset. Frequency determination functionality will exist on engineering sample processors which means that samples can run at varied frequencies. Production material will have the bus to core ratio locked and can only be operated at the rated frequency. NOTE: 1. Asserting this signal du ring RESET# will select the corresponding option. 2. Address signals not identified in this table as configuration options should not be asserted during RESET#.
6.2 Clock Control and Low Power States
The processor allows the use of AutoHALT and Stop-Grant states which may reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 22 for a visual representation of the processor low power states. Table 32. Power-On Configuration Option Signals
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6.2.1 Normal State
This is the normal operating state for the processor.
6.2.2 HALT and Extended HALT Powerdown States
The processor supports the HALT or Extended HALT powerdown state. The Extended HALT Powerdown must be enabled via the BIOS for the processor to remain within its specification. The Extended HALT state is a lower power state as compared to the Stop Grant State. If Extended HALT is not enabled, the default Powerdown state entered will be HALT. Refer to the sections below for details about the HALT and Extended HALT states.
6.2.2.1 HALT Powerdown State
HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions. When one of the processor cores executes the HALT instruction, that processor core is halted, however, the other processor continues normal operation. The processor will transition to the Normal state upon the occurrence of SMI#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. Figure 22. Processor Low Power State Machine
The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT Power Down state, the processor will process bus snoops.
6.2.2.2 Extended HALT Powerdown State
Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS. When one of the processor cores executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation. The Extended HALT Powerdown must be enabled via the BIOS for the processor to remain within its specification. The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended HALT state. Note that the processor FSB frequency is not altered; only the internal core frequency is changed. When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower VID. While in Extended HALT state, the processor will process bus snoops. The processor exits the Extended HALT state when a break event occurs. When the processor exits the Extended HALT state, it will first transition the VID to the original value and then change the bus ratio back to the original value.
6.2.3 Stop Grant State
When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Since the GTL+ signals receive power from the FSB, these signals should not be driven (allowing the level to return to V TT) for minimum power drawn by the termination resistors in this state. In addition, all other input signals on the FSB should be driven to the inactive state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the de- assertion of the STPCLK# signal. A transition to the Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section 6.2.4). While in the Stop-Grant State, SMI#, INIT#, and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process a FSB snoop.
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6.2.4 HALT Snoop State and Stop Grant Snoop State
The processor will respond to snoop transactions on the FSB while in Stop-Grant state or in HALT Power Down state. During a snoop transaction, the processor enters the HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB). After the snoop is serviced, the processor will return to the Stop Grant state or HALT Power Down state, as appropriate.
7 Boxed Processor Specifications
mechanical representation of a boxed processor. Mechanical Design Guidelines for further guidance. NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Figure 23. Mechanical Represen tation of the Boxed Processor
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7.1 Mechanical Specifications
7.1.1 Boxed Processor Cooling Solution Dimensions
mechanical representation of the boxed processor. assembled fan heatsink are shown in Figure 24 (Side View), and Figure 25 (Top View). (marked with alphabetic designations) to clarify relative dimensioning. Figure 24. Space Requir ements for the Boxed Processor (Side View)
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7.1.2 Boxed Processor Fan Heatsink Weight
Guidelines for details on the processor weight and heatsink requirements.
7.1.3 Boxed Processor Retention Mechanism and Heatsink
will ship with the heatsink attach clip assembly.
7.2 Electrical Requirements
7.2.1 Fan Heatsink Power Supply
contains specifications for the input and output signals at the fan heatsink connector.
- Pin 1: Ground; black wire.
- Pin 2: Power, +12 V; yellow wire.
- Pin 3: Signal, Open collector tachometer output signal requirement: 2 pulses per
Figure 27. Boxed Processor Fan Heatsi nk Power Cable Connector Description
7.3 Thermal Specifications
7.3.1 Boxed Processor Cooling Requirements
responsibility of the system integrator. Figure 28. Baseboard Power Header Plac ement Relative to Processor Socket
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Figure 29. Boxed Processor Fan Heatsink Ai rspace Keepout Requirements (Top 1 view) Figure 30. Boxed Processor Fan Heatsink Ai rspace Keepout Requirements (Side 2 View)
7.3.2 Variable Speed Fan
specification (see Chapter 5) is the responsibility of the system integrator. Table 33 for the specific requirements. Figure 31. Boxed Processo r Fan Heatsink Set Points Table 33. Fan Heatsink Powe r and Signal Specifications this set point, the fan operates at its lowest speed. nominal operating environment.
- Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink.
fan operates between its lowest and highest speeds. worst-case operating environment.
Boxed Processor Specifications
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§ §
Debug Tools Specifications
8 Debug Tools Specifications
8.1 Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of systems, the LAI is critical in providing the ability to probe and capture FSB signals. There are two sets of considerations to keep in mind when designing a r system that can make use of an LAI: mechanical and electrical.
8.1.1 Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI lands plug into the processor socket, while the processor lands plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keepout volume remains unobstructed inside the system. Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor’s heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as part of the LAI.
8.1.2 Electrical Considerations
The LAI will also affect the electrical performance of the FSB; therefore, it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution it provides.
Debug Tools Specifications