315876-002 INTEL | Alldatasheet
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Technical content
Datasheet sections
- 1.0 Introduction
- 1.1 Terminology
- 1.2 References
- 1.3 State of Data
- 2.0 Low Power Features
- 2.1 Clock Control and Low Power States
- 2.2 Enhanced Intel
- 2.3 Extended Halt State (C1E)
- 3.0 Electrical Specifications
- 3.1 Front Side Bus and GTLREF
- 3.2 Power and Ground Pins
- 3.3 Decoupling Guidelines
- 3.4 Voltage Identification and Power Sequencing
- 3.5 Catastrophic Thermal Protection
- 3.6 Signal Terminations and Unused Pins
- 3.7 FSB Frequency Select Signals (BSEL[2:0])
- 3.8 FSB Signal Groups
- 3.9 CMOS Signals
- 3.10 Maximum Ratings
- 3.11 Processor DC Specifications
- 4.0 Package Mechanical Specifications and Pin Information
- 4.1 Package Mechanical Specifications
- 4.2 Processor Pin-Out and Pin List
- 5.0 Thermal Specifications and Design Considerations
- 5.1 Thermal Specifications
- 1 Package-Level Low Power States
- 2 Core Low Power States
- 3 Active VCC and ICC Load Line for Intel
- 4 Micro-FCPGA Package Top and Bottom Views
- 5 Micro-FCPGA Processor Package Drawing (Sheet 1)
- 6 Micro-FCPGA Processor Package Drawing (Sheet 2)
- 7 The Coordinates of the Processor Pins as Viewed From the Top of the Package
- 1 Terminology
- 2 References
- 4 BSEL[2:0] Encoding for BCLK Frequency
- 5 FSB Pin Groups
- 6 Processor DC Absolute Maximum Ratings
- 7 Voltage and Current Specifications for the Intel
- 8 AGTL+ Signal Group DC Specifications
- 9 CMOS Signal Group DC Specifications
- 10 Open Drain Signal Group DC Specifications
- 11 Signal Description
Order Number: 315876-002 Intel® Celeron® Processor 1.66 GHz/
1.83 GHz
Intel® Celeron® Processor 1.66 GHz/1.83 GHz— Intel® Celeron® Processor 1.66 GHz/1.83 GHz DS January 2007
2 Order Number: 315876-002
Leg al Lines and Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT . Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. The Intel ® Celeron® Processor 1.66 GHz/1.83 GHz may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Hyper-Threading Technology requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a HT Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See http://www.intel.com/ products/ht/Hyperthreading_more.htm for additional information. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. BunnyPeople, Celeron, Celeron Inside, Centrino, Centrino logo, Core Inside, Dialogic, FlashFile, i960, InstantIP , Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Core, Intel Inside, Intel Inside logo, Intel. Leap ahead., Intel. Leap ahead. logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel Viiv, Intel vPro, Intel XScale, IPLink, Itanium, Itanium Inside, MCS, MMX, Oplus, OverDrive, PDCharm, Pentium, Pentium Inside, skoool, Sound Mark, The Journey Inside, VTune, Xeon, and Xeon Inside are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007, Intel Corporation. All Rights Reserved.
Intel® Celeron® Processor 1.66 GHz/1.83 GHz—Contents Intel® Celeron® Processor 1.66 GHz/1.83 GHz DS January 2007
4 Order Number: 315876-002
16 Power Specifications for the Intel
19 Thermal “Diode” n
Intel® Celeron® Processor 1.66 GHz/1.83 GHz January 2007 DS Order Number: 315876-002 5 Revision History—Intel ® Celeron® Processor 1.66 GHz/1.83 GHz
Revision History
November 2006 001 Initial public release. January 2007 002 Added information for Intel ® Celeron® Processor 1.83 GHz
Intel® Celeron® Processor 1.66 GHz/1.83 GHz—Introduction Intel® Celeron® Processor 1.66 GHz/1.83 GHz DS January 2007
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1.0 Introduction
The Intel® Celeron® Processor 1.66 GHz/1.83 GHz is a single-core, low-power processor designed for embedded, communications infrastructure and storage applications. The processor is manufactured on Intel’s advanced 65 nanometer process technology with copper interconnect. The following list provides some of the key features on this processor:
- S i n g l e c o r e
- Uniprocessor support only
- 36-bit physical addressing
- Address, Data, and Response Parity on the Front Side Bus (FSB)
- Supports Intel Architecture with Dynamic Execution
- On-die, 32 kB Level 1 instruction cache and 32 kB write-back data cache
- On-die, 1 MB, ECC protected, Level 2 cache with Advanced Transfer Cache Architecture
- Data Prefetch Logic
- Streaming SIMD Extensions 2 (SSE2) and Streaming Single Instruction Multiple Data (SIMD) Extensions 3 (SSE3)
- 667 MT/s (megatransfers/second), Source-Synchronous FSB
- Digital Thermal Sensor (DTS)
- Intel Thermal Monitor 1 (TM1) and Thermal Monitor 2 (TM2)
- Micro-FCPGA packaging technologies
- Execute Disable Bit support for enhanced security The Intel® Celeron® Processor 1.66 GHz/1.83 GHz maintains support for MMX TM Technology and Streaming SIMD instructions and full compatibility with IA32 software. The on-die, 32 kB Level 1 instruction and data caches and the 1 MB Level 2 cache with Advanced Transfer Cache Architecture enable performance improvement over existing low power processors. The processor’s Data Prefetch Logic speculatively fetches data to the L2 cache before an L1 cache request occurs, resulting in reduced bus cycle penalties and improved performance. The Intel ® Celeron® Processor 1.66 GHz/1.83 GHz includes the Data Cache Unit Streamer, which enhances the performance of the L2 prefetcher by requesting L1 warm-ups earlier. In addition, Write Order Buffer depth is enhanced to help with write-back latency performance. In addition to supporting all the existing Streaming SIMD Extensions 2 (SSE2), there are 13 new instructions, which further extend the capabilities of Intel processor technology. These new instructions are called Streaming SIMD Extensions 3 (SSE3). These new instructions enhance the performance of optimized applications such as video, image processing and media compression technology. 3D graphics and other video intense applications have the opportunity to take advantage of these new instructions as platforms with the Intel ® Celeron® Processor 1.66 GHz/1.83 GHz and SSE3 become available.
technology with low power enhancements. The processor also features the Auto Halt low power state (Extended Halt State - C1E). Developer's Manuals for more detailed information.
1.1 Terminology
Table 1. Terminology (Sheet 1 of 2) D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level). XXXX means that the specification or value is yet to be determined. as interrupt messages pass between the processor and chipset over the FSB. respect to the buffer reference voltage. only observable in simulations.
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1.2 References
other transmission line phenomena. Undershoot The minimum voltage extending below VSS observed for a signal at the device pad. current to a single processor. Table 1. Terminology (Sheet 2 of 2) Table 2. References
- Order numbers are subject to change
Intel® Celeron® Processor 1.66 GHz/1.83 GHz January 2007 DS Order Number: 315876-002 9 Introduction—Intel ® Celeron® Processor 1.66 GHz/1.83 GHz
1.3 State of Data
The data contained within this document represents the most accurate information available by the publication date. Note: All references to the Intel® Celeron® Processor 1.66 GHz/1.83 GHz in this document apply to the Intel® Celeron® Processor 1.66 GHz/1.83 GHz only, unless otherwise specified.
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2.0 Low Power Features
2.1 Clock Control and Low Power States
Celeron® Processor 1.66 GHz/1.83 GHz. Figure 1. Package-Level Low Power States
2.1.1 Core Low Power States
2.1.1.1 C0 State - Normal State
This is the normal operating state for the processor .
2.1.1.2 C1/AutoHALT Powerdown State
BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the system bus. RESET# causes the processor to immediately initialize itself. execution to the HALT state. Figure 2. Core Low Power States
Intel® Celeron® Processor 1.66 GHz/1.83 GHz—Low Power Features Intel® Celeron® Processor 1.66 GHz/1.83 GHz DS January 2007
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2.1.1.3 C1/MWAIT Powerdown State
MWAIT is a low power state entered when the processor core executes the MWAIT instruction. Processor behavior in the MWAIT state is identical to the AutoHALT state except that there is an additional event that can cause the processor core to return to the C0 state: the Monitor event. Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals in Volume 3A/3B: System Programming Guide for more information.
2.1.2 Package Low Power States
The following sections describe all package level low power states for the Intel ® Celeron® Processor 1.66 GHz/1.83 GHz.
2.1.2.1 Normal State
This is the normal operating state for the processor. Intel ® Celeron® Processor 1.66 GHz/1.83 GHz enters the Normal state when its core is in the Normal, AutoHALT, or MWAIT state.
2.1.2.2 Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Once the STPCLK# pin has been asserted, the Intel ® Celeron® Processor 1.66 GHz/1.83 GHz, the processor core must be in the Stop Grant state before the deassertion of STPCLK#. Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to V CCP) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the system bus should be driven to the inactive state. BINIT# is not serviced while the processor is in Stop-Grant state. The event is latched and can be serviced by software upon exit from the Stop Grant state. RESET# causes the processor to immediately initialize itself, but the processor stays in Stop-Grant state. A transition back to the Normal state occurs with the de-assertion of the STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should only be deasserted one or more bus clocks after the deassertion of SLP#. A transition to the HALT/Grant Snoop state occurs when the processor detects a snoop on the system bus A transition to the Sleep state occurs with the assertion of the SLP# signal. While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] is latched by the processor, and only serviced when the processor returns to the Normal state. Only one occurrence of each event is recognized upon return to the Normal state. While in Stop-Grant state, the processor processes snoops on the system bus and it latches interrupts delivered on the system bus. The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# is asserted if there is any pending interrupt latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear still causes assertion of PBE#. Assertion of PBE# indicates to system logic that it should return the processor to the Normal state.
Intel® Celeron® Processor 1.66 GHz/1.83 GHz January 2007 DS Order Number: 315876-002 13 Low Power Features—Intel ® Celeron® Processor 1.66 GHz/1.83 GHz
2.1.2.3 Stop Grant Snoop State
The processor responds to snoop or interrupt transactions on the FSB while in Stop- Grant state. During a snoop or interrupt transaction, the processor enters the Stop Grant Snoop state. The processor stays in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. After the snoop is serviced or the interrupt is latched, the processor returns to the Stop-Grant state.
2.1.2.4 Sleep State
The Sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped most of internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the processor enters the Sleep state upon the assertion of the SLP# signal. The SLP# pin has a minimum assertion of one BCLK period. The SLP# pin should only be asserted when the processor is in the Stop Grant state. For the Intel ® Celeron® Processor 1.66 GHz/1.83 GHz, the SLP# pin may only be asserted the processor core is in the Stop- Grant state. SLP# assertions while the processor is not in the Stop-Grant state are out of specification and may results in illegal operation. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state causes unpredictable behavior. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#) are allowed on the system bus while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state results in unpredictable behavior . If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor resets itself, ignoring the transition through Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the reset sequence. When the processor is in Sleep state, it does not respond to interrupts or snoop transactions.
2.2 Enhanced Intel ® SpeedStep® Technology (EIST)
Intel® Celeron® Processor 1.66 GHz/1.83 GHz does not support this feature.
2.3 Extended Halt State (C1E)
The Intel® Celeron® Processor 1.66 GHz/1.83 GHz Extended Halt State (C1E) enables significant power savings. Extended HALT state is a low power state entered when the processor core has executed the HALT or MWAIT instructions and Extended HALT state has been enabled via the BIOS. When the processor core executes the HALT instruction, the core is halted. The Extended HALT state is a lower power state than the HALT state or Stop Grant state. Note: The Extended HALT (C1E) state must be enabled for the processor to remain within its specifications. The Extended HALT state requires support for dynamic VID transitions in the platform. The processor automatically transitions to a lower core frequency and voltage operating point before entering the Extended HALT state. Note that the processor FSB frequency
Intel® Celeron® Processor 1.66 GHz/1.83 GHz—Low Power Features Intel® Celeron® Processor 1.66 GHz/1.83 GHz DS January 2007
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is not altered; only the internal core frequency is changed. When entering the low power state, the processor first switches to the lower bus to core frequency ratio and then transition to the lower voltage (VID). While in the Extended HALT(C1E) state, the processor processes bus snoops. The processor exits the Extended HALT state when a break event occurs. When the processor exits the Extended HALT state, it first transitions the VID to the original value and then changes the bus to core frequency ratio back to the original value.
Intel® Celeron® Processor 1.66 GHz/1.83 GHz January 2007 DS Order Number: 315876-002 15 Electrical Specifications—Intel ® Celeron® Processor 1.66 GHz/1.83 GHz
3.0 Electrical Specifications
3.1 Front Side Bus and GTLREF
Most Intel® Celeron® Processor 1.66 GHz/1.83 GHz FSB signals use Advanced Gunning Transceiver Logic (AGTL+) signalling technology. This signalling technology provides improved noise margins and reduced ringing through low-voltage swings and controlled edge rates. The termination voltage level for the Intel ® Celeron® Processor 1.66 GHz/ 1.83 GHz AGTL+ signals is V CCP= 1.05 V (nominal). Due to speed improvements to data and address bus, signal integrity and platform design methods have become more critical than with previous processor families. The AGTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board. Termination resistors are provided on the processor silicon and are terminated to its I/O voltage (V CCP). The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the FSB, including trace lengths, is highly recommended when designing a system.
3.2 Power and Ground Pins
For clean, on-chip power distribution, the Intel ® Celeron® Processor 1.66 GHz/1.83 GHz has a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to VCC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce IR drop. The processor VCC pins must be supplied with the voltage determined by the VID (Voltage ID) pins.
3.3 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 7. Failure to do so can result in timing violations or reduced lifetime of the component.
3.3.1 V CC Decoupling
Regulator solutions need to provide bulk capacitance with a low effective series resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low-power states, must be provided by the voltage regulator solution. For more details on decoupling recommendations, please refer to the Embedded Voltage Regulator-Down (EmVRD) 11.0 Design Guidelines for Embedded Implementations Supporting PGA478 .
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3.3.2 FSB AGTL+ Decoupling
provided by the system motherboard for proper AGTL+ bus operation.
3.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking
ratio at manufacturing. The processor uses a differential clocking implementation.
3.4 Voltage Identification and Power Sequencing
Embedded Implementations Supporting PGA478 . VID[5:0]. A ‘1’ in this refers to a high-voltage level and a 0 refers to low-voltage level.
1.83 GHz power supply requirements, please refer to the Embedded Voltage Regulator-
Table 3. Intel
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Table 3. Intel ® Celeron® Processor 1.66 GHz/1.83 GHz VID Map (Sheet 2 of 3)
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3.5 Catastrophic Thermal Protection
3.6 Signal Terminations and Unused Pins
and the location of all RSVD pins. refer to Table 11 for details.
3.7 FSB Frequency Select Signals (BSEL[2:0])
(BCLK[1:0]). The BSEL encoding for BCLK[1:0] is shown in Table 4. Table 3. Intel ® Celeron® Processor 1.66 GHz/1.83 GHz VID Map (Sheet 3 of 3) Table 4. BSEL[2:0] Encoding for BCLK Frequency
3.8 FSB Signal Groups
Table 5. FSB Pin Groups
- Refer to Chapter 4.0 for signal descriptions and termination requirements.
- BPM[2:1]# and PRDY# are AGTL+ output only signals.
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3.9 CMOS Signals
3.10 Maximum Ratings
should always take precautions to avoid high static voltages of electric fields.
3.11 Processor DC Specifications
listed in Table 8. DC specifications for the CMOS group are listed in Table 9. should be taken to read all notes associated with each parameter. SpeedStep® Technology (EIST), therefore HFM and LFM transitions are not supported. Table 6. Processor DC Absolute Maximum Ratings
- For functional operation, all processor electrical, signal quality, mechanical and thermal specifications
- Excessive overshoot or undershoot on any signal will likely result in permanent damage to the
- Storage temperature is applicable to storage conditions only. In this scenario, the processor must not
case temperature specifications.
Table 7. Voltage and Current Specifications for the Intel ® Celeron® Processor 1.66
36 A 5
2.5 A1 0
- These are VID values. Individual processor VID values may be calibrated during manufacturing such
processor during a power management event (Thermal Monitor 2 or Extended Halt State).
- The voltage specifications are assumed to be measured across V
external noise from the system is not coupled in the scope probe.
- Specified at the VID voltage.
- The I CCDES(max) specification comprehends only Intel® Celeron® Processor 1.66 GHz/1.83 GHz HFM
frequencies. Platforms should be designed to this specification.
- Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
- Refer to Figure 3 for a waveform illustration of this parameter.
- Measured at the bulk capacitors on the motherboard.
- V CC, boot tolerance is shown in Figure 3.
- I CCP specification refers to the processor package on the front side bus.
- Specified at the nominal voltage based on the loadline slope.
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Figure 3. Active V CC and ICC Load Line for Intel® Celeron® Processor 1.66 GHz/1.83 GHz Table 8. AGTL+ Signal Group DC Specifications (Sheet 1 of 2)
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- V IH is defined as the minimum voltage level at a receiving agent that is interpreted as a logical high
- V IH and VOH may experience excursions above VCCP. However, input signal drivers must comply with
the signal quality specifications.
- This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics.
- GTLREF should be generated from V CCP with a 1% tolerance resistor divider. The VCCP referred to in
these specifications is the instantaneous VCCP.
- R TT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at
- Specified with on die R TT and RON are turned off.
- Cpad includes die capacitance only. No package parasitics are included.
Differential Remote Sense required.
Table 9. CMOS Signal Group DC Specifications
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- The V CCP referred to in these specifications refers to instantaneous VCCP.
- Refer to the processor I/O Buffer Models for I/V characteristics.
- For Vin between 0V and V CCP. Measured when the driver is tristated.
- Cpad1 includes die capacitance only for PWRGOOD. No package parasitics are included.
- Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included.
Table 8. AGTL+ Signal Group DC Specifications (Sheet 2 of 2)
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- V IL is defined as the maximum voltage level at a receiving agent that is interpreted as a logical low
- V IH is defined as the minimum voltage level at a receiving agent that is interpreted as a logical high
- V IH and VOH may experience excursions above VCCP. However, input signal drivers must comply with
the signal quality specifications.
- This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics.
- GTLREF should be generated from V CCP with a 1% tolerance resistor divider. The VCCP referred to in
these specifications is the instantaneous VCCP.
- R TT is the on-die termination resistance measured at VOL of the AGTL+ output driver . Measured at
- Specified with on die R TT and RON are turned off.
- Cpad includes die capacitance only. No package parasitics are included.
- R TT for PREQ# is between 1.5kΩ and 6.0kΩ
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Table 10. Open Drain Signal Group DC Specifications
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
OH is determined by value of the external pull-up resistor to VCCP.
- For Vin between 0 V and V OH.
- Cpad includes die capacitance only. No package parasitics are included.
4.0 Package Mechanical Specifications and Pin
4.1 Package Mechanical Specifications
(Micro- Flip Chip PGA) package.
4.1.1 Package Mechanical Drawings
Figure 4. Micro-FCPGA Package Top and Bottom Views
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Note: All dimensions are in millimeters [inches]. Values shown for reference only. Figure 5. Micro-FCPGA Processor Package Drawing (Sheet 1)
Note: All dimensions are in millimeters [inches]. Values shown for reference only.
4.1.2 Processor Component Keep-Out Zones
the component keep-in. Refer to Figure 4, Figure 5, and Figure 6 for keep-out zones. Figure 6. Micro-FCPGA Processor Package Drawing (Sheet 2)
Intel® Celeron® Processor 1.66 GHz/1.83 GHz—Package Mechanical Specifications and Pin Information Intel® Celeron® Processor 1.66 GHz/1.83 GHz DS January 2007
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4.1.3 Package Loading Specifications
Maximum mechanical package loading specifications are given in Figure 5. These specifications are static compressive loading in the direction normal to the processor. This maximum load limit should not be exceeded during shipping conditions, standard use condition, or by thermal solution. In addition, there are additional load limitations against transient bend, shock, and tensile loading. These limitations are more platform specific, and should be obtained by contacting your field support. Moreover, the processor package substrate should not be used as a mechanical reference or load- bearing surface for thermal and mechanical solution.
4.1.4 Processor Mass Specifications
The typical mass of the processor is given in Figure 6. This mass includes all the components that are included in the package.
4.2 Processor Pin-Out and Pin List
Figure 7 shows the top view pinout of the Intel ® Celeron® Processor 1.66 GHz/1.83 GHz. The alphabetical pin listing is shown in Table 14. The alphabetical signal listing is shown in Table 15.
Figure 7. The Coordinates of the Processor Pins as Viewed From the Top of the Package
1 VID
2 VID
3 VID
4 PRE
5 VSS BPM
6 BPM
7 VCC VCC VCC VCC VSS
8 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
9 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
10 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
11 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
12 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
13 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC
14 VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS
15 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
16 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
17 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
18 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
19 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
20 VCC VCC VCC VCC VCCP VCCP VCC VCC BSE
21 VSS VCCP VCCP VSS VCCP D
22 VCCP VCCP VSS VCCP D
23 VCCP VSS D
24 VSS D
25 VCCP RSV
26 VCCP VSS GTL
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4.2.1 Alphabetical Signals Reference
Table 11. Signal Description (Sheet 1 of 7) phase 1 of the address phase, these pins transmit the address of a transaction. used as straps which are sampled before RESET# is deasserted. is only supported in real mode. TRDY# assertion of the corresponding Input/Output Write bus transaction. falling edges. Strobes are associated with signals as shown below. agents must receive these signals to drive their outputs and latch their inputs.
asserted to signal any bus condition that prevents reliable future information. front side bus and attempt completion of their bus queue and IOQ entries. cannot issue any new transactions. performance monitoring tools. releases the bus by deasserting BPRI#. the Memory Controller Hub - MCH (priority agent). BSEL[2:0] (Bus Select) are used to select the processor input clock frequency. MHz system bus frequency (166 MHz BCLK[2:0] frequency respectively). Table 11. Signal Description (Sheet 2 of 7)
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between the FSB agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. data signals to data strobes and DINV#. connect the appropriate pins of all FSB agents. appropriate pins of all processor front side bus agents. more than half the bits, within the covered group, change level in the next cycle. appropriate pins of both FSB agents. Table 11. Signal Description (Sheet 3 of 7) Table 12. Quad-Pumped Signal Groups Table 13. DINV[3:0]# Assignment To Data Bus
Data strobe used to latch in D[63:0]#. Data strobe used to latch in D[63:0]#. CPUID Instruction application note (AP-485) application note. (TCC). The TCC remains active until the system deasserts FORCEPR#. if a signal is a logical 0 or logical 1. until the assertion of RESET#, BINIT#, or INIT#. Table 11. Signal Description (Sheet 4 of 7)
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floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. TRDY# assertion of the corresponding Input/Output Write bus transaction. bus transaction. INIT# must connect the appropriate pins of both FSB agents. ® Pentium® processor. Both signals are asynchronous. transaction to the end of the last transaction. agents. MCERR# assertion conditions are configurable at a system level.
- Enabled or disabled.
- Asserted, if configured, for internal errors along with IERR#.
- Asserted, if configured, by the request initiator of a bus transaction after it observes an error.
- Asserted by any bus agent when it observes an error in a bus transaction. For more details regarding machine check architecture, refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals in Volume 3A/3B: System Programming Guide. Since multiple agents may drive this signal at the same time, MCERR# is a wire- OR signal which must connect the appropriate pins of all processor front side bus agents. In order to avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers, MCERR# is activated on specific clock edges and sampled on specific clock edges. ODTEN Input ODTEN (On-die termination enable) should be connected to V CC to enable on-die termination for end bus agents. Intel® Celeron® Processor 1.66 GHz/1.83 GHz is always the end bus agent because it supports uniprocessor configurations only. Whenever ODTEN is high, on-die termination is active, regardless of other states of the bus. PRDY# Output Probe Ready signal used by debug tools to determine processor debug readiness. PREQ# Input Probe Request signal used by debug tools to request debug operation of the processor.
Table 11. Signal Description (Sheet 5 of 7)
This signal may require voltage translation on the motherboard. and be followed by a 2 ms (minimum) RESET# pulse. throughout boundary scan operation. active transaction type. These signals are source synchronous to ADSTB[0]#. must be valid within the specified setup time before RESET# is deasserted. There is a 55 ohm (nominal) on die pull-up resistor on this signal. appropriate pins of all FSB agents. appropriate pins of all processor front side bus agents. open for possible future use. signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. internal clock signals to the bus and processor core units. Table 11. Signal Description (Sheet 6 of 7)
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serial input needed for JTAG specification support. the serial output needed for JTAG specification support. TEST2 Input TEST2 must have a 51W +/- 5% pull down resistor to V SS. THERMDA Other Thermal Diode Anode. THERMDC Other Thermal Diode Cathode. system by the THERMTRIP# (Thermal Trip) pin. appropriate pins of both FSB agents. driven low during power on Reset. CC Input Processor core power supply. VCCA Input V CCA provides isolated power for the internal processor core PLLs. VCCP Input Processor I/O Power Supply. are CMOS signals driven by the Intel® Celeron® Processor 1.66 GHz/1.83 GHz. be used to sense or measure ground near the silicon with little noise. Table 11. Signal Description (Sheet 7 of 7)
Table 14. Alphabetical Signal Listing (Sheet 1 of 12)
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Table 14. Alphabetical Signal Listing (Sheet 2 of 12)
Table 14. Alphabetical Signal Listing (Sheet 3 of 12)
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Table 14. Alphabetical Signal Listing (Sheet 4 of 12)
Table 14. Alphabetical Signal Listing (Sheet 5 of 12)
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Table 14. Alphabetical Signal Listing (Sheet 6 of 12)
Table 14. Alphabetical Signal Listing (Sheet 7 of 12)
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Table 14. Alphabetical Signal Listing (Sheet 8 of 12)
Table 14. Alphabetical Signal Listing (Sheet 9 of 12)
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Table 14. Alphabetical Signal Listing (Sheet 10 of 12)
Table 14. Alphabetical Signal Listing (Sheet 11 of 12)
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Table 14. Alphabetical Signal Listing (Sheet 12 of 12)
Table 15. Alphabetical Pin Listing (Sheet 1 of 12)
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Table 15. Alphabetical Pin Listing (Sheet 2 of 12)
Table 15. Alphabetical Pin Listing (Sheet 3 of 12)
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Table 15. Alphabetical Pin Listing (Sheet 4 of 12)
Table 15. Alphabetical Pin Listing (Sheet 5 of 12)
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Table 15. Alphabetical Pin Listing (Sheet 6 of 12)
Table 15. Alphabetical Pin Listing (Sheet 7 of 12)
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Table 15. Alphabetical Pin Listing (Sheet 8 of 12)
Table 15. Alphabetical Pin Listing (Sheet 9 of 12)
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Table 15. Alphabetical Pin Listing (Sheet 10 of 12)
Table 15. Alphabetical Pin Listing (Sheet 11 of 12)
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Table 15. Alphabetical Pin Listing (Sheet 12 of 12)
5.0 Thermal Specifications and Design Considerations
damage to the processor and potentially other components in the system. internal ambient temperature within the system. feature must be enabled for the processor to remain within specification. Table 16. Power Specifications for the Intel ® Celeron® Processor 1.66 GHz/1.83 GHz
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5.1 Thermal Specifications
5.1.1 Thermal Diode
thermal diode usage recommendation when the PROCHOT# signal is not asserted. location on the die, and time based variations in the die temperature measurement. Celeron® Processor 1.66 GHz/1.83 GHz Model Specific Register (MSR).
- The TDP specification should be used to design the processor thermal solution.
The TDP is not the maximum theoretical power the processor can generate.
- Not 100% tested. These power specifications are determined by characterization
of the processor currents at higher temperatures and extrapolating to 50 C.
- As measured by the activation of the on-die Intel Thermal Monitor. The Intel
been reached. Refer to Section 5.1 for more details.
- The Intel Thermal Monitor automatic mode must be enabled for the processor to
operate within specifications.
behavior of the Thermal Monitor. Table 17. Thermal Diode Interface Table 18. Thermal “Diode” Parameters using Diode Mode
- Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does
not within their specified tolerance range.
- Characterized across a temperature range of 50 - 100°C.
- Not 100% tested. Specified by design characterization.
- The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode
Constant, and T = absolute temperature (Kelvin).
- The series resistance, R T, is provided to allow for a more accurate measurement of the junction
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5.1.2 Thermal Diode Offset
particular processor is calculated. ntrim as defined in the temperature sensor manufacturers' datasheet. The ntrim used to calculate the Diode Correction Toffset are listed in Table 19.
5.1.3 Intel ® Thermal Monitor
the processor even when the TCC is active continuously. Automatic mode takes precedence. processor to be operating within specifications. internal die temperature reaches the maximum allowed value for operation. also activates to help cool down the processor . ® Celeron® Processor 1.66 GHz/1.83 GHz. Table 19. Thermal “Diode” n trim and Diode Correction Toffset
Intel® Celeron® Processor 1.66 GHz/1.83 GHz January 2007 DS Order Number: 315876-002 65 Thermal Specifications and Design Considerations—Intel ® Celeron® Processor 1.66 GHz/1.83 GHz Likewise, when Intel Thermal Monitor 2 is enabled, and a high temperature situation exists, the processor performs an voltage/frequency transition to a lower operating point. When the processor temperature drops below the critical level, the processor makes an voltage/frequency transition to the last requested operating point. Note: The Intel ® Celeron® Processor 1.66 GHz/1.83 GHz only supports TM2 initiated voltage/ frequency transitions. Intel® Celeron® Processor 1.66 GHz/1.83 GHz does not support Enhanced Intel® SpeedStep® Technology (EIST) therefore it does not support software or MSR based EIST transitions. Likewise, when TM1 is enabled, and a high temperature situation exists, the clocks are modulated by alternately turning the clocks off and on at a 50% duty cycle (automatic mode). Cycle times are processor speed dependent and decreases linearly as processor core frequencies increase. Once the temperature has returned to a non-critical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. Processor performance is decreased by the same amount as the duty cycle when the TCC is active. The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal Monitor control register is written to a 1, the TCC is activated immediately, independent of the processor temperature. When using on-demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be programmed from 12.5% used at the same time automatic mode is enabled, however , if the system tries to enable the TCC via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode takes precedence An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active. Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also includes one ACPI register, one performance counter register, three model specific registers (MSR), one output pin (PROCHOT#), and one input pin (FORCEPR#). All are available to monitor and control the state of the Intel thermal monitor feature. The Intel thermal monitor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Note: PROCHOT# is not asserted when the processor is in the Stop Grant, and Sleep, low power states (internal clocks stopped), hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within maximum specification. If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters a low power state with PROCHOT# already asserted, PROCHOT# remains asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point. If Thermal Monitor automatic mode is disabled, the processor is operating out of specification. Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor automatically shuts down when the silicon has reached a temperature of approximately 125 °C. At this point the THERMTRIP# signal goes active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified in Chapter 3.0.
Intel® Celeron® Processor 1.66 GHz/1.83 GHz—Thermal Specifications and Design Considerations Intel® Celeron® Processor 1.66 GHz/1.83 GHz DS January 2007
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5.1.4 Digital Thermal Sensor
The Intel® Celeron® Processor 1.66 GHz/1.83 GHz also contains an on die digital thermometer that can be read via a MSR (no I/O interface). The digital thermometer shares the thermal sensor of the Intel Thermal Monitor. Intel® Celeron® Processor 1.66 GHz/1.83 GHz has a unique digital thermometer whose temperature is accessible via processor MSR. The digital sensor is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor throttling via the Thermal Monitor. Unlike traditional thermal devices, the Digital Thermometer outputs a temperature relative to the maximum supported operating temperature of the processor (T J,max). It is the responsibility of software to convert the relative temperature to an absolute temperature. The temperature returned by the Digital Thermometer is always at or below T J,max. Over temperature conditions are detectable via an Out Of Spec status bit. This bit is also part of the Digital Thermometer MSR. When this bit is set, the processor is operating out of specification and immediate shutdown of the system should occur. The processor operation and code execution is not guaranteed once the activation of the Out of Spec status bit is set. The Digital Thermal Sensor (DTS) relative temperature readout corresponds to the thermal monitor (TM1/TM2) trigger points. When the DTS indicates maximum processor core temperature has been reached the TM1 or TM2 hardware thermal control mechanism activates. The DTS and TM1/TM2 temperature may not correspond to the thermal diode reading since the thermal diode is located in a separate portion of the die and thermal gradient between the individual core DTS. Additionally, the thermal gradient from DTS to thermal diode can vary substantially due to changes in processor power, mechanical and thermal attach and software application. The system designer is required to use the DTS to guarantee proper operation of the processor within its temperature operating specifications.
5.1.5 Out of Specification Detection
Overheat detection is performed by monitoring the processor temperature and temperature gradient. This feature is intended for graceful shut down before the THERMTRIP# is activated. If the processor’s TM1 or TM2 are triggered and the temperature remains high, an “Out Of Spec” status and sticky bit are latched in the status MSR register and generates thermal interrupt.
5.1.6 PROCHOT# Signal Pin
An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature has reached its maximum operating temperature. If the Intel Thermal Monitor 1 (TM1) or Intel Thermal Monitor 2 (TM2) is enabled (note that the TM1 or TM2 must be enabled for the processor to be operating within specification), the TCC is active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. If the processor die cools down below maximum operating temperature (T jmax) either due to TCC activation or an external event, PROCHOT# automatically de-asserts and the processor resumes normal operation. Refer to the Intel® 64 and IA-32 Architectures Software Developer's Manuals for specific register and programming details.
5.1.7 FORCEPR# Signal Pin
Monitor is enabled, the TCC is activated upon the assertion of the FORCEPR# signal. of the FORCEPR# pin may cause noticeable platform performance degradation.
5.1.8 THERMTRIP# Signal Pin
Table 11. THERMTRIP# activation is independent of processor activity and does not
Intel® Celeron® Processor 1.66 GHz/1.83 GHz—Thermal Specifications and Design Considerations Intel® Celeron® Processor 1.66 GHz/1.83 GHz DS January 2007