82573 INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 Introduction
- 1.1 Document Scope
- 1.2 Reference Documents
- 1.4 Product Codes for the
- 2.0 Signal Descriptions
- 2.1 Signal Type Definitions
- 2.2 PCIe* Data Signals
- 2.3 PCIe* Miscellaneous Signals
- 2.4 Non-Volatile Memory Interface Signals
- 2.5 Miscellaneous Signals
- 2.5.1 Reset and Power-down Signals
- 2.5.2 System Management Bus (SMBus) Signals
- 2.5.3 LED Signals
- 2.5.4 Other Signals
- 2.6 PHY Analog and Crystal Signals
- 2.7 Test Signals
- 2.7.1 MAC Test Signals
- 2.7.2 PHY Test Signals
- 2.7.3 Other Test Signals
- 2.8 Power Signals
- 2.8.1 Power Support Signals
- 2.8.2 Digital and Analog Power Supply Signals
- 2.9 Grounds and No Connects
- 3.0 Voltage, Temperature, and Timing Specifications
- 3.1 Absolute Maximum Ratings
- 3.2 Recommended Operating Conditions
- 3.3 Power Supply Connections
- 3.3.1 External LVR Power Delivery
- 3.3.2 Power Sequencing with External Regulators
- 3.3.3 Internally Generated Power Delivery
- 3.3.4 Internal LVR Power Sequencing
- 3.4 DC and AC Specifications
- 3.5 External Interfaces
- 3.5.1 Crystal
- 3.5.2 External Clock Oscillator
- 3.5.3 Non-Volatile Memory (NVM) Interface: EEPROM
- 4.0 Package and Pinout Information
- 4.1 Package Information
- 4.2 Thermal Specifications
- 4.3 Pinout Information
- 4.3.1 PCIe Bus Interface Signals
- 4.3.2 Non-Volatile Memory Interface Signals
- 4.3.3 Miscellaneous Signals
- 4.3.4 PHY Signals
- 4.3.5 Test Signals
- 4.3.6 Power Supply Signals
- 4.4 Visual Pin Assignments
Order Number: 315514-002 Revision 2.5
82573 Family of GbE Controllers
PCIe* — x1 PCIe* interface on ICH7 or MCH devices — Peak bandwidth: 2 Gb/s per direction — Power management — High bandwidth density per pin MAC — Optimized transmit and receive queues — IEEE 802.3x compliant flow control with software controlled pause times and threshold values — Caches up to 64 packet descriptors per queue — Programmable host memory receive buffers (256 bytes to 16 KB) and cache line size (16 bytes to 256 bytes) — 32 KB configurable transmit and receive FIFO buffer — Mechanism available for reducing interrupts generated by transmit and receive operation — Descriptor ring management hardware for transmit and receive — Optimized descriptor fetching and write-back mechanisms — Wide, pipelined internal data path architecture PHY — Integrated PHY for 10/100/1000 Mb/s full and half duplex operation — IEEE 802.3ab auto negotiation support — IEEE 802.3ab PHY compliance and compatibility — DSP architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation Host Offloading — Transmit and receive IP, TCP and UDP checksum off-loading capabilities — Transmit TCP segmentation, IPv6 offloading, and advanced packet filtering — IEEE 802.1q VLAN support with VLAN tag insertion, stripping and packet filtering for up to 4096 VLAN tags — Descriptor ring management hardware for transmit and receive Manageability — Intel® Active Management Technology (Intel® AMT) support (82573E only) — Alerting Standards Format 2.0 and advanced pass through support (82573E/V only) — Boot ROM Preboot eXecution Environment (PXE) Flash interface support — Compliance with PCI Power Management 1.1 and Advanced Configuration and Power Interface (ACPI) 2.0 register set compliant — Wake on LAN support Additional — Three activity and link indication outputs that directly drive LEDs — Programmable LEDs — Internal PLL for clock generation that can use a 25 MHz crystal — Power saving feature for the 82573L. During the L1 and L2 link states, the 82573L asserts the Clock Request signal (CLKREQ#) to indicate that its PCIe* reference clock can be gated — On-chip power control circuitry — Loopback capabilities — JTAG (IEEE 1149.1) Test Access Port (TAP) built in silicon Technology — Lead-free 196-pin Thin and Fine Pitch Ball Grid Array (TF-BGA) package — Operating temperature: 0° C to 70° C (with external regulators) — Operating temperature: 0° to 55° C (with on- die 2.5V regulator) — Storage temperature -40° C to 125° C
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82573—Datasheet Figures
Datasheet—82573 Tables
82573—Datasheet
Revision History
Jan 2007 2.5 Updated the PHY_REF signal description in Section 2.6. Oct 2006 2.4 Added document order number. Corrected the AUX_PWR pin (C6) description for the 82573E/V. Updated Table 18 “Crystal Specifications”. Updated the visual pin assignments for the 82573L. Major edit all sections. August 2006 2.3 Chapter 1, Introduction, corrected note. 3.5.1, Removed line item 3.5.2, Corrected title Heading June 2006 2.2 Revised Section 3.3, ’PCIe Miscellaneous Signals", updated Intel logo. Feb 2006 2.1 Added Section 5.2, ’Thermal Specifications".” Sept 2005 2.0 Integrated 82573L information into this document. June 2005 1.5 Initial public release.
Datasheet—82573
1.0 Introduction
Note: Unless specifically noted, 82573 refers to the Intel® 82573E, 82573V and 82573L GbE controllers.
82573 GbE controllers are single, compact components with integrated Gigabit
Ethernet Media Access Control (MAC) and Physical Layer (PHY) functions. These devices use PCIe* architecture (Revision 1.0a). For desktop, workstation, and value server network designs with critical space constraints, the 82573 enables a GbE implementation in a very small area. The 82573 provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab, respectively). In addition to managing MAC and PHY Ethernet layer functions, the 82573 manages PCIe* packet traffic across its transaction, link, and physical and logical layers. The 82573E contains a dedicated microcontroller for manageability with an on-board Intel ® Active Management Technology (Intel® AMT) enabling network. This enables manageability implementations required by information technology personnel for out- of-band management, remote troubleshooting and recovery, asset management, and non-volatile storage. Intel ® AMT is the first step towards a complete Intel® Cross- Platform Manageability Program (Intel® CPMP), which is a business and technology initiative to deliver consistent management capabilities, protocols, and interfaces across all Intel platforms. The 82573E and 82573V GbE controllers have an integrated System Management Bus (SMBus) port enabling industry standards, such as the Alert Standard Forum (ASF) 2.0. With SMBus, management packets can be routed to or from a management processor. In addition, integrated ASF 2.0 circuitry provides alerting and capabilities with standardized interfaces. The 82573 with PCIe* architecture is designed for high performance and low memory latency. The device is optimized to connect to a system I/O Control Hub (ICH7) using one PCIe* lane. Alternatively, the 82573 is able to connect to a Memory Control Hub (MCH) device with a PCIe* interface. Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. The 82573 efficiently handles packets with minimum latency by combining a parallel and pipelined logic architecture optimized for GbE and independent transmit and receive queues. The 82573 also includes advanced interrupt handling features and uses efficient ring buffer descriptor data structures, with up to 64 packet descriptors per queue cached on chip. A 32-KB on-chip packet buffer maintains superior performance. In addition, using hardware acceleration, the 82573 offloads tasks from the host (for example, TCP/UDP/IP checksum calculations and TCP segmentation). The 82573L features low power management. During the L1 and L2 link states, the 82573L asserts the Clock Request signal (CLKREQ#) to indicate that its PCIe* reference clock can be gated. The 82573 is packaged in a 15 mm X 15 mm, 196-Ball Grid Array (BGA).
82573—Datasheet
1.1 Document Scope
This document contains targeted datasheet specifications for the 82573 GbE controller, including signal descriptions, DC and AC parameters, packaging data, and pinout information.
1.2 Reference Documents
This application assumes that the designer is acquainted with high-speed design and board layout techniques. The following documents provide additional information:
- IEEE Standard 802.3, 2000 Edition. Institute of Electrical and Electronics Engineers (IEEE).
- PCI Express Base Specification, Revision 1.0a. PCI Special Interest Group.
- PCI Express Card Electromechanical Specification, Revision 1.0a. PCI Special Interest Group.
- PCI Bus Power Management Interface Specification, Revision 1.1. PCI Special Interest Group.
- Intel Ethernet Controller Timing Device Selection Guide. Intel Corporation.
- 82573 NVM Map and Programming Information Guide. Intel Corporation.
- 82573/82562 Dual Footprint Design Guide. Intel Corporation.
- PCIe* Family of Gigabit Ethernet Controllers Software Developer’s Manual. Intel Corporation.
- 82573 Family GbE Controllers Specification Update. Intel Corporation.
Note: The 82573L does not support manageability. Figure 1. 82573 Block Diagram
82573—Datasheet
1.4 Product Codes for the 82573
2.0 Signal Descriptions
2.1 Signal Type Definitions
The signals of the 82573 are electrically defined as follows: Device Top Marking Leaded/ Unleaded Product Features 82573E RC82573E Leaded 82573E with Intel® AMT includes:
- Intel® AMT
- A S F 2 . 0
- A d v a n c e d P a s s T h r o u g h ( A P T ) 82573E PC82573E Lead Free 82573E with Intel® AMT includes:
- Intel® AMT
- A S F 2 . 0
- A P T 82573V RC82573V Leaded 82573V Baseline includes:
- A S F 2 . 0
- A P T 82573V PC82573V Lead Free 82573V Baseline includes:
- A S F 2 . 0
- A P T 82573L RC82573L Leaded 82573L:
- Low-power
- No management 82573L PC82573L Lead Free 82573L:
- Low-power
- No management Name Definition I Input Standard input only digital signal. O Output Standard output only digital signal. I/O I/O Standard I/O digital signal. TS Tri-state Bi-directional three-state digital input/output signal. OD Open Drain Wired-OR with other agents. The signaling agent asserts the open drain signal, but the signal is returned to the inactive state by a weak pull-up resistor. The pull-up resistor might require two or three clock periods to fully restore the signal to the de-asserted state. A Analog PCIe, SerDes, or PHY analog signal. P Power Power connection, voltage reference, or other reference connection.
Datasheet—82573
2.2 PCIe* Data Signals
2.3 PCIe* Miscellaneous Signals
This signal requires a pull-up resistor. PD Pull Down This signal requires a pull-down resistor. Signal Type Name and Function PE_CLKn PE_CLKp A(In) PCIe Differential Reference Clock The reference clock is furnished by the system and has a 300 ppm frequency tolerance. It is used as reference clock for PCIe transmit and receive circuitry and is used by the PCIe core PLL to generate 125 MHz and 250 MHz clocks for the PCIe* core logic. PE_T0n PE_T0p A(0ut) PCIe* Serial Data Output These signals connect to corresponding PERn and PERp signals on a system motherboard or a PCIe* connector. Series AC coupling capacitors are required at the 82573 device end. The PCIe* differential outputs are clocked at 2.5 Gb/s. PE_R0n PE_R0p A(In) PCIe Serial Data Input These signals connect to corresponding PETn and PETp signals on a system motherboard or a PCIe* connector. The PCIe* differential inputs are clocked at 2.5 Gb/s. Signal Type Name and Function PE_RST# I Reset This signal indicates whether or not the PCIe* power and clock are available. PE_WAKE# OD Wake This signal is driven to zero when it receives a wake-up packet and either the PME enable bit of the Power Management Control/Status Register is set to 1b or the Advanced Power Management enabled bit of the Wake Up Control Register equals 1b. AUX_ PRESENT (AUX_PWR) 1. This signal is used in all three devices and has the same functionality but is denoted as AUX_PRESENT in the 82573E/V and AUX_PWR in the 82573L. I Auxiliary Power Present AUX_PRESENT must be pulled up to 3.3V standby power if the 82573 is powered from standby supplies. This signal must be pulled down if auxiliary power is not used. CLKREQ# (82573L only) OD Clock Request. The Clock Request (CLKREQ#) signal is located at ball P9 of the 82573L. When it is sampled high, this open-drain signal alerts the system that the 82573L does not need the PCIe* differential reference clock. During normal operation, the 82573L keeps CLKREQ# asserted (low), and the system supplies this clock to the device on the PE_CLKp and PE_CLKn signals. The 82573L deasserts CLKREQ# (high) when it is in an electrical idle state (L1 and L2), and the system might choose to continue supplying the reference clock or gate it conserving platform power. The CLKREQ# signal should be connected to the clock driver that supplies the 82573L PCIe* clock. If other devices use the same CLKREQ# signal, a pull-up resistor should be used to ensure that no device pulls this signal low when it is powered off. Name Definition
82573—Datasheet
2.4 Non-Volatile Memory Interface Signals
2.5 Miscellaneous Signals
2.5.1 Reset and Power-down Signals
Signal Type Name and Function NVM_SI I/O NVM Serial Data Output The data output pin is used for input to the non-volatile memory device. This pin is occasionally used as input during arbitration. This signal has an internal pull-up resistor. NVM_SO I NVM Serial Data Input The data input pin is used for output from the non-volatile memory device to the 82573. This signal has an internal pull-up resistor. NVM_SK O TS NVM Serial Clock The serial clock provides the clock rate for the memory interface. NVM_CS# I/O NVM Chip Enable This signal is used to enable the device. This signal has an internal pull-up resistor. NVM_REQ O NVM Arbitration Request. This signal is used to request use of the NVM interface. NVM_PROT I/PU NVM Protection Enable. This pin should be connected to ground to disable NVM protection; otherwise, NVM protection is enabled. This signal has an internal pull-up resistor. NVM_TYPE I/PU NVM Device Type If the device uses a Flash, this pin should be connected to a pull-down resistor. If the 82573 is connected to an EEPROM, this pin can be connected to an external pull-up resistor. This signal has an internal pull-up resistor of 30 KΩ ±50%. NVM_SHARED# I/PU NVM Shared Enable This pin should be connected to a pull-down resistor to enable sharing of SPI Flash with ICH. This signal has an internal pull-up resistor. Signal Type Name and Function LAN_PWR_ GOOD I LAN Power Good This signal indicates that stable power is available to the 82573. When the signal is low, LAN_PWR_GOOD acts as a master reset of the entire device. LAN_PWR_GOOD should be connected to a power supervisor driven from auxiliary power. The signal should go active approximately 80 ms after all power rails are within their operating ranges. A PCIe* reset must only occur after LAN Power Good is active. DEVICE_OFF# I Device Off This asynchronously disables the 82573, including voltage regulator control outputs if selected in external control.
Datasheet—82573
2.5.2 System Management Bus (SMBus) Signals 1
Note: The signals listed in the following table should not be connected when using an 82573L. Refer to the 82573/82562 Dual Footprint Design Guide reference schematics for more information.
2.5.3 LED Signals
2.5.4 Other Signals
- The 82573L does not support the System Management Bus (SMBus). Signal Type Name and Function SMB_CLK I/O SMBus Clock The SMBus Clock signal is an open drain signal for the serial SMBus interface. SMB_DAT I/O SMBus Data The SMB Data signal is an open drain signal for the serial SMBus interface. SMB_ALRT#/ ASF_PWR_ GOOD I/O SMBus Alert/PCI Power Good The SMBus Alert signal is an open drain signal for serial SMBus interface. In ASF mode, this signal acts as the PCI Power Good input signal. Signal Type Name and Function LED0# O LED0 This pin provides a signal for programmable LED indication. LED1# O LED1 This pin provides a signal for programmable LED indication. LED2# O LED2 This pin provides a signal for programmable LED indication. Signal Type Name and Function THERMn THERMp O Thermal Test Pins These pins are used for thermal testing. They can be connected to test points. FUSEV P Fuse Supply This should be connected to 2.5V for normal operation.
82573—Datasheet
2.6 PHY Analog and Crystal Signals
Signal Type Name and Function MDI0n MDI0p A Media Dependent Interface [0] 1000BASE-T: In MDI configuration, MDIp0/MDIn0 corresponds to BI_DA+/-, and in MDI-X configuration, MDIp0/MDIn0 corresponds to BI_DB+/-. 100BASE-TX: In MDI configuration, MDIp0/MDIn0 is used for the transmit pair, and in MDI-X configuration, MDIp0/MDIn0 is used for the receive pair. 10BASE-T: In MDI configuration, MDIp0/MDIn0 is used for the transmit pair, and in MDI-X configuration, MDIp0/MDIn0 is used for the receive pair. MDI1n MDI1p A Media Dependent Interface [1] 1000BASE-T: In MDI configuration, MDIp1/MDIn1 corresponds to BI_DB+/-, and in MDI-X configuration, MDIp1/MDIn1 corresponds to BI_DA+/-. 100BASE-TX: In MDI configuration, MDIp1/MDIn1 is used for the receive pair, and in MDI-X configuration, MDIp1/MDIn1 is used for the transmit pair. 10BASE-T: In MDI configuration, MDIp1/MDIn1 is used for the receive pair, and in MDI-X configuration, MDIp1/MDIn1 is used for the transmit pair. MDI2n MDI2p A Media Dependent Interface [2] 1000BASE-T: In MDI configuration, MDIp2/MDIn2 corresponds to BI_DC+/-, and in MDI-X configuration, MDIp2/MDIn2 corresponds to BI_DD+/-. 100BASE-TX: Unused. 10BASE-T: Unused. MDI3n MDI3p A Media Dependent Interface [3] 1000BASE-T: In MDI configuration, MDIp3/MDIn3 corresponds to BI_DD+/-, and in MDI-X configuration, MDIp3/MDIn3 corresponds to BI_DC+/-. 100BASE-TX: Unused. 10BASE-T: Unused. PHY_REF A Reference Input This signal is used as the analog reference input for the PHY. It should be connected to a pull-down, 4.99 K Ω, 1% resistor. XTAL1 I Crystal One The Crystal One pin is a 25 MHz input signal. It should be connected to a parallel resonant crystal with a frequency tolerance of 30 ppm. The other end of the crystal should be connected to XTAL2. XTAL2 O Crystal Two Crystal Two is the output of an internal oscillator circuit used to drive a crystal into oscillation.
Datasheet—82573
2.7 Test Signals
2.7.1 MAC Test Signals
2.7.2 PHY Test Signals
2.7.3 Other Test Signals
Signal Type Name and Function TEST_EN I Factory Test Pin A 1 KΩ pull-down resistor should be attached to ground from this pin for normal operation. ALT_CLK125 NC Alternate 125 MHz Clock This signal should not be connected. This signal has an internal pull-up resistor. JTAG_TCK I JTAG Test Access Port Clock This signal has an internal pull-down resistor. JTAG_TDI I JTAG Test Access Port Test Data In This signal has an internal pull-up resistor. JTAG_TDO O/OD JTAG Test Access Port Test Data Out JTAG_TMS I JTAG Test Access Port Mode Select This signal has an internal pull-up resistor. CLK_VIEW NC Clock View The Clock View signal is an output for the clock signals required for IEEE testing. This signal has an internal pull-up resistor. TEST[16:0] for the 82573E/V TEST[10:0] for the 82573L Rsvd Test Pin[16:0] These test pins are for the 82573E/V only. These signals have internal pull-up resistor. For normal operation, these pins should be left unconnected. Test Pin[10:0] These test pins are for the 82573L only. These signals have internal pull-up resistor. For normal operation, these pins should be left unconnected. Signal Type Name and Function PHY_HSDACn PHY_HSDACp (82573E/V) PHY_TESTn PHY_TESTp (82573L only) 1. These signals are used in all three devices and have the same functionality but are denoted as PHY_HSDACn and PHY_HSDACp in the 82573E/V and PHY_TESTn and PHY_TESTp in the 82573L. A(Out) PHY Differential Test Port These signals are used for factory test purposes only. PHY_TSTPT PHY Test Port This signal is used for factory test purposes only. This pin must be left unconnected for normal operation. Signal Type Name and Function SDP[3:0] NC These signals are used for factory test purposes only and have internal pull-up resistors.
82573—Datasheet
2.8 Power Signals
2.8.1 Power Support Signals
2.8.2 Digital and Analog Power Supply Signals
2.9 Grounds and No Connects
Signal Type Name and Function CTRL_25 P 2.5V Control This is the voltage control signal for external 2.5V. It is only active when the EN25REG signal is low (disabled). When external 2.5V and 1.2V supplies are used, CTRL_25 can be left floating or can be connected to ground through a 3.3 KΩ resistor. CTRL_12 P 1.2V Control This is the voltage control signal for external 1.2V. When external 2.5V and 1.2V supplies are used, CTRL_12 can be left floating or can be connected to ground through a 3.3 KΩ resistor. EN25REG I/PU Enable 2.5V Regulator When this signal is high, the internal 2.5V regulator is enabled. When it is low, the internal 2.5V regulator is disables and the CTRL_25 signal is active. This signal should be pulled up to the 3.3V power rail. Signal Type Name and Function VCC33 P 3.3V Power Supply This signal is used for I/O circuits. VCC25 P 2.5V Analog Power Supply These signals are used for PHY analog, PHY I/O, PCIe* analog and phase lock loop circuits. All 2.5V pins should be connected to a single power supply. VCC12 P 1.2V Digital Power Supply These signals are used for core digital, PHY digital, PCIe* digital and clock circuits. All 1.2V pins should be connected to a single power supply. IREG25_IN (82573E/V) VCC3.3_REG25 (82573L only) 1. This signal is used in all three devices and has the same functionality but is denoted as IREG25_IN for the 82573E/V and VCC3.3_REG25 for the 82573L. P IREG25_IN supplies are used, IREG25_IN should be connected to 3.3V. VCC25_OUT P VCC25_OUT 2.5V output supply from internal power supply. When external 2.5V and 1.2V supplies are used, VCC25_OUT can be left floating. Signal Type Name and Function VSS P Ground These signals connect to ground. VSS is also referred to as GND. NC No Connect These pins are reserved by Intel and might have factory test functions. For normal operation, do not connect any circuitry to these pins. Do not connect pull-up or pull-down resistors.
3.0 Voltage, Temperature, and Timing Specifications
3.1 Absolute Maximum Ratings
3.2 Recommended Operating Conditions
3.3 Power Supply Connections
- Connecting the 82573 to three external power supplies with nominal voltages of
- Powering the 82573 with only an external 3.3V supply and using internal power regulators from the 82573 combined with external PNP transistors to supply the
- Using the 2.5V internal (on-die) regulator combined with an external PNP transistor
Table 1. Absolute Maximum Ratings
- Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings
device operations. This specification is not guaranteed by design or simulations. Table 2. Recommended Operating Conditions
3.3.1 External LVR Power Delivery
built into the 82573 as described in Section 3.3.3. Table 3. 3.3V External Supply Voltage Ramp and Sequencing Recommendations
- Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.
- Excessive overshoot can affect long term reliability.
Table 4. 2.5V External Supply Voltage Ramp and Sequencing Recommendations
- Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.
- Excessive overshoot can affect long term reliability.
- Tantalum capacitors must not be used.
3.3.2 Power Sequencing with External Regulators
risk of either latch-up or forward biased internal diodes. in the following two subsections.
3.3.2.1 External LVR Power Up Sequencing and Tracking
required to begin ramping before the 3.3V or the 2.5V supply. Table 5. 1.2V External Supply Voltage Ramp and Sequencing Recommendations
- Good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less.
- Excessive overshoot can affect long term reliability.
- Tantalum capacitors must not be used.
- If the 1.2V and 2.5V rails power up before 3.3V, they should never exceed the 3.3V supply by more than 0.3 V.
- At power down, all three supplies should be turned off simultaneously. If the 3.3V supply powers down first, the 1.2V and 2.5V supplies must never exceed the 3.3V supply by more than 0.3 V.
3.3.2.2 External LVR Power Down Sequencing
in decoupling capacitors is left in the system.
3.3.3 Internally Generated Power Delivery
(nominal). These two voltages are stepped down from a 3.3V source. Figure 2. Minimum Requirements for Power Supply Sequencing Table 6. 3.3V Internal Power Supply Parameters
- The peak to peak output rippled is measured at 20 MHz bandwidth within the operational range.
Maximum overshoot allowed duration.
3.3.4 Internal LVR Power Sequencing
3.3.4.1 Power Up Sequencing and Tracking
are necessary to prevent electrical overstress or latch-up. circuit. The 2.5V supply tracks the 3.3V ramp. 3.3V supply at any time. The delay is proportional to the slope of the 3.3V ramp.
- It is recommended that the voltage on a lower voltage rail never exceed the voltage on a higher voltage rail during power on.
- There are no minimum time requirements between the voltage rails as long as they power up in sequence: 3.3V → 2.5V → 1.2V.
- All 3 supplies must be stable for at least 80 ms before LAN_PWR_GOOD is asserted. 100 ms is preferable if possible.
- A PCIe* reset must occur after LAN Power Good is active.
3.3.4.2 Internal LVR Power Down Sequencing
storing in decoupling capacitors is left in the system. Figure 3. Power Supply Sequencing
3.3.4.3 Internal Voltage Regulators Components for the 82573
Table 7. 82573 Bill of Materials (BOM) of Components for Internal Regulator Table 8. 2.5V Internal LVR Specification 1
- The use of tantalum capacitors is not recommended.
3.3.4.6 PNP Transistor Specification for Internal LVR
Table 9. 1.2V Internal LVR Specification 1
- The use of tantalum capacitors is not recommended.
Table 10. PNP Specification (Sheet 1 of 2)
3.3.4.7 Internal LVR Board Schematic
ce and out of the linear region. Table 10. PNP Specification (Sheet 2 of 2)
3.4 DC and AC Specifications
Figure 4. 82573 2.5V and 1.2V LVR Schematic Table 11. 82573E and 82573V Maximum Measured External Power Characteristics 1
- Maximum conditions refer to fast silicon, high temperature and nominal VCC.
Table 12. 82573E and 82573V Typical Measured External Power Characteristics 1
- Maximum conditions refer to fast silicon, high temperature and nominal VCC.
- For 10/100 Mb/s non-stress mode with Intel® AMT, add 12 mW to this number (for example,
- For 10/100 Mb/s stress mode active Intel® AMT, add 120 mW to this number (for example, using
1000 Mb/s:
100 Mb/s Idle 11 107 101 425
- The current use is slightly higher in the device off state than in the no link state. This occurs since
a PHY reset is required in the device off state, which overrides the PHY power down. Table 13. 82573E and 82573V 2.5V Internal Power Regulator Numbers
1000 Mb/s: Active with
1000 Mb/s Active 313 Internal 506 1638
1000 Mb/s Idle 294 Internal 404 1453
100 Mb/s Active 142 Internal 145 642
100 Mb/s Idle 119 Internal 101 513
10 Mb/s Active 173 Internal 126 722
10 Mb/s Idle 84 Internal 83 376
Table 14. 82573L Maximum Measured Power Characteristics 1
- Maximum conditions refer to fast silicon, high temperature and nominal VCC.
Table 15. 82573L Measured Power Characteristics Table 16. DC Specifications
3.5 External Interfaces
3.5.1 Crystal
various specification options.
3.5.2 External Clock Oscillator
coupling is not recommended. Table 17. LED DC Specifications
- Outputs are inputs/outputs in test mode.
- This parameter is characterized but not tested.
Table 18. Crystal Specifications
- This value can change up to 10%.
3.5.3 Non-Volatile Memory (NVM) Interface: EEPROM
Figure 5. External Clock Oscillator Connectivity to the 82573 Table 19. Specification for External Clock Oscillator Table 20. NVM Interface Timing Specifications for EEPROM (Sheet 1 of 2)
4.0 Package and Pinout Information
This section describes the 82573 physical characteristics and pin-to-signal mapping.
4.1 Package Information
measuring 15 mm by 15 mm. The nominal ball pitch is 1.0 mm. Table 20. NVM Interface Timing Specifications for EEPROM (Sheet 2 of 2) Figure 6. 82573 Controller TF-BGA Package Ball Pad Dimensions
Figure 7. 82573 Mechanical Specifications
82573—Datasheet
4.2 Thermal Specifications
The case temperature (TC) is calculated using the equation: TC = TA + P (⎝JA - ⎝JC) Junction temperature (TJ) is calculated using the equation: TJ = TA + P ⎝JA The power consumption (P) is calculated by using the typical ICC and nominal VCC where TA represents the ambient temperature. The thermal resistances are listed in Table 21.
board thickness, arrangement of ground planes, and proximity of other components.
4.3 Pinout Information
4.3.1 PCIe Bus Interface Signals
Table 21. Thermal Resistance Values Table 22. PCIe Data Signals
4.3.2 Non-Volatile Memo ry Interface Signals
4.3.3 Miscellaneous Signals
Table 23. PCI Express Miscellaneous Signals
- This signal is used in all three devices and has the same functionality but is denoted as AUX_PRESENT
in the 82573E/V or AUX_PWR in the 82573L. Table 24. Non-Volatile Memory Interface Signals Table 25. Reset and Power-down Signals Table 26. SMBus Signals Table 27. LED Signals Table 28. Other Signals
4.3.4 PHY Signals
4.3.5 Test Signals
Table 29. Analog and Crystal Signals Table 30. 82573E/V MAC Test Signals 1
- These test signals do not apply to the 82573L.
Table 31. 82573L MAC Test Signals 1
- These test signals do not apply to the 82573E or 82573V devices.
Table 32. PHY Test Interface Signals
4.3.6 Power Supply Signals
Table 33. 82573E/V Other Test Signals 1
- These test signals do not apply to the 82573L.
Table 34. Power Support Signals Table 35. Power Signals
Table 36. Ground Signals Table 37. 82573E/V No Connect Signals 1
- These test signals do not apply to the 82573L.
Table 38. 82573L No Connect Signals 1 (Sheet 1 of 2)
4.4 Visual Pin Assignments
Figure 8. 82573E and 82573V Gigabit Ethernet Controller Pinout
- These test signals do not apply to the 82573E or 82573V devices.
Table 38. 82573L No Connect Signals 1 (Sheet 2 of 2)
Figure 9. 82573L Gigabit Ethernet Controller Pinout