315038-003US

81348 INTEL | Alldatasheet

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Order Number: 3150 38-003 US D ecem b er 200 7 Int e l ® 8 134 8 I /O Pr ocess or Dat a s he et Product Fea t u re s /square6 T w o In t e gr a ted In tel X S ca le ® p roc es so rs — 667 MHz , 800 MHz a nd 1.2 GHz — A RM* V 5TE Co mpl ian t — In stru ctio n/ D a ta Ca ch e : 32 K B yte, 4-way Se t As so ci at iv e, N R U R ep l ac em e nt A lgo rith m, Lo cka ble — U nif ied Level 2 Cac he : 512 K B yte Se t As so ci at i v e , N R U R ep l ac em en t Al g or i t hm — 128-En try B r a nc h T a rget B u ffer — 8-E ntry W ri t e B uff er — 8-E ntry F ill an d P e nd B uff er /square6 In t e rna l B u s 128-bit w id e a t 3 33 M Hz an d

400 MHz d epe nd in g o n pro ce ss or spe ed

/square6 Ca n su pp ort ei the r PCI- X o r PC I Exp res s* a s an end p oi nt /square6 Ca n su pp ort b oth PC I - X Ce ntr a l R e so u rce an d PC I E xp r e ss * R oot C om p le x /square6 S up po rt fo r PC I E xp ress * Lan e Width s o f x 1 , x2, x4, x8 /square6 Ei g ht Se r i al - A t t a che d SC SI l i nk s — al so c apa bl e o f s up po rt i ng di rect -a t ta ch ed SA T A targ ets /square6 In t e gr a ted S RA M M em ory Co ntro lle r (1 MB ); d ed i ca t e d t o t he S A S t r an sp or t /square6 A ddre ss T ran sl atio n Un it — 2 K B or 4 K B O ut b ou nd R e ad Qu eu e — 4 K B O ut b oun d W r i t e Qu eue — 4 KB Inb ou n d Read an d W rite Q ue ue /square6 A ppl ica tio n D M A Co ntro lle r — T hr e e I nd ep e nd ent Ch ann el s Co nne ct ed t o th e M CU a n d th e S ou th Intern al B us — 4 KB yte Da t a T ran sf er Q ue ue — CRC 3 2C Calc u latio n — P e r f or m s Op t i on al XO R on R ea d D at a /square6 Mu lti-p orted M emo ry C on trol ler — Intel XS c ale ® p r oc es so r i np ut s an d n or t h i nt e r na l bus , s out h in t e r nal b us a nd A D MA in pu t po rts — PC 3 200 an d PC4300 Dou b le Da t a R a te (DDR2 4 00, DDR2 5 33) — Up t o 4 GB o f 64-bi t D DR2 400, D DR2 533 — Op t i on a l S in gle -bit E rror Corre ctio n , Mu lti- b i t D et ec t i on E CC S upp or t — S up por t s R e gi st er e d and Un bu f fe r e d D D R 2 Me mo ry — 36 -b it A ddre ss abl e — 32 -b it M emo ry S u ppo rt /square6 T w o Pro gram ma ble 32 -b it Tim ers an d W at ch dog T i me r /square6 Si xteen Gen e r al Pu rpo s e I/O Pin s /square6 E i gh t ACT I V ITY/ST A TUS pa irs — o n e p er SA S po rt /square6 Th ree I 2 C Bu s I n terfa ce Un its /square6 T w o UA R T (16 550) Un its — 64 Byte R ec eive an d T r a ns mit F IFO s — 4 pin M as ter/S lave Ca pa ble /square6 P e riph eral Bu s Interfa c e — 8-, 16-bi t D a ta B u s with T w o Ch ip Se lec t s — 25 D e mu ltip lexed Ad dres s Li ne s /square6 Interru pt Co n trol ler U ni t — F o u r P rio rit y Levels — Interru pt Pen di ng R eg ister — V ecto r Gen eratio n — 1 6 E x t e r nal I n t er r u pt Pi ns w i t h H i gh P r i or i t y Interru pt (HP I#) /square6 13 57-ba ll, F lip Ch ip B a ll Gri d A rr ay (FCB GA ), 37 . 5 m m x 37. 5 mm an d 1 . 0 mm ba ll pitch

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Leg al Li nes and Dis clai m ersLeg al Li nes and Dis clai m ers INFORMA TI ON I N T H I S DOCUMENT I S P ROVIDED I N C O NNECTI ON WIT H I N T EL® PR O D UCT S. NO LICENSE, EXPRESS O R I MPLIED, BY ESTO P PE L OR O THERWISE, T O A N Y INT E LLECT UAL PR O PERTY RI GHTS IS GRANTED BY THIS DOCUM E NT . EXCEPT AS P ROVIDED IN I NTEL ’ S TERMS AND C O NDI TI O NS O F SALE FOR SUCH PRODUC TS, INTEL ASSU MES NO LI ABILI TY WHA TS O EVER, AND INTEL D ISC LAIMS ANY E X PRESS OR IM PLIED W ARR AN T Y , R E LA TI NG TO SALE A N D /OR USE O F I NTEL PRODUC TS INCLU DING LI ABILI TY OR W A RRANTI ES RELA T ING TO F IT N ESS FOR A P ARTI CU LAR PUR PO SE, MERCHANT ABI LITY , OR I N F RING E MENT OF ANY P A TENT , COPYR IG H T O R O T HE R INTELLECTU AL PR O P E RTY R IG HT . I nt el pr oducts are not i ntend ed for use i n medical , l i fe savi ng , l i fe sustai ning, cr i ti cal cont rol or saf ety sy stem s, o r i n n ucl ear fac ilit y a p p li cati ons. Intel m ay m ak e chan ges to sp eci fi cat i ons and prod uct d escri p ti ons at a n y tim e, w i th o u t noti ce. Desi g ners m u st not r el y on t he a bse nce or ch aracte ri sti cs of any featur es or i nstr ucti ons mark ed “ r eserv ed” or “ un defined. ” I nte l re serve s these for futur e d efi ni t i on and shall hav e n o resp onsi bi li ty w hat s oev er for confli cts or i n co mp ati bi li ti es ari si n g from f uture chang es to th em . T h e informati on here i s subj ect to ch ange w ithout noti ce. D o not fi nal ize a design w ith th i s i nfor m atio n . The p rodu cts descr i bed i n thi s d ocum en t may contain de si gn d efects o r err ors kn o wn as e rr ata whi ch may cause the prod uct to d ev i ate from pu bl i sh ed sp eci fi catio n s. C ur rent char acteri zed er rata are av ai l ab l e on requ est. Contact y our l ocal I nte l sal es off i ce or y our d i stributor to obtai n the latest sp eci fi cati ons and b efore pl aci n g y o u r p roduct o rder . Copi es o f document s w h i ch ha ve an orde r nu m b er an d ar e re ference d i n thi s document, or other I n tel l iter ature, m ay be obtai n ed b y call i ng 1-800-548- 472 5, or b y vi siti ng I nte l ’ s W eb Si t e . Intel processor numbers are not a measure of per formance. Processor n umbers di ff erentiate feat ures wi thin each p rocessor f am i ly , not across di f feren t p rocessor fami l ies. See htt p:/ /ww w . intel .com/ p roduct s/ p rocessor_nu m b er for det ai l s. Code N am es are onl y for u se by I nt el to i d enti f y p roduct s, pl atf o r m s, prog rams, serv i ces, etc. (“prod ucts” ) i n dev el opment by I nte l that have not be en made co mmerci all y av ai l ab l e to t he pu bl i c, i.e. , ann o u nced, launched or shi p ped . They ar e nev er to be use d as “com mercial ” n am e s for p roduct s. Al so, th ey are not i nt ended to fu ncti on as t rad emarks. Bunn yP eopl e, Cel er o n , C eleron Insi de , C en tri no , C en tri no lo g o, Core Insi de, F l ash File , i 960, InstantIP , I ntel, I nt el l ogo , I nt el 386, Intel 48 6, I nt el 740, Intel DX2, I nt el DX4, Intel SX2, Intel C or e, Intel Insi de , Intel Insi de l og o, Intel. Leap ahead. , Intel . Leap ah ead. l ogo, Intel N et B u rst, I nte l NetMerg e, I nte l N etStruct ure, Intel S ingl eDr i ver , Intel S p eedSt ep, I nte l Str ataF lash, I n tel Vi i v , I n tel vPr o, I n tel XScal e, Itani u m , Itani um In si d e, MC S, M MX, O pl u s , O verDr i ve, PDCharm, Pen ti um, Pe nti um Insi de, skoool , Sound M ar k, The Journey I n si de, VT un e, Xe o n , and Xeon Insi d e are tr ademark s of I nt el Corpor ati on i n the U.S. and o t her coun tri es. *O ther names and br ands m ay be cl ai med as the p roper ty of o t hers. Copyr i ght © 2007, I ntel C or por ati on. Al l r i gh ts reser ved .

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 3 Conte n t s—Intel ® 8 134 8 Con ten ts 2.2. 9 I 4.1 V 4.3. 4 I

In t e l ® 813 48—Contents In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

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17 AC Tes t L o a d fo r a ll S ig na ls Ex cep t PCI, P CI-Exp res s a nd DDR2 an d

22 Tran s mitter Te st Lo ad (10 0

28 Intel ® 8134 8 I/O Pro c es so r S t o ra ge P HY 1. 2 V/1. 8 V Po w er S equ en c in g

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 5 Conte n t s—Intel ® 8 134 8 Ta b l es

15 I n te l

3 4 S t o ra ge I n terfa ce Tran s mitter O utp ut E lec trica l C ha rac teris t i cs [S_TX P [7 :0] S _TX N[7 :0] .. . 89 3 5 S t o ra ge I n terfa ce Rec eive r Inp ut E le ctric al Cha rac teris t i cs

In t e l ® 813 48—Contents In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

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D ate Revision Desc ript ion De cem ber 20 07 00 3 R e vi sed for 4 G B me mory s upport . A p ri l 200 7 0 02 Upda te d Le gal p age 2 . Edi t ed t ext i n S e c t ion 2 .2 .2 . R e vi se PCIX C AP descr i pti on i n Ta b l e 5 . Upda te d Ta b l e 1 9 for Cgp, Cpci x, C ddr2 a nd L pi n va l ues . Re v is e d Ta b l e 1 8 for T ca se (T c) m axi m um v a l ue to 1 00 C. Re v is e d F i gu r e 28 . October 2 00 6 00 1 I ni t i al r el e ase .

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 7 Introd uction—In t el ® 813 48 1 .0 Int roduct ion

1.1 About T h is D o cumen t

Th is do cu me nt i s a refe ren ce gu ide fo r th e ex t e rna l a rch itec ture of the Intel ® 813 48 I/O Pro ce ss or (a ls o k no w n as the 81 348). 1. 1. 1 T er mi no logy T o ai d th e di sc us s ion o f th e 81348 a rch itec ture , th e f ol lo wi ng t e rmin o lo gy is us ed: Do wn strea m At o r to ward a P CI bu s w ith a h igh er nu mb er (a fter co n fig uratio n ) W o rd 16 bits o f da ta Dwo rd 32 bits o f da ta Qw o rd 64 bits o f da ta Ho st p roc es so r P roc es so r lo c ated up strea m f rom the 81 348 L oc al p r oce s sor I n t el XS ca l e ® pro c ess o r wi t h in th e 8134 8 Lo ca l bu s 813 48 i nt er n al bu s Lo ca l me mo ry M emo ry s u bsy stem o n th e In tel X S ca le ® m ic roa rch itec ture , DDR2 SDRA M or P e riph er a l B u s In terfa ce bu ss es U ps t r e am A t o r t o wa r d a PC I b us wi t h a l owe r n umb e r ( a f t er co nf ig ur a t i on) 1. 1. 2 Ot h er Re le van t Do cum en t s 1. Intel X Sc al e ® M ic roa rch ite ctu re D eve lo per’s M an u al (O rder Num ber 27 3473)—In t el C or p or at io n 2. P CI L o c al Bu s Sp ec ific atio n , R evis io n 2.3— PCI S pec ia l In t e res t Gro u p 3. PC I - X Ad de nd um t o t h e P CI L oca l B us S pe c if i ca t i on, R ev i si on 2 .0 a —P C I Sp ec i al Intere st Gro u p 4. P CI Hot-P lu g S pe cifi ca tion , R ev isi on 1. 0—P CI Sp eci al I n tere st Gro up 5. PC I B us P owe r Ma na ge m ent I nt e r f ac e S pe c if i ca t i on , Revis io n 1.1—P CI S pec ia l Intere st Gro u p 6. PC I E x pr e ss Sp ec i fi c at i on , R e visi on 1. 0a— PCI S pec ia l In t e res t Grou p

In t el ® 8 1 34 8— I n t r o d uc t i o n In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

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In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 9 Fea ture s—Intel ® 8 134 8 2 .0 Fea t u re s

2.1 About the Intel ® 8 13 48 I /O P ro cess o r

Th e 8134 8 i s a s in gle - or du al-f un c t i on P CI dev ice tha t in tegrates two In t e l X Sc al e ® pro c ess o rs w ith in telli gen t pe riph er a ls in cl ud in g a PC I bu s i nterf ac e a nd eig ht S eria l- Attac he d SCS I (SA S ) en gi ne s. Th e 813 48 als o s up po rt s tw o in tern al bu s se s: North X S I b us a nd Sou t h XS I bu s. W i t h t he t wo i nt e r na l b us se s , t r ans ac t i ons ca n t a k e p l ac e si mu ltan eo u sl y o n eac h bu s. Th e n o rth XS I bu s p rovi des the two In tel X S ca le p r oce s sor s wi t h l ow - l at e nc y ac ce ss t o ei t h er t he D D R 2 SD R AM Me mo r y C on t r ol l er , t he o n-c h ip SRA M M em ory Co n trol ler , o r th e SA S En g ine s co n trol re gis t e rs. P e riph erals th at g en er a t e l a r ge bu r st t r a nsa ct io ns a r e l oc at ed on t h e s out h XSI b us , t hu s a ll ow in g t h e two In t e l X S ca le ® pr o ce ss or s e x c l usi v e ac ce ss t o t h e no r t h XS I bu s. Th e 8134 8 c o ns o lid ates the fo llo w in g fe atu res into a si ng le s ys t e m:

• T w o Intel X Sc ale ® p r oc es sor s r unn in g a t sp e ed s u p t o 1 .2 G H z
• E igh t Se ria l P roto co l Li nks c apa bl e o f S eria l- Atta ch ed SCS I (SA S) o r S eria l A T A ( S A T A) op er a t i on
• P CI –Loc al Me mo ry B u s A dd r e ss T ran sl atio n Un it, fu nc tio n 0 pro gr a mm in g in terfa ce
• Me s sa gi ng Un it , f unc t i on 0 p r og r a mm i ng in t e r fa ce
• A ppli ca tio n Di rect M em ory Ac ce ss (DMA ) Co n t ro ll er (in c lu din g o ff lo ad for up to a 16-so u rce XOR op er a tio n)
• T ran sp ort DM A Con tro lle r s
• Perip he r al B us Interf ac e U ni t
• Integ r a t e d DDR2 M emo ry C on trol ler
• Integ r a t e d S RAM M em ory Co ntro lle r
• T w o pro gram mab le t i mers pe r Intel XS c ale ® p r oc es so r
• W a t c h do g tim er pe r Inte l X Sc al e ® p r oce s sor
• Th ree I 2 C B us I n t e r f ac e U ni t s
• T wo Se r i al P o r t Un it s
• S ixteen Ge ne r al -Pu rpo s e In pu t /O u t p ut (GP IO) p orts
• A CTIVITY/S T A TUS p in pai rs— on e per S AS E ng in e
• Intern a l No rth Bu s–So u th Bu s Bri dge I t i s a n i nt e g r a t e d p r oc es so r t hat ad dr e s se s t h e ne e ds of in t e ll i ge nt I / O s t or ag e a pp l ic at io ns a nd h el p s r e d uce i nt e l li g en t I / O s y st e m c os t s. Th e 813 48 c an su pp ort P CI - X 1. 0b an d/o r P CI E xpres s* a s a res et op t i on . The PC I b us is a n in du stry sta nd ard, hi gh -perfo rm an ce , lo w-la ten cy sys tem bu s . The 8134 8 PC I bu s is ca pa ble o f 133 MHz o peratio n in P CI - X 1. 0b m od e (a s d efin e d by t h e PCI-X A dde nd um to t h e Lo c al Bu s Sp eci fic atio n , Revis io n 1 . 0b). A lso , th e p roc es so r s up po rts a 6 6 MH z c onv en t i ona l P CI mod e ( as d e fi n ed by t h e PC I L o c al Bu s Sp eci fic atio n , R ev isi on 2. 3 ). Th e add itio n of t h e I n tel XS ca le ® p r oc es so r s b r in gs in t e ll i g en ce t o t he P CI bu s a pp lic atio n brid ge. 8134 8 s u ppo rts a n x8 P CI Exp res s* in terfa ce .

Inte l ® 81 348—Feat u r es In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

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The 8134 8 ca n be se t up a s a s in gle - o r d ua l-fu n ctio n P CI de vic e a t res et u si ng ex t e rna l str a ps . R e fer to th e “Cl oc kin g an d R e se t” s ectio n in th e In t e l ® 8134 8 I/O Pro c ess o r D ev e l op er ’ s Ma nua l fo r a d esc rip t i on o f th e res et o ptio ns . Whe n th e 81348 is c o nfi gu red as a s in gl e-fu nc tio n devi ce , th e h o st p rog r am mi ng in t e rfac e i s p res en t e d a s th e Ad dres s T r a ns la t i on U ni t (A TU) an d th e M es sa gin g Un it (MU ). The M U pro vid es t h e mes sa gin g in t e rfac e b etwe en the h os t pro ce ss or an d th e 81348 . Whe n t h e 8 1348 is co n figu red a s a du al -fu nc tio n d evi ce, P CI fu nc tio n 0 ho s t pro gr a mm in g in terfa ce is pres en ted as the A TU wi th th e M U. Th e res et s t rap pin g op t i on s dete rmin e h o w t h e co n t ro ll er’ s SA S/SA T A po rt s a re a ss ign ed t o f un cti on 1 a nd f u nct io n 0 . B ot h t he a d dr e ss and d at a bu ss es on t h e 8 1 3 4 8 so ut h X SI b us a r e b y t e - wi s e p ar i t y p r ot ec t e d. Al l t h e p e r ip he r al s c onn ec t e d t o t he sou t h XS I bu s ca n c he ck and g en er at e pari t y . Fig ure 1 is a blo ck dia gram of t h e 81 348. Figu re 1 . In tel ® 8 13 4 8 I / O Pr o cesso r F un ctio nal Blo ck Diagr am PCI - X Intel® 81348 I/O Processor B6 1 4 0-0 1 16 -Bit I/F I 2 C Bus 72-B i t I/F SAS Serial Bus Serial Bus Bridge Multi - Port DDR II SDRAM Memory Controller Three Application DMA Channels Host Interface (A T U , CHAP) Two Transport DMA Channels Multi - Port SRAM Memory Controller Two UARTs Three I 2 C Bus Interface APB PBI Unit (Flash) SAS 0 PHY SAS 1 PHY SAS 7 PHY Intel XScale® Processor (Core ID = 0H) 512K L 2 Cache TimersIntel XScale® Processor (Core ID = 1H) 512K L2 Cache Inter -Core Interrupt Interrupt Controller Timers Inter -Core Interrupt Interrupt Controller SMBus Unit SMBus 128- Bit South Internal Bus 128- Bit North Internal Bus SAS Serial Bus PCI - E IMU Host Interface (A T U, CHAP)

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 11 Fea ture s—Intel ® 8 134 8

2.2 Intel ® 8 13 48 I /O P roc ess o r Fea t ures

Th e 8134 8 c o mbi ne s tw o Intel XS c ale ® p r oc es so r s wi t h p ow er f ul ne w f e at u r es t o cre ate an in telli gen t I/O s torag e pro c es so r . Th is si ng le- or d ua l-fu n ctio n P CI devi ce is fu lly co mp lia nt w ith the PC I -X A dde nd u m to the PCI Lo c al B u s Sp eci fic atio n , R ev isi on 2. 0 an d P CI E xpre ss Sp ec ific atio n , R evis io n 1.0. F e atu res sp eci fic to 8 1348 in cl ud e th e fo ll ow in g: Th e 8134 8 i s b as ed up on tw o I n tel XS ca le ® pro ces so rs . The pro ce ss or op er a tes at a ma xim um fre qu en cy of 1 . 2 GHz . Th e in s t ru c t i on c ac he is 32 Kbytes in s ize an d is 4 -way se t as so ci ative. A ls o, t h e pro ces so r i nc lu des a da t a c ac he tha t is 32 K b ytes an d i s 4- way se t as so ci ative. Th e In tel X S ca le ® p roc es so rs als o su pp ort a u ni fied 512 -Kb yte Level 2 (L2 ) ca ch e th at is 8-way s et a ss oc ia t i ve. Th e 8134 8 i nc lu de s s ixtee n G en er a l P urp os e I/O (GP I O ) pi ns , an d e igh t AC TI V ITY/ S T A TUS pi n pai rs w h ich a re u s ed f or S AS lin ks fo r a ctivi t y an d s tatus in di ca tors . Ea ch SA S l in k u se s o n e A CTIVITY/S T A TU S p in pa ir . No te: T he su bs ec t i ons t ha t f ol lo w p r ov i de a b r i ef ov er v i ew of ea ch f e at ur e . R ef e r t o t h e a pp r op r i at e ch ap t e r in t he I n tel® 813 48 I/O Pro c ess o r De vel op er’s Ma nu a l fo r fu ll tec hn ic al des cri ptio ns . 2. 2. 1 H os t I nt e rf ace Th e 8134 8 ca n b e s et u p a s e ithe r a sin gl e- o r du a l-fu n ctio n PCI d evic e, pro vid in g P CI - X o r PCI E xp ress * in terfa ce or b o t h P CI - X a n d P CI E xpres s* i nterf ac es. Th e PCI i nt e r f ac e i s s e le ct ed as a r e se t op t i on. Wh en se t up as a si ng l e- f un ct i on PC I d ev i ce , t h e A ddre ss T r a n sla tio n Un it (A TU ) an d t h e Mes s agi ng Un it (M U) p rovi de th e p rog r am mi ng in terfa ce betw een th e h o st pro c ess o r an d t h e 8 1348. W he n s et u p a s a d ua l-fu n ctio n de vic e, t h e A TU an d th e M U prov ide t h e pro gr a mm in g in terfa ce be t w ee n th e h o st pro c ess o r an d th e 81348 fo r fu nc tio n 0 , w h erea s th e Th ird -P a rt y Me ss ag ing Inte rfac e (TP MI) p rovi des th e p rog r a mmi ng in terfa ce be t w ee n the h os t pro c es so r a nd th e 81348 fo r fu n ctio n 1. Th e P CI in terfa ce is sel ecte d a s a res et o ptio n .

• A dd r e ss T r an sl at io n Un it • D D R 2 SD R AM M em or y C ont r o ll e r
• M es sa g in g U ni t • T r a nsp or t D MA C on t r ol l er s
• Fla sh In terfa ce Un it • UA R T U ni t s
• Chi p A rch itec ture Perfo rma nc e U n it • A ddre ss an d Data B u s P a rity Pr o t ec t i on

2 C Bu s Interf ac e Un its • In t e r -P ro ces so r C om mu n ica tio n

• Mu lti-Po rt SRA M Mem o ry Co ntro lle r • Tim ers
• A pp l i ca t i on D MA C ont r o ll e r s • W at c hd og T im e r s
• XS I Sys t e m Co n trol ler (n o rth a n d s out h)
• E igh t SA S L i nk En gi ne s w ith in teg r ated P HY s

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1. 2. 2 Inter n al B usse s The 813 48 i s bu il t aro u nd two in tern al bu ss es : n orth in tern al bu s a n d s ou th in t e rna l b us . T he t w o b uss e s us e t he sa me bu s p r ot o col . Th e n or t h in t er n al b us i s 1 2 8 b it s wi d e a nd op er at es at u p t o 4 0 0 MH z. Th e n or t h b us c on ne ct s t he t wo I nt e l X Sc al e ® pro ces s ors , wh ic h ha v e dire ct a cc es s to th e DDR2 SDRA M an d S RA M. Th e In tel X S ca le ® pro ces s ors al so h ave d irec t ac ce ss to th e S AS /SA T A Fi bre C ha nn e l en gi ne me mo ry - ma ppe d reg iste rs. Th e n o rt h X SI b us is de si gn ed to pro vid e th e two In tel X S ca le ® p r oc e sso r s wi t h lo w- l a t en cy ac ce s s. The so u th i nte rna l bu s is 12 8 b its wid e a nd o perates at u p t o 400 MH z. Th e s o uth X SI bu s p rovi des the da t a pa ths fo r b urs t t ran sa c t i on s gen erated by th e DM As . The so u th XS I bu s in t e rna l a ddre ss an d data bu ss es a r e pa rity -pro tec t e d o n a byte-wi se bas is . Ag en t s o n t h e so u t h X SI b us c an ge ne r a t e an d ch ec k ad dres s an d d ata pari t y . Th e p oi nt - t o- p oi nt i nt e r f ac es be t w ee n t h e a ge nt s an d t h e D D R 2 a nd SR AM Me mo r y Con tro lle r s a re a lso p arity -p ro t e cted on a byte-w is e ba si s. No t e : I n tern al bu ss es ru n at 333 M Hz fo r 6 67M Hz c o re sp eed . In tern al b us se s ru n at 40 0M Hz fo r 80 0M Hz an d 1. 2GHz co re s pe eds . 2. 2. 3 Ap p l ic a tio n D M A Con tr ol le rs The re a re th ree A pp lic atio n DMA Co n t ro ll ers . Th e Ap plic atio n DM A Co n trol ler i s d ua l- p or t ed — wi t h o ne o f i t s po r t s c onne c t e d t o t he s out h XS I bu s an d t h e ot he r p or t t o t he D DR2 S DRA M M em ory Co ntro lle r . Th is Ap pli ca t i on DM A C on tro ller all ow s lo w-la t e nc y , h ig h- t hr ou ghp ut d a t a t r a nsf e r s b e t we e n PC I b us a ge nt s an d t h e D D R2 m e mo r y . T he D MA c ont r o ll e r al so al lo ws d a t a t r a nsf e r be t w ee n D D R 2 M em or y . T he D MA C on t r ol l er su ppo rts ch ai ni ng an d un al ign ed da t a tr a ns fers . It i s p rog r a mma bl e th rou gh th e In t e l XS ca le ® p r oc e sso r and t he hos t p r oce s sor . I n a ddi t i on to s imp le d ata t ran sf ers, th e A DMA pe rfo rms XO R o peratio ns w ith up to 1 6 so u rces . 2. 2. 4 Ad d r ess Tr a ns la tio n Un it The Ad dres s T r a n sla tio n Un it (A TU ) al lo ws P CI t ran sa ctio n s dire ct ac ce ss to t h e 8 1348 lo ca l m em ory . Th e A TU pro vid es in terfa ce fo r th e RAID C on tro ller PC I fu nc tio n. The A TU su ppo rts t ran sa ctio n s betw een P CI ad dres s spa ce an d t h e 8 1348 ad dres s spa ce . Ad dres s tr a n sla tio n is co ntro lle d th ro ug h p rog r a mm abl e reg is t e rs a cc es sib le from bo th t h e PCI in terfa ce an d t h e I n tel XS ca le ® p r oc es so r . D u al ac ce ss t o r e gi s t er s al l ows flex ibil it y in ma pp in g th e two a dd r e ss s pac es . The A TU al so s up po rt s th e fo ll ow in g exten de d c apa bil ity co n fig uratio n h ead ers: 1 . P owe r Ma na ge me nt hea d er , as de f i ne d b y PCI B u s P o we r Ma n age men t In t e rfac e Sp eci fic atio n , Revis io n 1 . 1. 2. Mes s age Si gn al ed In terru pt ca pa bil it y stru ctu re, as s pec ifie d in P CI Lo ca l B us Sp eci fic atio n , Revis io n 2 . 3. 3. PCI- X Ca pab ili t i es L i st Item, a s s pe cif ied in the PCI-X A dde nd um to t h e L o c al Bu s Sp eci fic atio n , Revis io n 1 . 0b.

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 13 Fea ture s—Intel ® 8 134 8 2. 2. 5 M es s agi ng U n it T he Me ss ag i ng Uni t ( M U) p r ov i d es da t a t r a nsf e r be t w ee n t h e P C I sy st em and t he 813 48. It us es in t e rru pts to n otify ea ch sy stem wh e n n ew d ata arrives . Th e M U h as fo u r mes s agi ng me ch an is ms : Me ss ag e R e gis t e rs, Do orb ell R eg isters , Circ ul ar Q ue ue s, a nd I nd ex R eg i st er s . Ea ch a l lo ws a hos t pr o ce ss or or e xt er n al PC I d ev i ce an d t he 8 1 3 4 8 t o c om mun ic at e t hr oug h m e ss ag e p as si ng an d i nt er r u pt g e ne r a t i on. T he MU , i n c onj u nct io n wi t h t he A T U , e x is t s as t he PC I i nt e r f ac e f or P C I f unc t i on 0 w he n f unc t i on 0 is se t up as a RAID c on tro lle r . 2. 2. 6 DDR2 M em or y C o nt ro ll er Th e DDR2 M emo ry C on trol ler a llo w s direc t co n trol of the 40 0/533 MH z DDR2 S DRAM m em or y su bs y st e m . I t f e at u r es pr og r am ma b le ch ip se l ec t s and su pp or t f or e r r or - co rrec tio n c o des (ECC ). Th e DDR2 Mem o ry Co ntro lle r i s m ul t i -po rt e d w ith th e fo llo w in g i nt e r f ac e s: so ut h i nt er na l bus , A D MA c ont r ol le r s , nor t h in t e r nal b us. T he m e mor y c ont r o ll e r in t e r fa ce co nf ig ur a t i on su pp or t i nc l ud es unb uf f e r ed D I M Ms, r eg i st e r e d DIMM s, a nd dis cre t e DDR2 SDRA M devi ce s. 2 .2 .7 SR A M Me mor y Con tr ol le r Th e S RAM M em ory Con tro lle r all ow s dire ct c on tro l o f a 1.0 M By t e S RAM me mo ry su bs ys t e m. It su pp orts erro r co rre ctio n co de s (E CC). Th e S RA M M em ory Co ntro lle r is po rted with th e fo ll ow in g p ort: No rth in t e rna l b us . 2. 2. 8 P eri phe ral Bu s I nt e rf ace Th e Perip h er a l B us In t e rfac e U n it is a d ata co mm un ic atio n pa th t o th e fl as h mem ory co m po ne nts o r oth er p erip he r a ls o f a 81348 h a rdwa re s ys t e m. Th e P BI i nc lu des su pp o rt f or eith er 8- o r 16-bit d evic es . T o p erfo rm t h es e ta sks at h ig h ban dw id t h , the b us f e at u r es a bur s t - t r an sf e r c ap ab i l it y w hi ch al l ow s suc ce s si v e 8 / 1 6 - bi t d at a t r ans f er s . 2. 2. 9 I 2 C Bu s I nt e rf ac e U n it s Th ere are t h ree I 2 C (Inter-I n tegrated Circ ui t ) Bu s I n terfa ce Un its tha t all ow th e In t e l XS ca l e ® pro c ess o r to s erve as a m as ter a nd sl ave d evic e re sid in g o n the I 2 C bu s. Th e I 2 C0 al lo ws the I/O p roc es so r to in terfa ce t o a sto r a ge en clo s ure pro ce ss or , S EP . Fo r mo re in form atio n , refer t o I 2 C P eri ph eral s f or Mic ro co n t ro ll ers (Ph ili ps S emi co n du cto r) 1 . 2. 2. 10 U AR T U nit s Th e 8134 8 inc lu de s tw o U AR T un its . Th e UAR T un it a llo w the two In t e l XS ca l e ® pro ce ss ors to se rv e as a ma ster a n d s lave devi ce resi din g on th e UA R T bu s . Th e UA R T u n its u s e a se rial bu s co ns is ting o f a two -pi n i nterf ac e. UA R T0 all ow s t h e 813 48 to in terfa ce t o a co n so le po rt fo r de bu ggi ng . A ls o refe r to th e Na tio na l S emi co n du cto r* 1 6550 dev ice sp ec ific atio n 2 . 1. h tt p ://ww w . se mic o nd uc tors . ph ilip s. co m /bu ses /i2c/ 2. h tt p ://ww w . n atio n al. co m /pf/P C/PC 1 6550D .h tml

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1. 2. 11 Inter r u p t Co ntr ol l er U ni t Ea ch In t e l X Sc al e ® p r oce ss or s upp or t s an I nt e r r up t C on t r ol l er U ni t ( I C U) . Th e I CU a g gr e g at e s i nt er r u pt s our c e s b ot h e x t e r nal an d i nt e r na l sou r ce s of t h e 8 1348 to t h e I n tel X S ca le ® p ro ces so r . The ICU s u ppo rts h ig h-p erfo rma n ce in t e rrup t p r oc e ssi n g w it h d ir e ct in t e r r up t se r v i ce r out in e v e c t or g e ner a t i on on a p e r - s our c e b as i s. E ac h so ur ce ha s p r og r a mm ab i l it y f or m as k in g, pr oc e ss or in t e r r up t in pu t , a nd p r i or i t y . 2. 2. 12 X SI Sy stem Con tro ll e r E ac h XS I bu s ( nor t h an d s out h ) e m pl o ys an X SI s y st e m c ont r ol le r . Th e X SI s ys t e m co n t ro ll er o bs erves al l the ad dres s or data bu s requ es t s fro m requ es tors a nd c om pl e t or s con ne ct e d t o t he XS I bu s. T h e XS I sy s t e m co nt r o ll e r han dl e s XS I ad d r es s b us a r bi t r at io n, XSI da t a b us ar b i t r a t i on , f r am in g Ad dr e s s b us cy cl e s, and f r am i ng D a t a bu s c ycle s. Th e X S I sys tem c o ntro lle r pro vide s th e s h ared ad dres s an d s h ared da ta p a t hs f r om / t o u ni t s. 2. 2. 13 Inter -P ro c ess or C omm un i c ati on Ea ch Intel XS ca le ® p roc es so r ca n i nterru pt o r iss u e a re set to th e s eco n d In t e l XS c ale ® p r oc e sso r . E ac h pr o ce ss or ca n g en er at e u p t o 3 2 in t er r u pt s t o t he s e con d p r oc es sor . 2. 2. 14 Tim er s The 813 48 su pp orts two pro g r am ma ble 32 -b it time rs p er p roc es so r . Th e 81 348 al so su ppo rts on e watc hd og time r pe r pro ce ss or . 2. 2. 15 GPIO The 813 48 i n c lu des si xteen Ge ne r al -Pu rpo se I/O (GP IO) p in s, a nd eig ht A CTIV I TY/ S T A TU S p i n pa i r s.

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 15 Pa ck age In f ormat ion —Inte l ® 81 348 3 .0 Package In form at ion

3.1 Package I n troduction

Th e 8134 8 is o ff ered in a 1 357-ba ll F CB GA5 p ac kag e.

3.2 F unctional Sign a l D e fin i t io n s

T hi s s ec t i on d e f in es t he pi ns and si g na ls . 3. 2. 1 S igna l P in De scr ipt i on s T able 1 . Pin Descript i o n No m e n clatu re Symbol De scr i p tion I I npu t pi n on l y O Outp ut pi n o n l y I/O Pi n ca n be ei t he r a n i n put or a n o u tpu t OD Open- drai n pi n P WR P ower pi n G N D Gr o u nd pi n — Pi n mu st be con nect ed as descr i bed Sync( . ..) S yn chr o n ous. Si gn al m eet s t i mi ng s re l at i ve t o a c l o ck .

• Sync( P): S y nch ronous to P_CL KIN
• Sync( M): S y nch ronous to M_ CK [ 2 : 0 ] / M _CK# [ 2:0 ]
• Sync( T): Sync hron o u s t o TC K As ync Async hron o u s. I npu ts can be as ynch ronou s re l at i ve t o al l c l o ck s. Al l asy nch ronous si gna l s ar e l eve l -se nsi t i ve. R / W In d ic a t e s r e a d o r w r it e c a p a b ilit y . Rst (P ) The pi n i s re set wi th WA RM _ RST# or P_ R S T # . Rst( M) The p i n i s r ese t wi t h M_ R S T # . M_RST # i s a sser te d whe n t he mem o r y su bsyst em i s re set . Rst (P B) The pi n i s re set wi th PB_RS TOUT# . PB_RS TOUT# i s a sse rt ed wh en the Per i phe ral Bu s I nt er face su bsyst em i s r ese t. Rst (T) The pi n i s re set wi th TR ST# . Act Low The pi n i s an ac ti ve- l o w s i gna l . Di f f The pi n i s a di ffe ren ti a l si gn al p ai r .
• “P ” at th e e nd o f a di ffer en ti a l pi n na me i ndi ca te s “p o si t i ve” .
• “N” at t he end o f a di ffe ren ti a l pi n na me i ndi ca te s “ neg at i ve ” .

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Table 2 . DDR2 S DRA M Sign als (S heet 1 of 2) N a me Count Type De scrip tion M _CK[2: 0] , M _CK#[2:0 ] 6 O Di f f Me mory Cl ocko u t: i s u sed to pr o vi de t he thr ee di ffe re nt i a l cl ock pa i r s t o th e u nbu ffe red DI M M for t he ex ter na l SDR A M m emory sub syst em. R e gi st ere d DI M M s use o n l y th e M_ C K[ 0 ] / M _CK# [ 0] pa i r , w h i ch dri ve s t he i npu t t o th e on- DI M M PLL . M_ R S T # 1 O Asyn c ActL o w Mem o ry Rese t: i ndi ca te s t hat t he mem o r y su bsys tem ha s b een re set . I t i s us ed t o re- i ni t i al i ze reg i ste red DI M M s. M A [14: 0] a 14 O Sync (M) Rst (M ) M e mor y A d d r e s s B u s : c a r r ie s t h e m u lt ip le x e d r o w a n d c olu m n ad dres ses to th e SD RAM mem ory b an ks. Auto-pr ech ar ge i s not sup po r te d. BA[2: 0] 3 O Sync (M) Rst (M ) SDRAM Ban k Addr ess : cont rol s whi ch o f th e i nt er na l ban ks t o r ea d or wri t e. BA[1 :0] ar e u sed for 5 12 M bi t tec hnol ogy m emor y . BA[ 2:0] ar e u sed fo r 1 Gb i t t ech nol ogy m emory . RAS # 1 O Sync (M) Rst (M ) ActL o w SDRAM R ow Add res s St robe: i n di ca tes t he pr ese nce of a val i d r o w ad dres s on t he Mu l ti pl e xed Add res s Bus MA[13 :0] . CAS# 1 O Sync (M) Rst (M ) ActL o w SDRAM C o l u mn Addre ss St robe: i ndi ca te s t he pre sen ce of a val i d col umn a ddre ss on th e M ul t i pl exed Addre ss Bu s M A [13: 0] . WE# 1 O Sync (M) Rst (M ) ActL o w SDRAM W r i te Ena bl e: i ndi c at es wh eth er th e c urr en t m emor y tra nsa ct i on i s a re ad o r wri t e ope r a ti on . CS[1: 0]# 2 O Sync (M) Rst (M ) ActL o w SDRAM C hi p Se l ect : en abl e s t he SDRAM de vi ces for a me mory ac cess. On e for ea ch physi ca l ba nk. CK E[1 :0] 2 O Sync (M) Rst (M ) SDRAM C l o ck En abl e en abl e s: t he cl ocks f o r t he SDRAM me mory . De ass ert i ng pl ace s t he SDRAM i n sel f-re fre sh mode. One for eac h p h y si c a l ba nk . DQ[63 :0] 64 I/ O Sync (M) Rst (M ) SDRAM D at a Bus: ca rr i es 64 -bi t da ta t o an d f rom mem o r y . D ur i ng th e d at a cyc l e, re ad or wri t e da ta i s p rese nt on one or m o r e cont i guous byt es. Du ri n g wri t e opera ti ons , u nu sed pi ns dri ve to d e te rm i n at e v a l ue s . CB [ 7:0 ] 8 I/ O Sync (M) Rst (M ) SDRAM E CC Che ck Bi t s: c arr y t he 8- bi t E CC code t o an d fr o m me mory d ur i n g da ta cycl e s. DQS[8 :0] , DQS#[8: 0] 18 I/ O Sync (M) Rst (M ) Di f f SDRAM D at a St robes : ca rr y di ff ere nt i al or si ng l e -en ded str obe si gn al s, out put i n w r i te mode, a nd i npu t i n re ad mode f o r sour ce syn chr o n ous d at a t ran sfer . DM [8: 0] 9 O Sync (M) Rst (M ) SDRAM D at a Ma sk: cont rol s whi c h b yte s on th e d at a b us ar e t o be wri t ten . W h en DM [8 :0] i s a sser te d, the SDR AM d evi ce s do n o t ac cept val i d d at a f rom t he byt e l a nes . M_ V R E F 1I SDRAM V o l t age Refe ren ce: i s u sed to su ppl y t he i npu t swi t ch i ng re fer enc e vol ta ge for t he mem o r y i n put si gn al s. ODT[1: 0] 2 O Sync (M) Rst (M ) O n - D ie T e r m in a t ion : is u s e d t o t u r n o n S D R A M on - d ie t e r m in a t ion dur i ng wri te s.

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 17 Pa ck age In f ormat ion —Inte l ® 81 348 M_CAL[0] 1O M emor y Ca l i brat i on: C o n ne cte d t o a n ext ern al cal i bra ti on res i stor . M emor y out put dr i vers re fer enc e t he re si stor to dy na mi ca l l y a djust dr i ve s tre ngt h to compe nsa te for t em perat ur e a nd vo l t age var i at i o n s. Thi s pi n c o n ne cte d th rough a 24 .9 Ω 1 % re si st o r to gr o u nd. M_CAL[1] 1O M emor y Ca l i brat i on: C o n ne cte d t o a n ext ern al cal i bra ti on res i stor . M emor y out put dr i vers re fer enc e t he re si stor to dy na mi ca l l y a djust ODT r esi st an ce t o compen sa te for t emp erat ur e a nd vo l t age var i at i o n s. Thi s pi n c o n ne cte d th rough a 30 1 Ω 1 % r esi s tor t o gr o u nd. To t a l 1 3 5 a. MA[ 14 ] i s o n l y n eede d for 4G B m e mo ry supp o r t. Wh en 4G B me mory i s not use d t hi s p i n i s N C . T able 2 . DDR2 SDR AM S ignals ( Sh eet 2 o f 2 ) Name Count Type D escr iption

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Table 3 . Per i p her al B us In terface Sign als N a me Coun t Type Desc ript ion A[2 4:0] 25 O Rst (PB) Peri ph era l Addr ess Bu s: car ri es th e a ddr ess b i ts f o r t he cur ren t acc ess. The P BI i nt er fa ce ca n addr ess up to 3 2 M Byt es. D[15: 0] 16 I/ O Rst (PB) Peri ph era l Da ta Bus : ca rr i es r ea d or wr i te dat a to a nd f rom mem o r y . Dur i ng wri t e operat i ons to 8-b i t wi de mem o r y re gi o n s, t he PBI dri ve s un use d bu s pi n s t o det erm i na te v a l ue s. PO E # 1 O Rst (PB) Act Lo w P e r ip h e r a l O u t p u t E n a b le : in d ic a t e s w h e t h e r b u s a c c e s s is w r it e or rea d wi t h r espe ct to I / O proces sor a nd i s val i d d uri n g e nti r e bus acc ess. Thi s pi n can be use d t o c o n tr o l o u tpu t e na bl e on a per i phe r a l de vi ce. 0 = R ea d 1 = W r i te PW E # 1 O Rst (PB) Act Lo w P e r ip h e r a l Wr it e E n a b le : in d ic a t e s t o t h e p e r ip h e r a l d e v ic e w h e t h e r o r not to wr i te dat a to t he addr ess ed sp ace . T h i s p i n ca n be u sed to contr ol th e wr i te ena bl e o n th e p eri p hera l dev i ce. 0 = W r i te 1 = R ea d P CE[ 1:0] # 2 O Rst (PB) Act Lo w P e r ip h e r a l C h ip E n a b le : S p e c if ie s w h ic h of t h e t w o m e m o r y a d d r e s s ran ges ar e ass o ci a te d wi t h th e cur ren t bus a cces s. The pi n r em ai ns v a l i d du ri n g th e e nt i re bus acc ess. No t e : Thes e pi n s m ust be pu l l ed up to V CC3 P3 wi t h ext er na l 8 . 2 K Ω 5% , 1/ 1 6 Ω r es i stors for p roper o p erat i on. P B_R STOU T# 1 O Act Lo w Peri ph era l Bus R e set Out : ca n b e u sed to re set t he peri p hera l devi c e. I t ha s t he sam e t i mi ng as th e i n ter na l bu s r eset . To t a l 4 6

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 19 Pa ck age In f ormat ion —Inte l ® 81 348 T able 4 . Co mp act PCI H ot S w ap Sign als Name Count Type De scrip tion HS_ ENUM# 1 OD Rst (P) ActL o w Hot Swap E ven t: Condi t i o n al l y ass ert ed to noti f y sys tem h o st t hat e i the r a board ha s bee n fr esh l y i ns ert ed or i s about to be e xt r a ct ed. Th i s si gn al i n form s th e s yste m h ost t ha t the conf i gura ti on of the sy ste m h as ch an ged. Th e syst em host t he n perf o r ms an y n ece ssar y m a in t e n a n c e s u c h a s in s t a llin g o r q u ie s in g a d e v ic e d r iv e r . HS_ L ST AT 1 I Rst (P) Hot Swap L at ch S t at us : I n put i nd i c at i ng s ta te o f th e e ject o r swi t ch. 0 = I n di cat es th e e ject o r swi tc h i s cl osed. 1 = I n di cat es th e e ject o r swi tc h i s o p en. I f Compa ct PC I Hot Swap not s upport ed, t i e t hi s si gna l l ow . HS_ L ED_O UT 1 O Rst (P) H o t S w a p L E D O u t p u t : o u t p u t s a lo g ic o n e t o illu m in a t e t h e H o t Sw a p bl u e L ED. H S _F R E Q [ 1: 0 ] CR _FREQ[ 1:0 ]

2 I/ O

Rst (P) Hot Swap Fr equ enc y: In Hot Swap mode, th ese pi ns ar e i n put s, de ter mi n i ng t he bu s fr equ enc y a nd m o d e du ri n g a PC I - X hot sw a p ev en t. T h e se ar e v al i d o n l y w h e n PCIX _ EP # =0 a n d H S _SM# =0 . 0 0 = 1 3 3 M H z P C I-X 0 1 = 1 0 0 M H z P C I-X 1 0 = 66 MHz PC I -X 1 1 = 33 o r 6 6 M Hz. P CI ( fre que ncy depe nds o n P_M 6 6EN ) Ce nt ral Resou rce Frequ en cy: W h i l e i n Ce nt ral Resour ce mode, t hes e pi n s a re o u tpu ts , wh i ch c o n tr o l the ex ter na l P CI - X cl ock ge nera tor . Th ese ar e val i d o n l y wh en PCIX_EP# =1 . 00 = 133 MHz 01 = 10 0 MH z 10 = 66 M H z 11 = 33 M H z

• Thes e pi n s h ave i n te rn al pu l l -up s. To t a l 5

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Table 5 . PCI B u s Sign als (Sh eet 1 o f 3) N a me Coun t Type Des crip tion P_ A D [ 6 3 : 3 2 ] 32 I/O Sync(P) Rst(P) PCI Add res s/Da ta : i s th e upp er 3 2 bi ts of t he P CI da ta b us dri ve n dur i n g t he dat a pha se. P_ A D [ 3 1 : 0 ] 32 I/O Sync(P) Rst(P) PCI Addr ess/D at a: i s t he mu l ti pl exe d P CI a ddr ess an d l ow e r 3 2 bi ts o f th e da ta bu s. P _ CB E [7]# 1 I/O Sync(P) Rst(P) ActLow PCI Bus Comma nd an d Byt e E na bl es: ar e m ul t i pl exed o n th e sam e P CI pi ns. D uri n g t he add ress pha se, t he y de fi ne th e b us co m ma nd. Du ri n g t he dat a p ha se, th ey ar e u sed as b yte ena bl es . P _ CB E [6]# 1 I/O Sync(P) Rst(P) ActLow PCI Bus Comma nd an d Byt e E na bl es: ar e m ul t i pl exed o n th e sam e P CI pi ns. D uri n g t he add ress pha se, t he y de fi ne th e b us co m ma nd. Du ri n g t he dat a p ha se, th ey ar e u sed as b yte ena bl es . P _ CB E [5]# 1 I/O Sync(P) Rst(P) ActLow PCI Bus Comma nd an d Byt e E na bl es: ar e m ul t i pl exed o n th e sam e P CI pi ns. D uri n g t he add ress pha se, t he y de fi ne th e b us co m ma nd. Du ri n g t he dat a p ha se, th ey ar e u sed as b yte ena bl es . P _ CB E [4]# 1 I/O Sync(P) Rst(P) ActLow PCI Bus Comma nd an d Byt e E na bl es: ar e m ul t i pl exed o n th e sam e P CI pi ns. D uri n g t he add ress pha se, t he y de fi ne th e b us co m ma nd. Du ri n g t he dat a p ha se, th ey ar e u sed as b yte ena bl es . P _ CB E [3]# 1 I/O Sync(P) Rst(P) ActLow PCI Bus Comma nd an d Byt e E na bl es: ar e m ul t i pl exed o n th e sam e P CI pi ns. D uri n g t he add ress pha se, t he y de fi ne th e b us co m ma nd. Du ri n g t he dat a p ha se, th ey ar e u sed as b yte ena bl es . P _ CB E [2]# 1 I/O Sync(P) Rst(P) ActLow PCI Bus Comma nd an d Byt e E na bl es: ar e m ul t i pl exed o n th e sam e P CI pi ns. D uri n g t he add ress pha se, t he y de fi ne th e b us co m ma nd. Du ri n g t he dat a p ha se, th ey ar e u sed as b yte ena bl es . P _ CB E [1]# 1 I/O Sync(P) Rst(P) ActLow PCI Bus Comma nd an d Byt e E na bl es: ar e m ul t i pl exed o n th e sam e P CI pi ns. D uri n g t he add ress pha se, t he y de fi ne th e b us co m ma nd. Du ri n g t he dat a p ha se, th ey ar e u sed as b yte ena bl es . P _ CB E [0]# 1 I/O Sync(P) Rst(P) ActLow PCI Bus Comma nd an d Byt e E na bl es: ar e m ul t i pl exed o n th e sam e P CI pi ns. D uri n g t he add ress pha se, t he y de fi ne th e b us co m ma nd. Du ri n g t he dat a p ha se, th ey ar e u sed as b yte ena bl es . P_ PA R 6 4 1 I/O Sync(P) Rst(P) PCI Bus Uppe r D W ORD Pa ri ty i s e ven par i ty a cr o ss P_A D[63: 32] an d P _CBE _ #[7 :4 ] . P_ R E Q 6 4 # 1 I/O Sync(P) Rst(P) ActLow PCI Bus Requ est 64 -Bi t T ra nsf er i n di ca te s th e at te mpt o f a 6 4-b i t tran sac ti on on th e P CI bus. Wh en th e t ar get i s 6 4-b i t ca pa bl e, the ta rg et ack now l e dges th e a tt em pt wi t h t he as sert i on of P_ A C K6 4_ #. P _ ACK64# 1 I/O Sync(P) Rst(P) ActLow PCI Bus Acknowl edg e 6 4-Bi t T ra nsfe r i ndi ca te s th at t he devi c e has posi ti ve l y de co d ed i t s a ddre ss a s t he ta rge t of th e cu rr ent a c c e s s a n d t h e t a r g e t is w illin g t o t r a n s f e r d a t a u s in g t h e f u ll 6 4 - bi t da ta bu s.

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 21 Pa ck age In f ormat ion —Inte l ® 81 348 P_PAR 1 I/O Sync(P) Rst(P) PC I Bu s Par i ty i s eve n p ar i t y a cross P_A D[31: 0] a nd P_ CBE _#[3 :0] . P_FR AM E # 1 I/O Sync(P) Rst(P) ActLow PC I Bu s Cyc l e Fram e i s asse rt ed t o i ndi c at e t he begi n ni n g an d dura ti on o f an ac cess . P_IR DY # 1 I/O Sync(P) Rst(P) ActLow P C I B u s In it ia t o r Re a d y in d ic a t e s t h e i n it ia t in g a g e n t ’s a b ilit y t o compl et e the cu rr ent da ta ph ase o f th e t ran sac ti on. D uri n g a w r it e , it in d ic a t e s t h a t v a lid d a t a is p r e s e n t o n t h e a d d r e s s / d a t a bus . D ur i ng a r ea d, i t i n di cat es th at th e p rocess o r i s r ea dy t o ac cept th e d at a. P_TR DY # 1 I/O Sync(P) Rst(P) ActLow P C I B u s T a r g e t Re a d y in d ic a t e s t h e t a r g e t a g e n t ’ s a b ilit y t o compl et e the cu rr ent da ta ph ase o f th e t ran sac ti on. D uri n g a re ad, i t i ndi c ate s t ha t va l i d da ta i s pr ese nt o n t he addr ess /dat a bus . D ur i ng a wri t e, i t i n di ca te s th at th e t ar get i s r ead y to a cce pt th e da ta . P_S TOP# 1 I/O Sync(P) Rst(P) ActLow PC I Bu s Stop i n di ca te s a re ques t t o stop t he cu rre nt tra nsa ct i o n on t he PC I bu s. P_DEVSEL# 1 I/O Sync(P) Rst(P) ActLow PC I Bu s D evi ce Sel ec t i s dri ve n by a ta rge t a gen t t ha t ha s suc cessf ul l y decoded th e a ddr ess. As a n i npu t, i t i ndi ca te s whet he r or not an age nt ha s be en sel e cte d. P_S ERR# 1 I/O OD Sync(P) Rst(P) ActLow PC I Bu s Syste m E rr o r i s d ri ven for addr ess par i ty err ors on th e PC I bu s. P_R STOU T# 1 O Async ActLow PC I Reset Out i s ba sed on P_R ST# a nd WARM_RS T# . I t br i ngs PC I -spec i fi c r egi st er s, sequ enc ers , a nd si gn al s t o a co n si st ent s t at e. W he n e i th er P_ R S T # or WARM_RS T# is a s s e r t e d , it ca uses P_RS TOUT# to a sse rt an d:

• P CI o u tpu t si gna l s a re dri ve n t o a known c o n si ste nt st at e.
• P CI bus i nt erf ace out put si gn al s a re th re e-st at ed.
• Ope n-d r a i n si gna l s su ch as P_ SERR _# a re fl oat ed. P_RS TOUT # ca n be a sync hron o u s t o P _ CLK w h en ass ert ed o r dea sse rte d. P_PERR # 1 I/O Sync(P) Rst(P) ActLow PC I Bu s Par i ty Err or i s ass ert ed w h en a dat a p ar i ty e rr o r occur s dur i ng a P CI bus tra nsa cti on . P_M66EN 1 I PC I Bu s 66 M Hz En abl e i ndi c at es t he spee d of th e P CI bus. Whe n th i s si gn al i s sa mpl ed hi gh , th e P CI bus spee d i s 6 6 MHz; whe n l o w , t he bus spee d i s 3 3 MHz. P_IDS EL 1 I Sync(P) P C I B u s In it ia liz a t io n D e v ic e S e le c t is u s e d t o s e le c t t h e 8 1 3 4 8 dur i ng a c o n fi gura ti on rea d or wri te . No t e: I n cen tra l re so u rc e mode th i s pi n mu st be p ul l ed dow n to V SS wi th an ex ter na l 4.7 K Ω 5 % , 1/ 16 Ω re si st o r for prope r opera ti on. T able 5 . PC I Bu s S i g nals (S heet 2 o f 3) Name Count Ty p e De scr iption

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P_ G N T [ 0 ] # / P_ R E Q # 1 O Sync(P) ActLow PCI Bus Gra nt :

• I n te rna l a rbi t er mode: Thi s i s one o f four o u tp ut gran t si gn al s from the i nt er na l ar bi te r . PCI Bus R e que st:
• Ex ter na l a rbi t er mode: Thi s i s th e out put r equ est si gn al f o r th e A TU. P_ R E Q [ 0 ] # / P_ G N T # 1 I Sync(P) Rst(P) ActLow PCI Bus R e que st:
• I n te rna l a rbi t er mode: Thi s i s one o f four i npu t r equ est si gn al s to t he i nte rn al a rbi t er . PCI Bus Gra nt :
• Ex ter na l a rbi t er mode: Thi s i s th e i n put gra nt si gna l t o the AT U . P_ G N T [ 3 : 1 ] # 3 O Sync(P) ActLow PCI Bus Gra nt :
• Ex ter na l a rbi t er mode: N ot use d
• I n te rna l a rbi t er mode: Thes e a re th ree of fou r out put gra nt si gn al s from the i nt er na l ar bi te r . P_ R E Q [ 3 : 1 ] # 3 I Sync(P) Rst(P) ActLow PCI Bus R e que st:
• Ex ter na l a rbi t er mode: N ot use d
• I n te rna l ar bi te r m o d e: Th ese are th re e of four i np ut requ est si gn al s to t he i nte rn al a rbi t er . P_ PC I X C A P 1 I P C I-X C a p a b ilit y : R e f e r t o t h e In te l ® 81 34 8 I /O P ro ce s s o r S p ecifica tion Upda te for more det ai l s. P_ BM I 1 O Sync(P) Rst(P) PCI Bus Ma ste r Indi ca tor i ndi ca te s t ha t t he I /O process o r i s mas ter i ng a t ran sact i on on th e P CI bus. P _ CAL [ 0] 1 O P C I C a lib r a t ion is c on n e c t e d t o a n e x t e r n a l c a lib r a t io n r e s is t o r . Th e V CC VIO PC I out put dr i ver s re fer en ce t he re si stor to dyna mi ca l l y a djus t t he dri ve st ren gth t o c o m pen sat e f o r vol ta ge and te mpera tu re vari a ti ons . Th i s pi n i s c o n ne cte d th roug h a 22 . 1 Ω 1% res i stor to gr o u nd. P _ CAL [ 1] 1 O P C I C a lib r a t ion is c on n e c t e d t o a n e x t e r n a l c a lib r a t io n r e s is t o r . T h e P CI outp ut dri ve rs r ef ere nce th e r esi s tor t o dyn ami c al l y adju st t he ODT re si sta nc e t o co m pen sat e f o r vol ta ge a nd tem pera tur e v a ri a ti ons. Th i s pi n i s conn ect ed th rough a 12 1 Ω 1% res i stor to gr o u nd. P _ CAL [ 2] 1 O P C I C a lib r a t ion is c on n e c t e d t o a n e x t e r n a l c a lib r a t io n r e s is t o r . Th e V CC 3 P3 PC I out put dr i vers re fer enc e t he re si stor to dyna mi ca l l y a djus t t he dri ve st ren gth t o c o m pen sat e f o r vol ta ge and te mpera tu re vari a ti ons . Th i s pi n i s c o n ne cte d th roug h a 22 . 1 Ω 1% res i stor to gr o u nd. P_ C LK I N 1 I PCI Bus I np ut Cl ock p ro v i des the AC ti mi n g r efe ren ce fo r a l l PC I tran sac ti ons. P_ C LK O U T 1 O PCI Bus Out put Cl ock: When REFCLK N / RE F C L K P ar e u sed, t he I /O pr o c essor can gen era te th e P CI o u tpu t cl o c ks. Thi s pi n i s the n c o n ne cte d to P_ C LK I N a nd trac e l e ngt h m at che d to P_CLK O [3:0 ] . P_ C LK O [ 3 : 0 ] 4 O PCI Bu s Outp ut C l ock s: W h en REFCL KN / REFCLK P ar e use d, t he I /O pr o c essor can gen era te th e P CI o u tpu t cl o c ks. The se pi n s t h en pr o vi d e th e PC I cl o c ks t o de v i c es o n th e PC I b us . To t a l 1 0 5 Table 5 . PCI B u s Sign als (Sh eet 3 o f 3) N a me Coun t Type Des crip tion

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 23 Pa ck age In f ormat ion —Inte l ® 81 348 T able 6 . PC I Exp ress Sign al s N a me Coun t Type Descr ipt i on RE F C L K P , RE F C L K N 2 I Di f f PCI Ex pre ss* C l o c k i s th e 10 0 MHz d i ffer en ti a l i n put re fer en ce cl ock for t he PC I E xpre ss* i nt erf ace . PETP[7: 0] , PETN [7:0 ] 16 O Di f f PCI Ex pre ss* T ra nsm i t car ri e s the di ffe ren ti a l ou tpu t ser i al da ta a nd embe dded cl ock f o r th e P CI Exp res s* i n te rfa ce. PERP[7 :0] , PERN [7:0 ] 16 I Di f f PCI Ex pre ss* R e cei ve car ri e s th e d i ffer en ti a l i npu t ser i al da ta a nd embe dded cl ock f o r th e P CI Exp res s* i n te rfa ce. PE_CA L P , PE_CA L N 2 I/O PCI Ex pre ss* Ca l i b rati on pi ns ar e c o n nec ted to a n e xte rn al cal i bra ti on res i stor . The P CI E xpr ess* out put dr i ve rs can re fer en ce th e r esi st o r t o dyna mi ca l l y a djus t t he i r sl e w rat e a nd dri ve st ren gth to compe nsa te for vol t age an d t empe rat ur e var i at i o n s. A 1 . 4 K Ω 1% res i stor i s conn ect ed betwe en th ese two pi n s. To t a l 3 6

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Table 7 . Sto r age I n terface Sign als (S heet 1 o f 3) N a me Coun t Typ e Des cript ion S_CLK N 0 , S_CLK P0 2 I Di f f Storage Cl o c k i s t he 1 25 M Hz ± 1 00 pp m di ffe ren ti a l i n put ref ere nce cl ock f o r th e i n te rfa ce. No t e : Shoul d be AC coupl e d wi th a 10 0n F cap aci t o r . S_TXP[7: 0] , S_TXN [7:0 ] 16 O Di f f Storage T ra nsmi t ca rr i es t he di ff ere nt i al out pu t se ri a l da ta an d em bedde d cl ock fo r t he i nt erf ace . No t e : Shoul d be AC coupl e d wi th a 10 nF ca pa ci tor . S_R X P[7: 0] , S_R X N [7:0 ] 16 I Di f f Storage Recei ve ca rr i es t he di ffe re nt i al i n put ser i al dat a a nd em bedde d cl ock fo r t he i nt erf ace . No t e : Shoul d be AC coupl e d wi th a 10 nF ca pa ci tor . R B I A S[ 1 : 0] 2O R e si st o r Bi as : A 6 . 4 9K Ω 1% 1/ 8 Ω e xt ern al res i stor must be conn ect ed be twee n t hi s pi n an d grou nd f o r pr o pe r ope rat i o n . Th i s re si stor gen erat es i nt ern al bi as cur ren ts . RBIAS _SEN SE[ 1:0 ] 2I / O R e si st o r Bi as Sens e i s use d i nt er na l l y t o s ens e gr o u nd. Th i s ba l l mu st b e con nect ed to t he sam e ph ysi ca l groun d poi n t a s t he RBIA S[1 :0] re si st o r i s con nec ted to on the P CB. S_A CT0 / SCL O CK 0 1O D Storage Act i vi ty: When SG PI O[ 0] i s di sa bl ed, t hi s pi n c an be u sed to dr i ve a n LED to i n di cat e act i vi ty o n t he l i nk f o r st o ra ge en gi ne [0]. Th e pi n ca n b e di r ect dr i ven by t he storag e e ngi n e or d r i v en fr o m an S GPI O . No t e : Conn ect th e L ED to a ser i es res i stor pul l ed up to VCC . S e r ia l C loc k : ( d e f a u lt ) W h e n S G P I O[ 0 ] is e n a b le d , t h is p in is t h e ser i al o u tpu t c l o ck ru nn i ng a t 99 . 8 KHz. Th e fa l l i ng edge of SCLOCK0 is u s e d t o la t c h SL O AD0 , S DATAO UT0 , a nd SDA TAIN 0 . S_S TAT0 / SLOAD0 1O D Storage Sta tu s: Wh en S G P I O[0 ] i s di s abl e d th i s pi n can be use d t o dri ve a n LED t o i nd i cat e sta tu s of th e l i n k for storage e ngi n e[0 ]. The pi n can be di re ct dri ven by th e st or a ge eng i ne o r dr i ven from an SGP I O. No t e : Conn ect th e L ED to a ser i es res i stor pul l ed up to VCC . S e r ia l L o a d : ( d e f a u lt ) W h e n S G P I O [ 0 ] is e n a b le d , t h is p in is t h e ser i al l oa d cl ock. I t i s dri ven h i gh t o i ndi ca te th e sta rt of th e bi t str ea m. S_A CT1 1O D Storage Act i vi ty: When SG PI O[ 0] i s di sa bl ed, t hi s pi n c an be u sed to dr i ve a n LED to i n di cat e act i vi ty o n t he l i nk f o r st o ra ge en gi ne [1]. Th e pi n ca n b e di r ect dr i ven by t he storag e e ngi n e or d r i v en fr o m an S GPI O . No t e : Conn ect th e L ED to a ser i es res i stor pul l ed up to VCC . S_S TAT1 1O D Storage Sta tu s: W h en SGP I O[0 ] i s di sa bl ed, t hi s p i n c an be used to dri ve a n LED t o i nd i cat e sta tu s of th e l i n k for storage e ngi n e[1 ]. The pi n can be di re ct dri ven by th e st or a ge eng i ne o r dr i ven from an SGP I O. No t e : Conn ect th e L ED to a ser i es res i stor pul l ed up to VCC . S_A CT2 / SDATA IN0 1O D Storage Act i vi ty: When SG PI O[ 0] i s di sa bl ed, t hi s pi n c an be u sed to dr i ve a n LED to i n di cat e act i vi ty o n t he l i nk f o r st o ra ge en gi ne [2]. Th e pi n ca n b e di r ect dr i ven by t he storag e e ngi n e or d r i v en fr o m an S GPI O . No t e : Conn ect th e L ED to a ser i es res i stor pul l ed up to VCC . Ser i al D at a In: (def aul t ) Wh en SGP I O[0 ] i s ena bl ed, t hi s pi n i s th e ser i al i n put da ta . Ther e a re th re e bi t s of d at a pe r devi ce a nd u p t o ei gh t d evi ce s a re supp o r ted . S_S TAT2 / SDATA OUT 0 1O D Storage Sta tu s: W h en SGP I O[0 ] i s di sa bl ed, t hi s p i n c an be used to dri ve a n LED t o i nd i cat e sta tu s of th e l i n k for storage e ngi n e[2 ]. The pi n can be di re ct dri ven by th e st or a ge eng i ne o r dr i ven from an SGP I O. No t e : Conn ect th e L ED to a ser i es res i stor pul l ed up to VCC . S e r ia l D a t a O u t : ( d e f a u lt ) W h e n S G P IO [ 0 ] is e n a b le d , t h is p in is t h e ser i al ou tpu t da ta . Ther e are t hre e bi t s of d at a pe r d evi ce an d u p to ei gh t d evi ce s a re supp o r ted .

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 25 Pa ck age In f ormat ion —Inte l ® 81 348 S_ A C T 3 1O D St o ra ge Act i vi ty : Whe n SG P I O[0] i s di s abl e d, thi s pi n can be use d t o dri ve an LE D t o i ndi ca te ac ti vi t y on t he l i nk for s torage e ngi n e[3 ]. The pi n c an be di rec t d ri ven by the st o ra ge engi n e or dr i ven from an SGP I O. Note: Con nec t t he LED t o a se ri e s re si st o r pu l l e d u p t o VC C. S _STA T3 1O D St o ra ge St at us: Whe n SG PIO [ 0] i s di sa bl ed , t hi s pi n can be use d t o dr i ve an LE D to i n di ca te st at us o f t he l i nk for st o ra ge eng i ne[ 3]. Th e pi n ca n be di r ect dri ve n b y th e storage en gi ne or dr i ven fr o m an SG PI O. Note: Con nec t t he LED t o a se ri e s re si st o r pu l l e d u p t o VC C. S_ A C T 4 / SC L O C K 1 1O D St o ra ge Act i vi ty : Whe n SG P I O[1] i s di s abl e d, thi s pi n can be use d t o dri ve an LE D t o i ndi ca te ac ti vi t y on t he l i nk for s torage e ngi n e[4 ]. The pi n c an be di rec t d ri ven by the st o ra ge engi n e or dr i ven from an SGP I O. Note: Con nec t t he LED t o a se ri e s re si st o r pu l l e d u p t o VC C. S e r ia l C lo c k : ( d e f a u lt ) W h e n SG P IO [ 1 ] is e n a b le d t h is p in is t h e s e r ia l o u t p u t c lo c k r u n n in g a t 9 9 . 8 K Hz . T h e f a llin g e d g e o f SCLOCK 1 is u s e d t o la t c h SLOAD1 , SDATA OUT1 and SDA TAIN 1 . S _STA T4 / SL O AD 1 1O D St o ra ge St at us: Whe n SG PIO [ 1] i s di sa bl ed , t hi s pi n can be use d t o dr i ve an LE D to i n di ca te st at us o f t he l i nk for st o ra ge eng i ne[ 4]. Th e pi n ca n be di r ect dri ve n b y th e storage en gi ne or dr i ven fr o m an SG PI O. Note: Con nec t t he LED t o a se ri e s re si st o r pu l l e d u p t o VC C. Ser i al Lo a d: (def aul t ) Wh en SGP I O[1 ] i s ena bl ed, t hi s pi n i s th e s er i al l o ad cl o c k. I t i s d r i v en hi g h t o i n di c a te th e s ta r t o f th e b i t st re am. S_ A C T 5 1O D St o ra ge Act i vi ty : Whe n SG P I O[1] i s di s abl e d, thi s pi n can be use d t o dri ve an LE D t o i ndi ca te ac ti vi t y on t he l i nk for s torage e ngi n e[5 ]. The pi n c an be di rec t d ri ven by the st o ra ge engi n e or dr i ven from an SGP I O. Note: Con nec t t he LED t o a se ri e s re si st o r pu l l e d u p t o VC C. S _STA T5 1O D St o ra ge St at us: Whe n SG PIO [ 1] i s di sa bl ed , t hi s pi n can be use d t o dr i ve an LE D to i n di ca te st at us o f t he l i nk for st o ra ge eng i ne[ 5]. Th e pi n ca n be di r ect dri ve n b y th e storage en gi ne or dr i ven fr o m an SG PI O. Note: Con nec t t he LED t o a se ri e s re si st o r pu l l e d u p t o VC C. S_ A C T 6 / S DATAI N1 1O D St o ra ge Act i vi ty : Whe n SG P I O[1] i s di s abl e d, thi s pi n can be use d t o dri ve an LE D t o i ndi ca te ac ti vi t y on t he l i nk for s torage e ngi n e[6 ]. The pi n c an be di rec t d ri ven by the st o ra ge engi n e or dr i ven from an SGP I O. Note: Con nec t t he LED t o a se ri e s re si st o r pu l l e d u p t o VC C. Ser i al Da ta I n: (de fau l t) When SG PI O[1 ] i s en abl e d, th i s pi n i s t he se ri a l i npu t dat a. The re ar e t hr ee bi ts o f dat a per dev i ce a nd up to e i ght dev i ces a re su pporte d. S _STA T6 / S DATAO UT1 1O D St o ra ge St at us: Whe n SG PIO [ 1] i s di sa bl ed , t hi s pi n can be use d t o dr i ve an LE D to i n di ca te st at us o f t he l i nk for st o ra ge eng i ne[ 6]. Th e pi n ca n be di r ect dri ve n b y th e storage en gi ne or dr i ven fr o m an SG PI O. Note: Con nec t t he LED t o a se ri e s re si st o r pu l l e d u p t o VC C. S e r ia l D a t a O u t : ( d e f a u lt ) Wh e n S G P IO [ 1 ] is e n a b le d , t h is p in is t h e se ri a l o u tp ut dat a. The re ar e t hr ee bi ts o f dat a per dev i c e a nd up t o e i ght dev i ces a re su pporte d. T able 7 . S tor age In terface S i g nals (S h ee t 2 of 3 ) Name Count Type De scrip tion

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S_A CT7 1O D Storage Act i vi ty: When SG PI O[ 1] i s di sa bl ed, t hi s pi n c an be u sed to dr i ve a n LED to i n di cat e act i vi ty o n t he l i nk f o r st o ra ge en gi ne [7]. Th e pi n ca n b e di r ect dr i ven by t he storag e e ngi n e or d r i v en fr o m an S GPI O . No t e : Conn ect th e L ED to a ser i es res i stor pul l ed up to VCC . S_S TAT7 1O D Storage Sta tu s: W h en SGP I O[1 ] i s di sa bl ed, t hi s p i n c an be used to dri ve a n LED t o i nd i cat e sta tu s of th e l i n k for storage e ngi n e[7 ]. The pi n can be di re ct dri ven by th e st or a ge eng i ne o r dr i ven from an SGP I O. No t e : Conn ect th e L ED to a ser i es res i stor pul l ed up to VCC . To t a l 5 4 Table 7 . Sto r age I n terface Sign als (S heet 3 o f 3) N a me Coun t Typ e Des cript ion

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 27 Pa ck age In f ormat ion —Inte l ® 81 348 Ta b l e 8. I nt e rr up t Si gn a l s Name Count Type De scrip tion P_IN T[D:A ]# / XIN T[3:0 ]# / GP IO [ 1 1: 8 ] OD I I/ O Asyn c Rst (P) ActL o w Whe n P CIX_EP# = 0:

• PC I I n te rru pt re ques ts an i nt err upt fr o m t he cen tral res o u rce . The asse rt i o n a nd d eas ser ti on i s asy nch ronous . A devi ce ass ert s i t s XINT[3 :0] # / P_ I N T [ D : A ] # l i n e w h en re que sti n g at ten ti on from i ts devi ce dr i ver . As s o on as the XINT[3 :0] # / P_IN T[D:A ]# s ig n a l is a s s e r t e d , it r e m a in s a s s e r t e d u n t il t h e devi c e dr i ver cl ea rs th e pe ndi n g re que st. Whe n P CIX_EP# = 1:
• Ext er na l I nt er ru pt r equ est s a re use d by ext er nal devi c es t o req ues t i n te rru pt ser vi ce. Th ese pi ns ar e l e vel -de tec t i n put s an d ar e i nte rn al l y sync hron i zed. The se pi ns go to th e XIN T[3:0 ]# i npu ts of th e i n ter ru pt co n tr o l l e r . The i nt er rup t contr ol l e r can st eer th e i n te rr upt to e i the r the FI Q or the I R Q i nt ern al i n te rr upt i npu t o f th e Inte l XSca l e ® pr o c e s so r . G en eral Pu rpose I /O pi n s ca n be se l ect ed o n a per-p i n ba si s as ge nera l -pu rpose i npu ts o r outp ut s. T h e defa ul t mode i s a gen era l - pu rpose i npu t. XIN T[7:4 ]# / G P I O[15 :12] 4 I I/ O Asyn c ActL o w E xte rn al I nt er ru pt R e que sts a re u sed by ex te rna l devi c es to req ues t i n ter ru pt ser vi ce. Th ese pi ns ar e l eve l -de tec t a nd ar e i n ter na l l y sy nch roni ze d. These pi n s go t o the XINT[7 :4] # i np uts of th e in t e r r u p t c on t r olle r . T h e in t e r r u p t c o n t r o lle r c a n s t e e r t h e in t e r r u p t t o ei th er th e FI Q o r th e IRQ i nt er na l i nt er rup t i n put of t he I nt el XSca l e ® proces so r . G en eral Pu rpose I /O pi n s ca n be se l ect ed o n a per-p i n ba si s as ge nera l -pu rpose i npu ts o r outp ut s. T h e defa ul t mode i s a gen era l - pu rpose i npu t. GP IO [ 7 :0 ] / XIN T[15: 8]# / PM O NOU T I/ O I O Asyn c Rs t ( p) G en eral Pu rpose I /O pi n s ca n be se l ect ed o n a per-p i n ba si s as ge nera l -pu rpose i npu ts o r outp ut s. T h e defa ul t mode i s a gen era l - pu rpose i npu t. E xte rn al I n te rr upt s a re use d by ext ern al devi ce s t o req ues t i n ter ru pt ser vi ce. Th ese pi ns ar e l eve l -de tec t a nd ar e i n ter na l l y sy nch roni ze d. These pi n s go t o the XINT[1 5:8 ]# i npu ts o f th e i n ter ru pt co n tr o l l e r . The se i n te rr upt s ar e dedi ca te d t o t he I n tel XSca l e ® proce ssor . T o en ab l e a g i ven pi n a s a n i nt err upt , i t ne eds to be un ma sked i n t he I NT CTL [3:0 ] r egi s ter . Per form anc e M o n i tor Out : Th e P M O N un i t o u tpu t i ndi ca tor gen era tes a si gn al on the GPIO[7 ] p in w h e n e n a b le d in t h e P M O NE N r e g is t e r . W h e n e n a b le d it w ill overr i de the n o r mal G P IO [7] fu nct i o n . HPI# 1 I Asyn c ActL o w Hi gh -Pr i o r i ty I nt er ru pt c aus es a h i gh-p ri ori ty i nt er rup t t o th e I / O pr o c essor . Thi s pi n i s l eve l -det ect onl y an d i s i n te rn al l y sy nch roni ze d. NM I 0# 1 I Asyn c ActL o w Non-M ask abl e I n ter ru pt cau ses a n on-m aska bl e dat a abort t o t he I n te l XScal e ® p r o c e s s o r 0 in t h e I/ O p r o c e s s or . T h is p in is f a llin g e dge-d ete ct o n l y a nd i s i nt er na l l y syn chr oni zed . NM I 1# 1 I Asyn c ActL o w Non-M ask abl e I n ter ru pt cau ses a n on-m aska bl e dat a abort t o t he I n te l XScal e ® p r o c e s s o r 1 in t h e I/ O p r o c e s s or . T h is p in is f a llin g e dge-d ete ct o n l y a nd i s i nt er na l l y syn chr oni zed . To t a l 1 9

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Table 9 . I 2 C an d S M Bu s S i g nals N a me Coun t Typ e Des cript ion SCL 0 1 I/ O OD I 2 C 0 C l o ck provi de s syn ch ronous o pe rat i o n of t he I 2 C bu s. SDA0 1 I/ O OD I 2 C 0 Da ta i s u s ed f o r d a ta t r an s f er an d a rb i t r at i o n o f t he I 2 C bus . SCL 1 1 I/ O OD I 2 C 1 C l o ck provi de s syn ch ronous o pe rat i o n of t he I 2 C bu s. SDA1 1 I/ O OD I 2 C 1 Da ta i s u s ed f o r d a ta t r an s f er an d a rb i t r at i o n o f t he I 2 C bus . SCL 2 1 I/ O OD I 2 C 2 C l o ck provi de s syn ch ronous o pe rat i o n of t he I 2 C bu s. SDA2 1 I/ O OD I 2 C 2 Da ta i s u s ed f o r d a ta t r an s f er an d a rb i t r at i o n o f t he I 2 C bus . SM BCLK 1 I/ O OD SM Bus C l o c k pr o vi de s sy nch ronous o p erat i o n of t he SM bus. SM BDAT 1 I/ O OD SM Bus D at a i s us ed f o r da ta tra nsf er an d ar bi tra ti on o f th e bu s. To t a l 8 Note : Ope n drai n out put s req ui re a n ext er na l pu l l -up re si st o r t o pu l l up t he si gn al to 3 .3 V . Th e v a l ue of the pu l l -up re si stor depe nds o n t he bus l o a di ng .

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 29 Pa ck age In f ormat ion —Inte l ® 81 348 T able 1 0 . UAR T S i g nals (S h ee t 1 of 2 ) Name Count Type De scrip tion U 0_R X D 1 I Async UART 0 Ser i al I n put : Se ri al da ta i n put fr o m de vi ce pi n t o th e rec ei ve sh i ft re gi ste r . U 0_TXD 1 O Async UART 0 Seri a l Out put : C o m posi te ser i al d at a out put t o the comm un i cat i o n s l i n k - per i phera l , modem , or dat a set . Th e TXD si gn al i s set t o t he MAR KI NG (l ogi c 1) st at e upon a re set ope r a ti on . U 0_CTS # 1 I ActLow Async UART 0 Clear to Send: When low, this pin indicates that the receiving UART is ready to receive data. When the receiving UART deasserts CTS# high, the transmitting UART must stop transmission to prevent overflow of the receiving UART buffer. The CT S # signal is a modem-status input whose condition can be tested by the host processor or by the UART when in Autoflow Mode as described below: Non-A u tofl ow Mode : Whe n n ot i n Aut o f l o w M o d e, bi t[ 4] (CTS) of the M o de m St at us Regi st er ( MSR) i n di cat es t he st at e o f C TS # . Bi t[4 ] is t h e c o m p le m e n t of t h e C TS # s ig n a l. B it [ 0 ] (D CTS) of the M o de m St at us R eg i ste r i n di cat es whe th er th e C T S# i n put ha s c han ged sta te si n ce t he pre vi ous r ea di ng o f th e M odem Stat us Regi st er . C T S# h as no ef fec t on th e t r a ns mi tt er . Th e u ser can pr o g r a m the UART to i n ter ru pt the pr o c essor w h en DC T S cha nge s st at e. The pr o g r a mm er can t hen st al l t he outg o i n g da ta st re am by st ar vi n g th e t ran smi t FI FO or di sa bl i n g th e U A R T w i th th e I E R r eg i s te r . Note: W h e n U A RT t ra n s m is s io n is s t a lle d b y d is a b lin g t h e U A RT , t he use r doe s not re cei ve an MSR i nt err upt whe n C TS # r eas ser ts. Thi s i s beca use di sa bl i ng t he U AR T al s o di s abl e s i n ter ru pts . T o wo r k arou nd th i s, t he us er ca n use Aut o CTS i n Aut o fl ow M o d e, o r pr o gra m t he CTS# pi n to i n te rru pt. Aut ofl o w M ode: I n A u tofl ow M ode, t he U AR T tran smi t ci rcu i ty ch ecks t he s tat e of C T S# be fore tra nsm i tti n g e ach byt e. Whe n C T S# i s hi gh , n o dat a i s t r a ns mi tt ed. U 0_R TS# 1 O ActLow Async UAR T 0 Requ est to Se nd: Thi s bi t i n di ca tes to t he re mote devi ce w h e t h e r t h e U A R T is r e a d y t o r e c e iv e d a t a . W h e n t h is b it is lo w , t h e U A R T i s re ad y to r e ce i v e da ta . A re s e t o p e r at i o n s e ts t hi s s i gn a l t o i t s i na ct i ve (h i gh) sta te . LOO P M o d e opera ti on hol ds t hi s si gna l i n i t s i na ct i ve st at e. Non-A u tofl ow Mode : Th e RT S# out put si gn al can be ass ert ed by se tt i ng b i t[1 ] (RTS) of th e Modem C o n tr o l Regi st er t o 1. The R TS bi t i s t he compl em ent of t he R TS# si gn al . Aut ofl o w M ode: RT S# i s au toma ti ca l l y a sser te d by th e a ut o fl ow ci r cui t ry when t he rec ei ve buff er exce eds i t s pr ogramm ed t hr eshol d. I t i s dea sser te d whe n enou gh b yte s a re r emoved f rom t he bu ffer t o l ower th e d at a l e vel b ac k to t he th re s ho l d . U 1_R X D 1 I Async UART 1 Seri a l I n put : Se ri al dat a i npu t fr om t he devi c e pi n to t he r ecei ve sh i ft reg i ste r .

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U1_ TXD 1 O Async UAR T 1 Se ri al Out put : Comp o si t e s eri a l da ta out put to t he commu ni ca ti ons l i nk -pe ri ph era l , m o d em, or d at a se t. The TXD si gn al i s set to t he MAR KI NG (l o g i c 1 ) st at e u po n a re set opera ti on. U1_ CTS# 1 I ActLow Async UART 1 Clear to Send: When low, this pin indicates that the receiving UART is ready to receive data. When the receiving UART deasserts CT S # high, the transmitting UART must stop transmission to prevent overflow of the receiving UART buffer. The CTS# signal is a modem-status input whose condition can be tested by the host processor or by the UART when in Autoflow Mode as described below: No n - Aut ofl ow Mode: When n o t i n A u tofl ow Mode , bi t[4 ] ( CTS) of t he Modem Sta tu s R e gi st er (M SR) i ndi c at es th e sta te of CTS#. Bi t [4] i s th e c o m p l e me nt o f th e C T S # s i g na l . B i t[ 0 ] (D CTS) of t he Modem Sta tu s Regi st er i ndi c at es whet he r t he CTS# i np ut ha s ch an ged s ta te si nce th e pr ev i o u s re adi n g of t he M o de m St at us R e gi st er . CTS# h as n o eff ect on t he tra nsm i tt er . The use r c an progra m t he UAR T t o i nt err upt t he proce ssor wh en DCTS ch an ges sta te . The progra mme r c an th en sta l l th e o u tgoi ng dat as tr eam by sta rvi n g t he tra nsm i t FI FO or di sa bl i ng the UART wi th th e I E R r egi st er . No t e : When UART tra nsm i ssi on i s sta l l ed by di sa bl i ng th e UART , th e u ser does not r ece i ve a n M SR i n te rr upt when CTS# re asse rt s. T h i s i s be cau se d i s abl i n g th e UART al so di sa bl es i nt er rup ts. T o g et a roun d t hi s, the u ser c an u se Auto CTS i n Aut o fl ow M o d e, o r pr o gra m t he CTS# pi n to i n te rru pt. Aut o fl ow M o d e: No t e : I n Autofl ow M o de , th e UART tra nsm i t c i rcu i ty c hec ks t he s t at e o f CT S # b ef o r e t r an s mi t ti n g ea c h b y te . W h en CT S # i s hi g h , no da ta i s t r an s mi t t ed . U1_ RTS# 1 O ActLow Async UAR T 1 R eque st to Sen d: Th i s bi t i nd i cat es t o th e r em o t e de vi ce whet he r t he UAR T i s re ady to r ece i ve da ta . W h en l ow , t he UAR T i s re ady to r ecei ve da ta . A res et o p erat i o n se ts thi s si gn al t o i ts i na cti ve (h i gh) sta te . LOOP M o de opera ti on h ol d s t hi s s i gna l i n i t s i na cti ve st at e. No n - Aut ofl ow Mode: The R TS# out put si gn al ca n be a sse rt ed by set ti n g bi t [1] (RT S) of t he M odem Cont rol R e gi ste r to 1. Th e R TS bi t i s th e c o m pl eme nt of t he R TS# si gna l . Aut o fl ow M o d e: R TS# i s a ut o m at i cal l y as ser ted by t he au tofl ow ci rc ui t ry wh en th e r ece i ve bu ffe r e xcee ds i t s pr o gra mme d th re shol d. I t i s d eas ser ted when e nough byt es ar e re mo ve d fr om t he buff er to l ower th e da ta l eve l bac k t o the t hre shol d. To t a l 8 Table 1 0. UART Sign als (S heet 2 o f 2) N a me Coun t Typ e Des cript ion

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 31 Pa ck age In f ormat ion —Inte l ® 81 348 T able 1 1 . Miscellan eou s S i gn als Name Count Type De scrip tion TC K 1I T es t C l o ck provi de s cl ock i npu t f o r I E EE 11 49 . 1 Boun dar y Sca n T es ti ng (JT AG ). Sta te i nf o r ma ti on a nd dat a ar e cl ocked i nt o th e de vi ce o n th e ri si n g cl ock e dge, a nd dat a i s cl ocked o u t on th e fa l l i ng cl ock e dge. TD I 1 I Sy n c ( T ) T es t D at a Inpu t i s th e J T AG seri a l i n put pi n. TD I i s sam pl ed on th e r i si ng edge of T C K, dur i ng th e SHI FT -I R an d SHI FT - DR s ta tes of t he T es t Acc ess Port . Thi s si gna l ha s a wea k i n ter na l pu l l -up to en sur e pr o p er o pe rat i o n whe n t hi s pi n i s not bei n g dr i ve n. TD O 1 O Sy n c ( T ) Rs t (T ) T es t D at a Ou tpu t i s th e s eri a l out put pi n for t he JT AG fe at ur e. TDO i s dr i ven on th e fa l l i ng edg e o f TCK du ri n g th e SH IFT - IR an d SHIFT - D R st at es o f th e T es t Acc ess Port . A t oth er ti m es, TDO fl oat s. The be hav i o r of TDO i s i ndep end ent of oth er re set s. TR S T # 1 I Asyn c ActL o w T es t Rese t a syn chr o n ousl y res ets th e T e st Ac cess P or t con tr o l l e r fu nct i on of I E EE 11 49 Bound ar y Scan T est i ng ( JT AG ). Thi s pi n ha s a w e a k in t e r n a l p u ll- u p . Note: Th i s pi n mu st b e t i ed l ow whe n n o t u sed. TM S 1 I Sy n c ( T ) T es t Mode Sel ec t i s s amp l ed o n t he r i si ng edg e o f TCK t o sel e ct th e opera ti on o f th e t est l ogi c for I EE E 11 49 Bo u nda ry Sca n t est i ng. Th i s pi n ha s a wea k i nt er na l pul l - up. NC 54 I /O No Conn ect : P i ns have no u sabl e fu nct i o n a nd must n o t be conn ect ed to a ny si gn al , power , or groun d. P_R ST# 1 I Asyn c ActL o w Col d Rese t i s u sed to asy nch ronous l y re set th e I /O p rocessor w h en i t i s l ow . Thi s si gn al mus t be ass ert ed whe neve r th e po we r supp l i es ar e o ut s i de o f th e s p ec i f i e d r a ng e s .

• R eg i s t er s a r e re s e t to d e f au l t v a l u es .
• Pi n s a re dri ven t o known s ta tes .
• Sti cky confi g urat i on bi t s a re re set . W ARM_RST # Async ActLow W arm Rese t i s th e s ame a s a col d r ese t, exce pt sti c ky c o n fi gura ti on bi t s a re not res et. Th i s pi n shoul d onl y b e u sed w h en th e s ti cky bi t fu nct i ona l i t y i s req ui re d. I n th i s sce na ri o , t he W ARM _RST# pi n m ust be ti ed to t he syst em res et PC I _R ST # si gna l whi l e th e P _RST# p i n ca n be t i ed to th e s yste m p o wer good si gn al . I f th e st i cky bi t fun cti ona l i ty i s not re qui r ed, th e W ARM_ RST# pi n shou l d n o t be use d a nd m ust be ti e d t o Vc c. W h en th e P CI Exp ress i n ter fa ce i s use d a s a n e ndpoi nt , th e P CI Expr ess i nba nd Ho t R e set M ech an i sm c an al so be us ed t o provi de th e st i cky bi t fun cti on al i ty . Note: D ri vi n g W ARM _R ST# usi n g an y oth er met hods tha n su gges ted above may res ul t i n u npr edi ct ab l e be hav i o r of t he devi c e. TH E R M D A 1 I Th erm al D i o d e An o de i s t he an ode of t he th er ma l di ode. TH E R M D C 1 O Th erm al D i o d e C at hode i s th e ca th ode of t he th er ma l di ode. PUR 1 1I P ul l -U p Requ i r ed 1: Thi s p i n m ust be pul l e d up to V CC3 P3 wi t h a n ex t er n al 8. 2K Ω 5%, 1 / 16 Ω r esi st o r for prope r opera ti on . To t a l 6 4

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Table 1 2. Po wer and G ro u nd S ign al s N a me Coun t Typ e Des cript ion V C C1 P2PLLS 0 1 PW R V CC P LL Storage : Ba l l conn ect ed t o a 1 .2 V fi l te red boar d su ppl y . Pr o v i des p o wer t o o n e of t wo PLL s t hat cont rol St o ra ge i n te rfa ce . V C C1 P2PLLS 1 1 PW R V CC P LL Storage : Ba l l conn ect ed t o a 1 .2 V fi l te red boar d su ppl y . Pr o v i des p o wer t o o n e of t wo PLL s t hat cont rol St o ra ge i n te rfa ce . V C C1 P2PLLP 1 PW R V CC P LL PC I -X : Bal l co n ne cte d t o a 1 . 2 V f i l ter ed bo a rd supp l y . P ro v i des p o wer t o PLL th at cont rol s t he PC I - X l o gi c an d i n ter fa ce. V C C1 P2PLLD 1 PW R V CC P LL DD R: Ba l l conn ect ed t o a 1.2 V fi l te re d boar d su ppl y . P ro vi d e s po w e r to th e P LL th at c o nt r o l s t h e D DR 2 S D RA M i nt e rf ac e an d pr o c essor di gi ta l l ogi c. V C C3 P3PLLX 1 PW R V CC P LL X: Ba l l to be conn ect ed t o a 3.3 V fi l te red boar d su ppl y . Thi s pi n p ro v i des po we r t o a vol t age re gul a tor , whi ch su ppl i es p o w er to th e PL L th at c o n tr o l s t he I nt e l X S c al e ® pr ocessor a nd XSI proce ssor l ogi c. V S SPL LS0 1 GN D V SS PLL Storage : Ba l l to b e conn ect ed to a board grou nd p l a ne a t th e l oca ti on of th e V CC1 P2PLLS0 fi l te r . V S SPL LS1 1 GN D V SS PLL Storage : Ba l l to b e conn ect ed to a board grou nd p l a ne a t th e l oca ti on of th e V CC1 P2PLLS1 fi l te r . V S SPL LP 1 GN D V SS PLL PC I - X: Ba l l conne cte d t o capa ci t o r of t he V CC1P2 PLL P f ilt e r . V S SPL LD 1 GN D V SS PLL DD R2 SDRAM: Ba l l conn ect ed t o ca paci t o r of V C C1 P2PLLD f ilt e r . V S SPL LX 1 GN D V SS PLL X: Ba l l conn ect ed t o cap aci t o r of V C C3 P3PLLX f ilt e r . V CC 1 P 2 18 7 PW R 1.2 V Po we r: B a l l s t o be co n ne cte d to a 1 . 2 V boa rd power pl a ne. The se pi n s pr o v i de power to t he proce ssor l ogi c . V CC 1 P 2 A E 8 PW R 1.2 V Po we r: B a l l s t o be co n ne cte d to a 1 . 2 V boa rd power pl a ne. The se pi n s pr o v i de power to t he PC I E xpr ess* an al og l ogi c . V CC 1 P 2 E 6 PW R 1.2 V Po we r: B a l l s t o be co n ne cte d to a 1 . 2 V boa rd power pl a ne. The se pi n s pr o v i de power to t he PC I E xpr ess* di gi t al l ogi c . V CC 1 P 2 D S 6 PW R 1.2 V Po we r: B a l l s t o be co n ne cte d to a 1 . 2 V boa rd power pl a ne. The se pi n s pr o v i de power to t he st o ra ge i n te rfa ce di gi ta l l ogi c. V CC 1 P 2 A S 9 PW R 1.2 V Po we r: B a l l s t o be co n ne cte d to a 1 . 2 V boa rd power pl a ne. The se pi n s pr o v i de power to t he st o ra ge i n te rfa ce an al og l ogi c. V CC 1 P 2 X 11 9 PW R 1.2 V Po we r: B a l l s t o be co n ne cte d to a 1 . 2 V boa rd power pl a ne. The se pi n s pr o v i de power to t he I n tel XScal e ® pr o ce ssors. V CC V I O 21 PW R VI O Power : Ba l l s to be conn ect ed to a 3.3V b o a rd po we r pl a ne . The se pi n s pr o v i de 3 . 3 V p o wer t o t he P CI - X I /Os . V CC 1 P 8 30 PW R 1.8 V Po we r: B a l l s t o be co n ne cte d to a 1 . 8 V boa rd power pl a ne. The se pi n s pr o v i de power to t he DD R2 SDRAM i n ter fa ce I/Os . V CC 1 P 8 E 14 PW R 1.8 V Po we r: B a l l s t o be co n ne cte d to a 1 . 8 V boa rd power pl a ne. The se pi n s pr o v i de power to t he PC I E xpr ess* i nt er fac e I / Os. V CC 1 P 8 S 6 PW R 1.8 V Po we r: B a l l s t o be co n ne cte d to a 1 . 8 V boa rd power pl a ne. The se pi n s pr o v i de power to t he st o ra ge i n te rfa ce I /Os. V CC 3 P 3 42 PW R 3.3 V Po we r: B a l l s t o be co n ne cte d to a 3 . 3 V boa rd power pl a ne. The se pi n s pr o vi d e power to th e P BI , mi sc el l an eous pi ns, a nd P CI - X I /Os i n M ode 1 . V SS 37 3 GN D Gr ound : Bal l s to be conn ect ed t o a bo a rd groun d pl a ne . V SS E 20 GN D PC I E xpre ss* Gr ound : Ba l l s conn ect ed t o a bo a rd groun d pl a ne . V SS AS 20 GN D Ana l o g Storage G roun d: Ba l l s conn ect ed t o a bo a rd groun d pl a ne . V SS DS 6 GN D Di gi t al Storage Gr o u nd: Bal l s conn ect ed t o a b o a rd groun d pl a ne . To t a l 8 7 7

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 33 Pa ck age In f ormat ion —Inte l ® 81 348 T able 1 3 . Reset S trap S ign al s ( Sh eet 1 o f 3 ) Na m e Coun t T yp e Desc ript ion BO OT_WIDTH_8 # 1 Rese t St rap PBI Boo t Bus Wi dth : Set s t he def aul t bu s wi dt h f o r th e P BI Me mory Bo ot wi ndow . 0 = 8 b i ts w i de 1 = 16 bi t s wi de (def aul t m o de ) Note: Mu xed o n to si gn al A[0] . DF_S EL [ 2:0] 3 Rese t St rap De vi ce F u nct i on Se l ect : The se stra ps se l ect th e n um ber o f s to r ag e po rt s a s s i g ne d t o e ac h f u nc ti o n w i t hi n 81 34 8. Note: DF_ SEL[2 ] m uxed o n to si g na l A[9] Note: DF_ SEL[1 ] m uxed o n to si g na l A[8] Note: DF_ SEL[0 ] m uxed o n to si g na l A[7] See th e “ Dev i ce Fu nct i o n Sel e ct ” of t he In tel® 81 34 8 I/O Pr ocessor Dev eloper ' s Ma nu al fo r a ddi ti ona l de ta i l s. CFG_ CY CL E _EN# 1 Rese t St rap Conf i gura ti on C ycl e E na bl e: De ter mi n es wh eth er PC I in t e r f a c e r e t r ie s c on f ig u r a t i o n c y c le s u n t il C on f ig u r a t ion Cycl e R e try bi t i s c l ear ed i n A TU (P CSR[ 2] a nd Host Locko u t Bi t i s cl ea re d. 0 = Confi g urat i on cyc l e s e na bl ed 1 = Confi g urat i on r etr y e na bl ed (def aul t mode )

• P CI - X Int erf ace: Con fi gura ti on cycl es ar e cl a i med an d te rm i n at ed w i t h a r et ry s ta tu s .
• P CI Exp res s* Inte rf ace: Conf i gurat i on r equ est s re sul t i n a c o m pl et i o n TLP w i t h Confi g urat i on R et ry St atu s (CRS) . Note: M u xed o n to si gn al A[1] HOLD_X0_IN _RS T# 1 Rese t St rap H old In t e l X Sc a le ® Mi c roproce ssor 0 i n R e set : De te rmi n es w h et h er th e I n te l X S ca l e ® mi cr o p rocess o r nu mber 0 i s h el d in r e s e t u n t il t h e r e s e t b it is c le a r e d in t h e P C I C on f ig u r a t ion an d St at us Regi s ter . 0 = Ho l d i n r ese t 1 = Do n o t hol d i n r eset (de fa ul t mode) Note: Mu xed o n to si gn al A[2] HOLD_X1_IN _RS T# 1 Rese t St rap H old In t e l X Sc a le ® Mi c roproce ssor 1 i n R e set : De te rmi n es w h et h er th e I n te l X S ca l e ® mi cr o p rocess o r nu mber 1 i s h el d in r e s e t u n t il t h e r e s e t b it is c le a r e d in t h e P C I C on f ig u r a t ion an d St at us Regi s ter . 0 = Ho l d i n r ese t 1 = Do n o t hol d i n r eset (de fa ul t mode) Note: Mu xed o n to si gn al A[3] ME M _ F R E Q [ 1 : 0 ] 2 Rese t St rap M em o r y F re q ue nc y : D e te rm i n es f re q ue nc y at w hi c h DD R2 me mory subsy ste m r un s. 00 = Reserved 01 =Reser ved 10 =5 33 MHz 11 =4 00 MHz (De fa ul t mode) Note: ME M_ F R E Q [ 1 ] muxe d ont o si gna l A[ 5] Note: ME M_ F R E Q [ 0 ] muxe d ont o si gna l A[ 4] EXT_ ARB# 1 Rese t St rap Ex ter na l Arbi t er : D ete rm i nes whet he r t he PC I i n ter fa ce en abl e s t he i nte grat ed ar bi ter , o r us e a n e xte rn al a rbi t er . 0 = Ext er na l ar bi te r 1 = I nt er na l ar bi te r ( defa ul t mode ) Note: Mu xed o n to si gn al A[6] I NTERFA CE_SE L _PCIX# 1 Rese t St rap 0 = PC I -X i s a cti ve 1 = PC I E xpre ss i s act i ve ( defa ul t mode ) When both i n ter fa ces are a cti ve , t hi s stra p se l ect s t he A TU th at i s f un cti on 0 i n th e i n te rn al a ddr ess m ap. Note: M u xed o n to si gn al A[10 ] PCIX_EP# 1 Rese t St rap PC I - X En d Poi nt : De te rmi n es w h et her t he PC I - X i nt erf ace operat es as an en dpoi nt o r a cen tra l re sourc e. 0 = En dpoi nt 1 = Cen tra l re sourc e (d efa ul t mode) Note: Mu xed o n to si gn al A[11 ] Note: Set ti n g bot h PCIX_EP# a nd PC I E_ RC # t o en dpoi nt i s u nsu pport ed.

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P CIE _RC# 1 Reset Stra p PCI -E Ro ot Compl e x: D et erm i nes whet he r P CI Exp res s* i nte rfa ce o p erat es as an end po i n t o r a roo t comp l ex. 0 = Roo t compl e x 1 = E ndp o i n t ( defa ul t mode) No t e : Mu x e d ont o si gna l A[1 2] S e tt i ng bo t h PCIX_EP# and PCIE_RC# t o endp o i n t i s uns upport ed. SM B _ A5 , SM B _ A3 , SM B _ A2 , SMB_A1

4 Reset

S M Bu s Addr ess: Ma ps to ad dres s bi t [5] , b i t[3 ], bi t[ 2], a nd bi t[1 ] wh ere bi t s[7 :0] re pres ent a ddre ss SM Bus sl ave po r t r e sp o nd s to w h e n ac c e s s i s at te m p te d . 0 = Add res s bi t i s l ow 1 = Add res s bi t i s h i gh ( defa ul t mode ) No t e : SM B _ A5 m uxed o n to si gn al A[ 1 6] No t e : SM B _ A3 m uxed o n to si gn al A[ 1 5] No t e : SM B _ A2 m uxed o n to si gn al A[ 1 4] No t e : SM B _ A1 m uxed o n to si gn al A[ 1 3] P CIX_PULL U P # 1 Reset Stra p PCI - X P ul l U p: De te rmi n es wh eth er PC I i nt er face ha s on-di e pul l -u ps e na bl ed. The se may be u sed for t he cen tra l res o u rce bus keep ers . 0 = E na bl e P CI pul l - up r esi s tors 1 = D is a b le P C I p u ll- u p r e s is t or s ( d e f a u lt m o d e ) No t e : Mu x e d ont o si gna l A[1 7] P CIX_3 2BIT# 1 Reset Stra p 32 -Bi t P CI - X Bu s: I ndi c ate s wi dt h of the P CI - X bu s t o P CI - X S t at us Regi s ter . E na bl es pu l l -up s for upp er h al f of bu s when in 3 2 - b it m od e . 0 = 3 2- bi t wi de P CI - X bu s 1 = 6 4- bi t wi de P CI - X bu s (de fa ul t mode) No t e : Mu x e d ont o si gna l A[1 8] PCIXM 1_ 100 # 1 Reset Stra p PCI - X Mode 1 1 00 M Hz En ab l e: In C ent ral R es o u rce Mode , t h is b it lim it s P C I-X b u s t o 1 0 0 M Hz w h ile in m o d e 1 : 0 = L i mi t PC I - X mode 1 t o 10 0 M Hz 1 = 1 33 M Hz e nab l ed ( defa ul t mode) No t e : Mu x e d ont o si gna l A[1 9] HS_ SM # 1 Reset Stra p H ot S wap Sta rt up M ode: I n End Po i n t Mode, t hi s b i t det erm i nes whet he r Hot S wap mode i s en abl e d. 0 = Hot S wap Mode ena bl ed 1 = Hot S wap Mode di sab l ed ( defa ul t mode) No t e : Mu x e d ont o si gna l A[2 1] FW _TIM E R_OFF # 1 Reset Stra p F i r mw a re Ti me r Off : D i sabl e s 4 00 mS f i rmwar e t i me r for devel opm ent a nd deb ug. Wh en en abl e d, ti m er a utoma ti c al l y cl ea rs C o n fi gu rat i o n Cycl e R e tr y (C CR) bi t i n P CSR aft er 40 0 m S re gar dl ess o f pr o ce ssor s ta te. Wh en di sabl e d, CCR bi t f un cti ons as norma l ba sed o n st at e of CFG_ CYCLE _E N# pi n a t ri si n g edg e of P _R ST# . 0 = F i rm w ar e t i me r d i s a bl e d 1 = F i rm w ar e t i me r e n ab l e d ( d ef a ul t mo de ) No t e : Mu x e d ont o si gna l A[2 2] CON TROLL ER _ON L Y# 1 Reset Stra p C o n t r o lle r - O n ly E n a b le : 0 = C o n tr o l l e r on l y , RAI D di sa bl ed 1 = R AI D ena bl ed (def au l t m o de ) No t e : Mu x e d ont o si gna l A[2 3] L K_DN_R ST_BYP A SS# 1 Reset Stra p Li nk Down Rese t By pass : D i sabl e s t he ful l chi p rese t tha t w oul d norm al l y be c au sed b y a Li nk Down o r hot re set . 0 = D o not res et o n Li n k D o wn 1 = Rese t o n Li n k Down (def au l t m o de ) No t e : Mu x e d ont o si gna l A[2 4] Table 1 3. Reset Str ap S i g nals (S h ee t 2 of 3 ) Name C ou nt Type D escr iption

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 35 Pa ck age In f ormat ion —Inte l ® 81 348 CLK _S RC_PCIE# 1 Rese t St rap Cl ock Sour ce PC I - E: Se l ect s P CI E xpr ess* R e fcl k pai r as th e i npu t cl o c k t o t he P LLs t ha t co n tr o l most i nte rn al l ogi c. 0 = So u rce cl ock i s REF C LK P / REFCLK N 1 = So u rce cl ock i s P_CL KIN (default mode) Note: When P_ C LK O [ 3 : 0 ] a re use d th i s pi n mu st be p u lle d lo w. Note: Mu xed o n to si gn al PW E # Tota l 25 Rese t st rap si gna l s a re l at che d on the r i si ng e dge o f P_RS T# . A ll r e s e t s t r a p s ig n a ls a r e in t e r n a lly p u lle d t o l o gi c 1 by de fau l t. An ext er nal 4.7K o h m 5%, 1 /16 ohm pul l - do wn re si stor i s r equi r ed to forc e a l ogi c 0 o n t hes e pi n s. T able 1 3 . Reset S trap S ign al s ( Sh eet 3 o f 3 ) Na m e Coun t T yp e Desc ript ion

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Table 1 4. Fu nctio n al P i n Mo de B e h avio r ( Sh eet 1 o f 4 ) Pin Boun da ry Scan H igh Z Reset (End Point) Reset (Central Resou rce) N orm al -Bit SD RAM PC IX_3 2BIT# PC IX_PULLU W hen on ly PCI-X Interface Active W hen on ly PCI Ex p ress* Interface Active M _CK[2: 0] , M A[ 14:0 ] BA [ 2 : 0 ] Z V O V O V O ––––– C S [1: 0]# Z V O V O V O ––––– D Q S[8] , D Q S[7: 4] , D Q S[3: 0] , DM [ 7 : 4 ] Z V O * V O * V O ––––– DM [ 3 : 0 ] Z V O * V O * V O ––––– PC E [ 1 : 0 ] # Z H H V O ––––– H S _FREQ[ 1:0 ] / C R _FREQ [1:0 ] Z H H H ––––– Note s: 1 = dr i ven to V CC 0 = dr i ven to V SS X = dri ve n t o un known s ta te ID = Th e i n put i s di sabl e d. H = pul l e d up to V CC P D = pul l - up di s abl e d L = pu l l ed down to V SS ODT = On Di e T er mi na ti on G ND = T i e t o G rou nd . E A = Ext er na l Arbi t er mode IA = I nt er na l Arbi t er mode Z = ou tpu t, pul l - up/d o wn di sa bl ed V B = a c t s lik e a Va lid Bid ir e c t io n a l p in V O = a Va lid O u t p u t l e v e l is d r iv e n . VI = nee d t o dri ve a V al i d I np ut l evel . AO = An al og Ou tpu t l e vel AI = Anal og I npu t l e vel * = af te r power fa i l seq uen ce co m pl et es “- ” = u na ffe cte d by thi s mode a . MA[1 4 ] i s onl y ne ede d for 4G B me mory suppor t. Whe n 4 GB mem o r y i s not use d th i s pi n i s NC .

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 37 Pa ck age In f ormat ion —Inte l ® 81 348 P_A D [ 63:3 2] ZZZ V B –H H–H P_A D [ 31:0 ] Z Z 0 V B –––– H P_CBE[7 :4]# ZZZ V B –H H–H P_PAR6 4 ZZZ V B –H H–H P_RE Q64# ZV I0 V B – – H – H P_A CK 64 # ZZZ V B – –H–H P_FRA M E# Z V I V O V B – –H–H P_IR D Y# Z V I V O V B – –H–H P_TR D Y# Z V I V O V B – –H–H P_S TOP# Z V I V O V B – –H–H P_DEVSEL# Z V I V O V B – –H–H P_PERR# Z V I V O V B – –H–H P_G NT[0 ]# / P_ R E Q # Z Z (EA) H (I A ) Z (EA) H (I A ) V O –––– H P_RE Q[0]# / P_G NT# – VI (E A ) VI (E A ) H (I A ) VI (E A ) H (I A ) –––– H P_G NT[3 :1]# Z H H V O –––– H P_CLK IN – V I V I V I –––– G N D P_CLK OU T Z Z V O V O –––– Z P_CLK O[ 3:0] Z Z V O V O –––– Z P_PCIXCAP – A I A I A I –––– G N D P_BM I Z V O V O V O –––– V O P_CA L [2: 0] Z A O A O A O –––– V O S _CL KP 0 , S_CLK N 0 – V I V I V I ––––– S _TXP [ 7:0] , S_ R X P [7 : 0] , S_ R X N [ 7: 0 ] – I D I D V I ––––– T able 1 4 . Fu n ction al Pin M od e B ehav ior (S heet 2 o f 4) Pi n Boun da ry Scan H igh Z Reset (End Point) Reset (Central Resou rce) N orm al -Bit SD RAM PC IX_3 2BIT# PC IX_PULLU W hen on ly PCI-X Interface Active W hen on ly PCI Ex p ress* Interface Active No t e s : 1 = dri ven t o V CC 0 = dri ven t o V SS X = dr i ven to un kn o wn sta te I D = The i npu t i s di sa bl ed. H = pu l l e d u p t o V CC PD = pu l l -up di sab l ed L = pu l l ed do wn to V SS OD T = On D i e T e rmi n at i o n GND = Ti e t o Gr o u nd . E A = E xte rna l Ar bi ter mode IA = In t e r n a l A r b it e r m o d e Z = o u tpu t, pu l l -up /dow n di sa bl ed VB = act s l i ke a V a l i d Bi di re cti ona l pi n VO = a V al i d Out put l eve l i s dr i ven. V I = n e e d t o d r iv e a V a lid In p u t le v e l. AO = Anal og O u tpu t l evel AI = Ana l o g I n put l eve l * = a ft er po we r f ai l se que nce compl e tes “ -” = un aff ect ed by th i s m o de a. M A[14 ] i s o n l y n eed ed f o r 4G B m emory sup po r t. Wh en 4G B me mory i s not use d t hi s pi n i s NC.

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RBIAS[ 1:0 ] – A O A O A O ––––– RBIAS_ SEN SE[1: 0] – A I A I A I ––––– S_A CT0 / SC L O C K 0 Z Z Z V O ––––– S_S TAT0 / SLOAD0 Z Z Z V O ––––– S_A CT2 / SD AT A I N0 Z Z Z V O ––––– S_S TAT2 / SDATA OUT 0 Z Z Z V O ––––– S_A CT4 / SC L O C K 1 Z Z Z V O ––––– S_S TAT4 / SLOAD1 Z Z Z V O ––––– S_A CT6 / SD AT A I N1 Z Z Z V O ––––– S_S TAT6 / SDATA OUT 1 Z Z Z V O ––––– REFCL KP , REFCL KN – V IV IV I – – – G ND/ VI – P ETP[7 :0] , P ETN [7: 0] –Z Z V O –––Z – PE R P[ 7 : 0 ] , PE R N [ 7 : 0 ] – I D I D V I –––Z – PE _ C A LP – A O A O A O –––Z – PE _ C A LN – A O A O A O –––Z – P_ I N T [ D : A ] # / X IN T[3: 0]# Z Z/VI Z/VI V B – – H – – GPIO[7: 0] / XI N T [ 1 5 : 8 ] # / P MONOU T Table 1 4. Fu nctio n al P i n Mo de B e h avio r ( Sh eet 3 o f 4 ) Pin Boun da ry Scan H igh Z Reset (End Point) Reset (Central Resou rce) N orm al -Bit SD RAM PC IX_3 2BIT# PC IX_PULLU W hen on ly PCI-X Interface Active W hen on ly PCI Ex p ress* Interface Active Note s: 1 = dr i ven to V CC 0 = dr i ven to V SS X = dri ve n t o un known s ta te ID = Th e i n put i s di sabl e d. H = pul l e d up to V CC P D = pul l - up di s abl e d L = pu l l ed down to V SS ODT = On Di e T er mi na ti on G ND = T i e t o G rou nd . E A = Ext er na l Arbi t er mode IA = I nt er na l Arbi t er mode Z = ou tpu t, pul l - up/d o wn di sa bl ed V B = a c t s lik e a Va lid Bid ir e c t io n a l p in V O = a Va lid O u t p u t l e v e l is d r iv e n . VI = nee d t o dri ve a V al i d I np ut l evel . AO = An al og Ou tpu t l e vel AI = Anal og I npu t l e vel * = af te r power fa i l seq uen ce co m pl et es “- ” = u na ffe cte d by thi s mode a . MA[1 4 ] i s onl y ne ede d for 4G B me mory suppor t. Whe n 4 GB mem o r y i s not use d th i s pi n i s NC .

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 39 Pa ck age In f ormat ion —Inte l ® 81 348 SM B C L K Z Z Z V B ––––– SM B D A T Z Z Z V B ––––– NC - / Z Z / H Z / H Z / H ––––– T able 1 4 . Fu n ction al Pin M od e B ehav ior (S heet 4 o f 4) Pi n Boun da ry Scan H igh Z Reset (End Point) Reset (Central Resou rce) N orm al -Bit SD RAM PC IX_3 2BIT# PC IX_PULLU W hen on ly PCI-X Interface Active W hen on ly PCI Ex p ress* Interface Active No t e s : 1 = dri ven t o V CC 0 = dri ven t o V SS X = dr i ven to un kn o wn sta te I D = The i npu t i s di sa bl ed. H = pu l l e d u p t o V CC PD = pu l l -up di sab l ed L = pu l l ed do wn to V SS OD T = On D i e T e rmi n at i o n GND = Ti e t o Gr o u nd . E A = E xte rna l Ar bi ter mode IA = In t e r n a l A r b it e r m o d e Z = o u tpu t, pu l l -up /dow n di sa bl ed VB = act s l i ke a V a l i d Bi di re cti ona l pi n VO = a V al i d Out put l eve l i s dr i ven. V I = n e e d t o d r iv e a V a lid In p u t le v e l. AO = Anal og O u tpu t l evel AI = Ana l o g I n put l eve l * = a ft er po we r f ai l se que nce compl e tes “ -” = un aff ect ed by th i s m o de a. M A[14 ] i s o n l y n eed ed f o r 4G B m emory sup po r t. Wh en 4G B me mory i s not use d t hi s pi n i s NC.

Intel ® 8 1348 —P ack ag e Informa tion In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

40 O r d er N um b e r: 31 50 38 -0 03 US

Figu re 2 . 13 57 -Lead FCB GA Pa ckage (To p an d Bo tto m V iews )

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 41 Da tas h e et —I nte l ® 813 48 Th e fo ll ow in g f igu res sh o w t h e I n tel ® 8 1348 ba llo u t dia gr a ms :

• Fi gu re 3, “In t e l ® 813 48 I/O pro ce ss or Ba llo u t —Pac ka ge T o p (Left S ide) ” o n pa ge 4 2
• Fi gu re 4, “In t e l ® 813 48 I/O pro ce ss or Ba llo u t —Pac ka ge T o p (Righ t S ide) ” o n pa ge 4 3
• Fi gu re 5, “In t e l ® 813 48 I/O pro ce ss or Ba llo u t —Pac ka ge B o tt o m (L e ft S ide) ” o n pa ge 4 4
• Fi gu re 6, “In t e l ® 813 48 I/O pro ce ss or Ba llo u t —Pac ka ge B o tt o m (Righ t S ide) ” o n pa ge 4 5 Th e fo ll ow in g ta ble s s h ow th e In t e l ® 813 48 b all an d sig na l l istin gs :
• T abl e 15, “Intel ® 81 348 I/O p ro ces so r 1357-L e ad P a ck age — A lp ha betic al B all Lis t i ng s” on pa ge 46
• T abl e 16, “Intel ® 81 348 I/O p ro ces so r 1357-L e ad P a ck age — A lp ha betic al S ign al Lis t i ng s” on pa ge 54

Intel ® 8 134 8—Da ta sheet In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

42 O r d er N um b e r: 31 50 38 - 0 03 US

Figu re 3 . In tel ® 8 13 4 8 I / O pr oc e s so r Ballo ut —Pac kage To p (Left Side) ABCDEFGHJKLMNPRTUV W 37 vss dq [63] dqs [7] dqs# [7] dq [57] dq [56] dq [60] dq [43] dq [47] dqs [5] dqs# [5] dq [41] dq [40] dq [44] cb [2] cb [6] dqs# [8] 36 vss dq [59] dq [58] dq [62] vss dm [7] dq [61] vss vss dq [42] dq [46] vss dm [5] dq [45] vss cb [3] cb [7] dqs [8] 35 vss nc dq [51] dq [50] dqs [6] dqs# [6] dm [6] dq [53] dq [52] dq [35] dq [34] dqs [4] dqs# [4] dm [4] dq [37] dq [36] m_ck# [2] vss dm [8] 34 nc nc vss dq [55] dq [54] vss dq[ 49] dq [48] vss vss dq [39] dq [38] vss dq [33] dq [32] vss m_ck [2] m_ck# [0] m_ck [0] 33 nc nc ma[14] a nc vss odt [1] cs# [1] ma [13] odt [0] cas# we# vss cs# [0] ras# ba [0] ma [10] ba [1] ma [0] vss 32 nc nc nc nc nc vcc3 vcc3 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 31 nc nc nc nc nc nc vcc3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 30 nc vss nc vss nc nc vcc3 p3 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 29 nc nc nc nc nc nc vcc3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vsspllx therm da nc 28 nc nc nc nc nc nc vcc3 p3 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x therm dc vcc1 p2x 27 s_ act1 vss s_ stat5 vss s_ act4 stat3 vcc3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 26 s_ act5 stat2 act0 stat7 stat6 stat4 vcc3 p3 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 25 s_ stat0 act2 act3 act7 stat1 act6 vcc3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 24 vssas vssas vssas vssas vcc1 p2as vcc1 p2as vcc1 p2as vss vcc1 p2 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 23 s_ rxp[3] rxn[3] txp[3] txn [3] vcc1 p2as vcc1 p2as vcc1 p2as vcc1 p2 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 22 s_ rxp[1] rxn[1] txp[1] txn [1] vcc1 p2as vcc1 p2as vcc1 p2as vss vcc1 p2 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 21 vssas vssas vssas vssas rbias_ sense [0] nc nc s_ clkp0 vssplls0 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 20 s_ rxp[0] rxn[0] txp[0] txn [0] rbias [0] nc nc s_ clkn0 vcc1 p2plls0 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 19 s_ rxp[2] rxn[2] txp[2] txn [2] vcc1 p8s vcc1 p8s vcc1 p8s vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 18 vssas vssas vssas vssas vcc1 p8s vcc1 p8s vcc1 p8s vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 17 s_ rxp[7] rxn[7] txp[7] txn [7] vcc1 p2ds vssds vssds vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 16 s_ rxp[5] rxn[5] txp[5] txn [5] rbias_ sense [1] nc nc vss vssplls1 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 15 vssas vssas vssas vssas rbias [1] nc nc vss vcc1 p2plls1 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 14 s_ rxp[4] rxn[4] txp[4] txn [4] vssds vcc1 p2ds vssds vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 13 s_ rxp[6] rxn[6] txp[6] txn [6] vcc1 p2ds vssds vcc1 p2ds vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 12 vssas vssas vssas vssas vssds vcc1 p2ds vcc1 p2ds vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 11 gpio [1] gpio [3] gpio [7] gpio [5] gpio [6] vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vsspllp vcc1 p2pllp vss vcc1 p2 vss vcc1 p2 vss 10 gpio [0] vss gpio [2] vss gpio [4] vcc3 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 9 xint# [1] xint# [3] xint# [5] xint# [4] xint# [7] vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 8 xint# [2] xint# [0] xint# [6] nmi0# hs_ led_out vcc3 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 7 hs_ enum# vss hpi# vss nmi1# vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 6 u0_ rts# u0_ rx d hs_ lstat hs_ freq [1] hs_ freq [0] vcc3 vcc3 p3 vccvio vcc3 vcc3 p3 vccvio vccvio vcc3 p3 vccvio vcc3 vcc3 p3 vccvio vcc3 vcc3 5 u0_ cts# u0_ tx d u1_ rx d nc vcc3 cal [0] gnt# [3] vccvio gnt# [0] ad [31] vccvio ad [26] idsel vccvio ad [16] trdy# vccvio ad [13] ad [9] 4 u1_ cts# u1_ tx d u1_ rts# vss warm_rs bmi vss req# [3] gnt# [1] vss ad [30] ad [24] vss ad [20] frame# vss p_ par ad [11] vss 3v s s clko [3] clko [2] cal [2] nc cal [1] req# [2] gnt# [2] nc ad [27] ad [28] ad [23] ad [22] ad [18] devsel# stop# ad [15] ad [12] cbe# [0] 2 vss clko [0] clkout vss p_ rst# v s sn c n cv s s ad [25] ad [21] vss cbe# [2] pcixcap vss cbe# [1] ad [10] vss 1 vss p_ clkin clko [1] rstout# nc req# [1] req# [0] ad [29] cbe# [3] ad [19] ad [17] irdy# perr# serr# ad [14] m66en vss a. MA[1 4] o n l y n ee ded f o r 4 GB m emor y su pport, oth er w i s e t hi s pi n i s NC.

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 43 Da tas h e et —I nte l ® 813 48 Figu r e 4 . In tel ® 8 1 34 8 I /O pr o cesso r B all o u t—P ackage To p (R ight S ide) Y A AA BA CA DA EA FA GA HA JA KA LA MA NA PA RA TA U cb [1] cb [0] dq [27] dq [31] dqs [3] dqs# [3] dq [25] dq [24] dq [28] dq [11] dq [15] dqs [1] dqs# [1] dq [9] dm [1] vss 37 cb [5] cb [4] vss dq [26] dq [30] vss dm [3] dq [29] vss vss dq [10] dq [14] vss dq [8] dq [13] dq [12] vss 36 vss m_ck [1] dq [19] dq [18] dqs [2] dqs# [2] dm [2] dq [21] dq [20] dq [3] dq [2] dqs [0] dqs# [0] dm [0] dq [5] dq [4] cal [0] vss 35 ma [2] m_ck# [1] vss dq [23] dq [22] vss dq [17] dq [16] vss vss dq [7] dq [6] vss dq [1] dq [0] vss cal [1] vss 34 ma [1] ma [3] ma [4] ma [6] vss ma [5] ma [8] ma [7] ma [9] ma [11] ma [12] vss ba [2] cke [0] cke [1] rst# vref vss 33 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 p8 32 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc3 vcc3 p3 vss tck vss trst# 31 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 vcc3 vcc3 p3 tdo tms tdi 30 vcc3 p3pllx vss vcc1 p2x vssplld vcc1 p2plld vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc3 p3 scl1 sda2 sda1 scl0 smbclk 29 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 p3 scl2 vss sda0 vss smbdat 28 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x 27 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e 26 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p8e vcc1 p8e vsse vsse vsse vsse 25 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc1 p2ae vcc1 p8e petn [7] petp [7] pern [7] perp [7] 24 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2 vss vcc1 p2ae vcc1 p8e petn [6] petp [6] pern [6] perp [6] 23 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2 vss vcc1 vcc1 p2ae vcc1 p8e vsse vsse vsse vsse 22 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2ae vcc1 p8e petn [5] petp [5] pern [5] perp [5] 21 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 refclkp nc nc pe_cal p petn [4] petp [4] pern [4] perp [4] 20 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss refclkn nc nc pe_cal n vsse vsse vsse vsse 19 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 vcc1 p2ae vcc1 p8e petn [3] petp [3] pern [3] perp [3] 18 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2ae vcc1 p8e petn [2] petp [2] pern [2] perp [2] 17 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 vcc1 p2ae vcc1 p2e vsse vsse vsse vsse 16 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2ae vcc1 p2e petn [1] petp [1] pern [1] perp [1] 15 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 vcc1 p2e vcc1 p2e petn [0] petp [0] pern [0] perp [0] 14 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2e vcc1 p2e vsse vsse vsse vsse 13 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 p2 12 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 pce# [1] a [21] a [19] a [18] a [22] 11 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 vcc3 a [20] vss pce# [0] vss a [13] 10 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 p3 nc a [9] a [12] a [8] a [14] 9 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 vcc3 p3 PUR1 a [10] pb_rsto ut# a [1] a [6] 8 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 a [11] vss a [15] vss a [2] 7 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 vcc3 d [15] a [16] a [17] a [3] a [7] 6 ad [4] vccvio cbe# [7] par64 vccvio ad [56] ad [52] vccvio ad [44] ad [40] vccvio ad [32] d [10] vcc3 d [9] d [4] a [4] a [5] 5 ad [6] ad [0] vss cbe# [5] ad [60] vss ad [54] ad [48] vss ad [42] ad [36] vss poe# d [2] vss d [3] d [8] d [1] 4 ad [5] ad [2] req64# ad [63] ad [62] ad [58] ad [51] ad [50] ad [46] ad [39] ad [38] ad [34] pwe# d [12] d [11] a [23] d [0] vss 3 ad [7] ad [1] vss cbe# [4] ad [59] vss ad [53] ad [47] vss ad [41] ad [35] vss d [14] d [6] d [5] a [0] vss ad [8] ad [3] ack64# cbe# [6] ad [61] ad [57] ad [55] ad [49] ad [45] ad [43] ad [37] ad [33] a [24] d [7] d [13] vss 1

Intel ® 8 134 8—Da ta sheet In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

44 O r d er N um b e r: 31 50 38 - 0 03 US

Figu re 5 . In tel ® 8 13 4 8 I / O pr oc e s so r Ballo ut —Pac kage Bo tto m (Left Side) AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W 37 vss dm [1] dq [9] dqs# [1] dqs [1] dq [15] dq [11] dq [28] dq [24] dq [25] dqs# [3] dqs [3] dq [31] dq [27] cb [0] cb [1] dqs# [8] 36 vss dq [12] dq [13] dq [8] vss dq [14] dq [10] vss vss dq [29] dm [3] vss dq [30] dq [26] vss cb [4] cb [5] dqs [8] 35 vss cal [0] dq [4] dq [5] dm [0] dqs# [0] dqs [0] dq [2] dq [3] dq [20] dq [21] dm [2] dqs# [2] dqs [2] dq [18] dq [19] m_ck [1] vss dm [8] 34 vss cal [1] vss dq [0] dq [1] vss dq [6] dq [7] vss vss dq [16] dq [17] vss dq [22] dq [23] vss m_ck# [1] ma [2] m_ck [0] 33 vss m_ vref rst# cke [1] cke [0] ba [2] vss ma [12] ma [11] ma [9] ma [7] ma [8] ma [5] vss ma [6] ma [4] ma [3] ma [1] vss 32 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 31 trst# vss tck vss vcc3 vcc3 p3 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 30 tdi tms tdo vcc3 vcc3 vcc3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 29 smbclk scl0 sda1 sda2 scl1 vcc3 p3 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2plld vssplld vcc1 p2x vss vcc3 p3pllx nc 28 smbdat vss sda0 vss scl2 vcc3 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 27 vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 26 vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p8e vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 25 vsse vsse vsse vsse vcc1 p8e vcc1 p8e vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 24 perp [7] pern [7] petp [7] petn [7] vcc1 p8e vcc1 p2ae vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 23 perp [6] pern [6] petp [6] petn [6] vcc1 p8e vcc1 p2ae vss vcc1 p2 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss 22 vsse vsse vsse vsse vcc1 p8e vcc1 p2ae vcc1 p2 vss vcc1 p2 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x 21 perp [5] pern [5] petp [5] petn [5] vcc1 p8e vcc1 p2ae vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 20 perp [4] pern [4] petp [4] petn [4] pe_cal p nc nc refclkp vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 19 vsse vsse vsse vsse pe_cal n nc nc refclkn vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 18 perp [3] pern [3] petp [3] petn [3] vcc1 p8e vcc1 p2ae vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 17 perp [2] pern [2] petp [2] petn [2] vcc1 p8e vcc1 p2ae vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 16 vsse vsse vsse vsse vcc1 p2e vcc1 p2ae vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 15 perp [1] pern [1] petp [1] petn [1] vcc1 p2e vcc1 p2ae vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 14 perp [0] pern [0] petp [0] petn [0] vcc1 p2e vcc1 p2e vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 13 vsse vsse vsse vsse vcc1 p2e vcc1 p2e vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 12 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 11 a [22] a [18] a [19] a [21] pce# [1] vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 10 a [13] vss pce# [0] vss a [20] vcc3 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 9 a [14] a [8] a [12] a [9] nc vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 8 a [6] a [1] pb_rst out# a [10] PUR1 vcc3 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 7 a [2] vss a [15] vss a [11] vcc3 p3 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss 6 a [7] a [3] a [17] a [16] d [15] vcc3 vcc3 p3 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 p3 vccvio vccvio vcc3 5 a [5] a [4] d [4] d [9] vcc3 d [10] ad [32] vccvio ad [40] ad [44] vccvio ad [52] ad [56] vccvio p_ par64 cbe# [7] vccvio ad [4] ad [9] 4 d [1] d [8] d [3] vss d [2] poe# vss ad [36] ad [42] vss ad [48] ad [54] vss ad [60] cbe# [5] vss ad [0] ad [6] vss 3v s s d [0] a [23] d [11] d [12] pwe# ad [34] ad [38] ad [39] ad [46] ad [50] ad [51] ad [58] ad [62] ad [63] req64# ad [2] ad [5] cbe# [0] vss a [0] d [5] d [6] d [14] vss ad [35] ad [41] vss ad [47] ad [53] vss ad [59] cbe# [4] vss ad [1] ad [7] vss 1 vss d [13] d [7] a [24] ad [33] ad [37] ad [43] ad [45] ad [49] ad [55] ad [57] ad [61] cbe# [6] ack64# ad [3] ad [8] vss

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 45 Da tas h e et —I nte l ® 813 48 Figu r e 6 . In tel ® 8 1 34 8 I /O pr o cesso r B all o u t—P ackage Bo tto m ( Righ t Side) VUTRPNMLKJHGFEDCBA cb [6] cb [2] dq [44] dq [40] dq [41] dqs# [5] dqs [5] dq [47] dq [43] dq [60] dq [56] dq [57] dqs# [7] dqs [7] dq [63] vss 37 cb [7] cb [3] vss dq [45] dm [5] vss dq [46] dq [42] vss vss dq [61] dm [7] vss dq [62] dq [58] dq [59] vss 36 vss m_ck# [2] dq [36] dq [37] dm [4] dqs# [4] dqs [4] dq [34] dq [35] dq [52] dq [53] dm [6] dqs# [6] dqs [6] dq [50] dq [51] nc vss 35 m_ck# [0] m_ck [2] vss dq [32] dq [33] vss dq [38] dq [39] vss vss dq [48] dq [49] vss dq [54] dq [55] v s s n cn c3 4 ma [0] ba [1] ma [10] ba [0] ras# cs# [0] vss we# cas# odt [0] ma [13] cs# [1] odt [1] vss nc ma [14]a nc nc 33 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc1 vcc3 vcc3 p3 nc nc nc nc nc 32 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 p3 nc nc nc nc nc nc 31 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc3 p3 nc nc vss nc vss nc 30 therm da vsspllx vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 p3 nc nc nc nc nc nc 29 therm dc vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc3 p3 nc nc nc nc nc nc 28 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 stat3 act4 vss s_ stat5 vss s_ act1 27 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc3 stat4 stat6 stat7 act0 stat2 act5 26 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vcc3 act6 stat1 act7 act3 act2 stat0 25 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2 vss vcc1 p2as vcc1 p2as vcc1 p2as vssas vssas vssas vssas 24 vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 vcc1 p2as vcc1 p2as vcc1 p2as txn [3] txp[3] rxn[3] rxp[3] 23 vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2x vss vcc1 p2 vss vcc1 p2as vcc1 p2as vcc1 p2as txn [1] txp[1] rxn[1] rxp[1] 22 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 vssplls clkp nc nc rbias_ sense [0] vssas vssas vssas vssas 21 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2plls0 clkn nc nc rbias [0] txn [0] txp[0] rxn[0] rxp[0] 20 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 vcc1 p8s vcc1 p8s vcc1 p8s txn [2] txp[2] rxn[2] rxp[2] 19 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p8s vcc1 p8s vcc1 p8s vssas vssas vssas vssas 18 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vssds vssds vcc1 p2ds txn [7] txp[7] rxn[7] rxp[7] 17 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vssplls 1 vss nc nc rbias_ sense [1] txn [5] txp[5] rxn[5] rxp[5] 16 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 vcc1 p2plls1 vss nc nc rbias [1] vssas vssas vssas vssas 15 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vssds vcc1 p2ds vssds txn [4] txp[4] rxn[4] rxp[4] 14 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 vcc1 p2ds vssds vcc1 p2ds txn [6] txp[6] rxn[6] rxp[6] 13 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2ds vcc1 p2ds vssds vssas vssas vssas vssas 12 vcc1 p2 vss vcc1 p2 vss vcc1 p2pllp vsspllp vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 gpio [6] gpio [5] gpio [7] gpio [3] gpio [1] 11 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 vcc3 gpio [4] vss gpio [2] vss gpio [0] 10 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 xint# [7] xint# [4] xint# [5] xint# [3] xint# [1] 9 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 vcc3 hs_ led_out nmi0# xint# [6] xint# [0] xint# [2] 8 vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc1 p2 vss vcc3 p3 nmi1# vss hpi# vss hs_ enum# 7 vcc3 p3 vccvio vcc3 vcc3 p3 vccvio vcc3 p3 vccvio vccvio vcc3 vcc3 p3 vccvio vcc3 vcc3 hs_ freq [0] hs_ freq [1] hs_ lstat u0_ rx d u0_ rts# 6 ad [13] vccvio p_ trdy# ad [16] vccvio p_ idsel ad [26] vccvio ad [31] gnt# [0] vccvio gnt# [3] cal [0] vcc3 p3 nc u1_ rx d u0_ tx d u0_ cts# 5 ad [11] par vss p_ frame# ad [20] vss ad [24] ad [30] vss gnt# [1] req# [3] vss p_ bmi warm_ rst# vss u1_ rts# u1_ tx d u1_ cts# 4 ad [12] ad [15] stop# devsel ad [18] ad [22] ad [23] ad [28] ad [27] nc gnt# [2] req# [2] cal [1] nc cal [2] clko [2] clko [3] vss 3 ad [10] cbe# [1] vss pcixca p cbe# [2] vss ad [21] ad [25] vss nc nc vss p_ rst# vss p_ clkout clko [0] vss 2 m66en ad [14] serr# perr# irdy# ad [17] ad [19] cbe# [3] ad [29] req# [0] req# [1] nc p_ rstout# clko [1] clkin vss 1 a. MA[ 14 ] i s onl y n ee ded for 4G B mem o r y supp o r t, ot her wi se th i s p i n rem ai n s N C .

Intel ® 8 134 8—Da ta sheet In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

46 O r d er N um b e r: 31 50 38 - 0 03 US

Table 1 5. In tel ® 8 13 4 8 I / O pr oc e s so r 1 35 7-Lead P ackage—Alph abetical Ball L istin gs (S heet 1 o f 8) B all Signa l Ball S ig n a l Ba ll Signal B all Signa l Ball S ig n a l A 1 – B 1 – C 1 v s s D 1 p _ c lk in E 1 p _ c lk o [ 1 ] A2 – B2 v ss C 2 p_ cl ko [ 0] D2 p_c l ko u t E 2 v ss A3 vs s B3 p_cl ko[3 ] C 3 p_ cl ko [ 2] D3 p_c al [2 ] E 3 n c A4 u 1_ cts # B4 u 1_ txd C 4 u 1_ rt s# D4 vs s E 4 w a rm_ rs t# A 5 u0 _c t s# B 5 u0 _t x d C5 u 1_ rx d D 5 nc E5 v c c 3p 3 A6 u0 _r ts# B6 u0 _r xd C 6 hs_ l sta t D6 h s_f req [1] E 6 hs_ fre q[0 ] A 7 h s _e nu m # B 7 vs s C7 hp i # D 7 v ss E7 n mi 1# A 8 x i nt # [ 2] B 8 xi n t # [ 0] C8 x i n t# [ 6 ] D 8 nm i 0# E8 hs _l e d _o ut A 9 x i nt # [ 1] B 9 xi n t # [ 3] C9 x i n t# [ 5 ] D 9 x i nt # [ 4] E9 xi n t # [ 7] A10 g pi o [ 0] B1 0 v ss C 10 gpi o[2 ] D10 vs s E1 0 gpi o[4 ] A11 g pi o [ 1] B1 1 gpi o[3] C 11 gpi o[7 ] D11 g pi o [ 5] E1 1 gpi o[6 ] A12 vssa s B1 2 vs sas C 12 v ssa s D12 vssa s E1 2 vssd s A13 s_r xp[6 ] B1 3 s_ rxn [6] C 13 s_ txp[ 6] D13 s_ txn [6 ] E1 3 vc c1p2 ds A 1 4 s _ rx p [ 4] B 14 s _r x n[ 4 ] C1 4 s _t x p [4 ] D 1 4 s _t x n[ 4] E 14 v s s ds A15 vssa s B1 5 vs sas C 15 v ssa s D15 vssa s E1 5 r bi as[ 1] A 1 6 s _ rx p [ 5] B 16 s _r x n[ 5 ] C1 6 s _t x p [5 ] D 1 6 s _t x n[ 5] E 16 rb i a s _s e ns e [1 ] A17 s_r xp[7 ] B1 7 s_ rxn [7] C 17 s_ txp[ 7] D17 s_ txn [7 ] E1 7 vc c1p2 ds A18 vssa s B1 8 vs sas C 18 v ssa s D18 vssa s E1 8 v cc1p 8s A 1 9 s _ rx p [ 2] B 19 s _r x n[ 2 ] C1 9 s _t x p [2 ] D 1 9 s _t x n[ 2] E 19 vc c 1 p8 s A 2 0 s _ rx p [ 0] B 20 s _r x n[ 0 ] C2 0 s _t x p [0 ] D 2 0 s _t x n[ 0] E 20 rb i a s [0 ] A21 vssa s B2 1 vs sas C 21 v ssa s D21 vssa s E2 1 r bi as_ sen se[ 0] A22 s_r xp[1 ] B2 2 s_ rxn [1] C 22 s_ txp[ 1] D22 s_ txn [1 ] E2 2 vcc1 p2a s A23 s_r xp[3 ] B2 3 s_ rxn [3] C 23 s_ txp[ 3] D23 s_ txn [3 ] E2 3 vcc1 p2a s A24 vssa s B2 4 vs sas C 24 v ssa s D24 vssa s E2 4 vcc1 p2a s A25 s_ sta t0 B2 5 s_ act 2 C 25 s _a ct3 D25 s_a ct 7 E2 5 s _st at 1 A26 s_a ct 5 B2 6 s_ st at 2 C 26 s _a ct0 D26 s_ sta t7 E2 6 s _st at 6 A27 s_a ct 1 B2 7 v ss C 27 s_s ta t5 D27 vs s E2 7 s_ act 4 A 2 8 nc B 28 nc C2 8 n c D 2 8 nc E 28 nc A 2 9 nc B 29 nc C2 9 n c D 2 9 nc E 29 nc A30 n c B3 0 v ss C 30 nc D30 vs s E3 0 n c A 3 1 nc B 31 nc C3 1 n c D 3 1 nc E 31 nc A 3 2 nc B 32 nc C3 2 n c D 3 2 nc E 32 nc A 3 3 nc B 33 nc C3 3 m a[ 14 ] a D33 n c E3 3 v ss A 3 4 nc B 34 nc C3 4 v s s D 3 4 d q [5 5] E 34 dq [ 5 4] A35 vs s B3 5 n c C 35 dq[5 1] D35 dq[ 50 ] E3 5 dqs [6] A36 – B3 6 v ss C 36 dq[5 9] D36 dq[ 58 ] E3 6 d q[62 ] A37 – B3 7 – C 37 vss D37 dq[ 63 ] E3 7 dqs [7]

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 47 Da tas h e et —I nte l ® 813 48 F1 p_r stou t# G 2 vss H3 p_ gnt #[2] J4 p_gn t#[1 ] K5 p_a d[3 1] F2 p _r st# G 3 p_ req#[ 2] H4 p_ re q#[3] J5 p_gn t#[0 ] K6 vc c3p3 F3 p_ cal [ 1] G 4 vss H5 vccv i o J6 vcc3 p3 K7 vc c1p2 F4 p_bm i G 5 p_g nt # [ 3] H6 vccv i o J7 v ss K8 vss F5 p_ cal [ 0] G 6 vc c3p3 H7 vcc1 p2 J8 vcc1 p2 K9 vc c1p2 F6 vcc3 p3 G 7 vss H8 vs s J9 v ss K 10 vss F7 vcc3 p3 G 8 vc c1p2 H9 vcc1 p2 J 10 vcc1 p2 K 11 vc c1p2 F8 vcc3 p3 G 9 vss H10 vs s J 11 v ss K 12 vss F9 vcc3 p3 G 10 vc c1p2 H11 vcc1 p2 J 12 vcc1 p2 K 13 vc c1p2 F 1 0 vcc3 p3 G 11 vss H12 vs s J 13 v ss K 14 vss F 1 1 vcc3 p3 G 12 vcc1 p2ds H13 vcc1 p2 J 14 vcc1 p2 K 15 vc c1p2 F 1 2 vc c1p2 ds G 13 vcc1 p2ds H14 vs s J 15 vcc 1p2 pl l s1 K 16 vss F 1 3 vssd s G 14 vs sds H15 vs s J 16 vsspl l s1 K 17 vc c1p2 F 1 4 vc c1p2 ds G 15 nc H16 vs s J 17 v ss K 18 vss F 1 5 n c G 16 nc H17 vcc1 p2 J 18 vcc1 p2 K 19 vc c1p2 F 1 6 n c G 17 vs sds H18 vs s J 19 v ss K 20 vss F 1 7 vssd s G 18 vcc1 p8s H19 vcc1 p2 J 20 vcc 1p2 pl l s0 K 21 vc c1p2 F 1 8 vc c1p 8s G 19 vcc1 p8s H20 s _cl kn 0 J 21 vsspl l s0 K 22 vss F 1 9 vc c1p 8s G 20 nc H21 s_cl k p0 J 22 vcc1 p2 K 23 vcc1 p2x F 2 0 n c G 21 nc H22 vs s J 23 v ss K 24 vss F 2 1 n c G 22 vcc1 p2 as H23 vcc1 p2 J 24 vcc1 p2 K 25 vcc1 p2x F 2 2 vcc1 p2a s G 23 vcc1 p2 as H24 vs s J 25 v ss K 26 vss F 2 3 vcc1 p2a s G 24 vcc1 p2 as H25 vcc 1p2 x J 26 v cc1p 2x K 27 vcc1 p2x F 2 4 vcc1 p2a s G 25 vc c3p3 H26 vs s J 27 v ss K 28 vss F 2 5 s_ act 6 G 26 vc c3p3 H27 vcc 1p2 x J 28 v cc1p 2x K 29 vcc1 p2x F 26 s _s ta t4 G2 7 v cc 3 p 3 H 2 8 v ss J2 9 vs s K3 0 v s s F 2 7 s_ st at 3 G 28 vc c3p3 H29 vcc 1p2 x J 30 v cc1p 2x K 31 vcc1 p2x F 2 8 n c G 29 vc c3p3 H30 vs s J 31 v ss K 32 vc c1p8 F 2 9 n c G 30 vc c3p3 H31 vcc 1p2 x J 32 vcc1 p8 K 33 cas # F 3 0 n c G 31 vc c3p3 H32 vcc1 p8 J 33 odt[ 0] K 34 vss F 3 1 n c G 32 vc c3p3 H33 m a[1 3] J 34 v ss K 35 dq[3 5] F 3 2 vcc3 p3 G 33 cs#[1 ] H34 dq[ 48 ] J 35 d q[52 ] K 36 vss F 3 3 odt[ 1] G 34 dq[4 9] H35 dq[ 53 ] J 36 v ss K 37 dq[4 3] F 3 4 v ss G 35 dm[ 6] H36 dq[ 61 ] J 37 d q[60 ] L1 p_cb e#[3] F 3 5 dqs # [ 6] G 36 dm[ 7] H37 dq[ 56 ] K1 p _a d[29 ] L2 p_a d[2 5] F 3 6 v ss G 37 dq[5 7] J 1 p_ re q#[0] K2 v ss L3 p_a d[2 8] F 3 7 dqs # [ 7] H1 p_ req#[ 1] J 2 n c K3 p _a d[27 ] L4 p_a d[3 0] G1 nc H 2 n c J3 nc K 4 vs s L 5 vc c v i o T able 1 5 . In tel ® 8 1 34 8 I /O pr o cesso r 1 3 57 -Le ad P ackage— Al p hab e tical Ball Listings ( She e t 2 o f 8) Ball S ig n a l Ba ll Signal B all Signa l Ball S ig n a l Ba ll Signal

Intel ® 8 134 8—Da ta sheet In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

48 O r d er N um b e r: 31 50 38 - 0 03 US

L6 vccvi o M 7 vcc1 p2 N8 vc c1p2 P 9 vcc1 p2 R1 0 vcc1 p2 L7 vs s M 8 v ss N9 vss P 10 vs s R1 1 v ss L8 vcc1 p2 M 9 vcc1 p2 N 1 0 vc c1p2 P 11 v cc1 p2pl l p R1 2 vcc1 p2 L9 vs s M1 0 v ss N 1 1 vsspl l p P 12 vs s R1 3 v ss L10 vcc1 p2 M1 1 vcc1 p2 N 1 2 vc c1p2 P 13 vcc1 p2 R1 4 vcc1 p2 L11 vs s M1 2 v ss N 1 3 vss P 14 vs s R1 5 v ss L12 vcc1 p2 M1 3 vcc1 p2 N 1 4 vc c1p2 P 15 vcc1 p2 R1 6 vcc1 p2 L13 vs s M1 4 v ss N 1 5 vss P 16 vs s R1 7 v ss L14 vcc1 p2 M1 5 vcc1 p2 N 1 6 vc c1p2 P 17 vcc1 p2 R1 8 vcc1 p2 L15 vs s M1 6 v ss N 1 7 vss P 18 vs s R1 9 v ss L16 vcc1 p2 M1 7 vcc1 p2 N 1 8 vc c1p2 P 19 vcc1 p2 R2 0 vcc1 p2 L17 vs s M1 8 v ss N 1 9 vss P 20 vs s R2 1 v ss L18 vcc1 p2 M1 9 vcc1 p2 N 2 0 vc c1p2 P 21 vcc1 p2 R2 2 v cc1p 2x L19 vs s M2 0 v ss N 2 1 vss P 22 vs s R2 3 v ss L20 vcc1 p2 M2 1 vcc1 p2 N 2 2 vcc1 p2x P 23 vcc 1p2 x R2 4 v cc1p 2x L21 vs s M2 2 v ss N 2 3 vss P 24 vs s R2 5 v ss L22 vcc1 p2 x M2 3 vc c1p2 x N 2 4 vcc1 p2x P 25 vcc 1p2 x R2 6 v cc1p 2x L23 vs s M2 4 v ss N 2 5 vss P 26 vs s R2 7 v ss L24 vcc1 p2 x M2 5 vc c1p2 x N 2 6 vcc1 p2x P 27 vcc 1p2 x R2 8 v cc1p 2x L25 vs s M2 6 v ss N 2 7 vss P 28 vs s R2 9 v ss L26 vcc1 p2 x M2 7 vc c1p2 x N 2 8 vcc1 p2x P 29 vcc 1p2 x R3 0 v cc1p 2x L27 vs s M2 8 v ss N 2 9 vss P 30 vs s R3 1 v ss L28 vcc1 p2 x M2 9 vc c1p2 x N 3 0 vcc1 p2x P 31 vcc 1p2 x R3 2 vcc1 p8 L29 vs s M3 0 v ss N 3 1 vss P 32 vcc1 p8 R3 3 ba [0] L 3 0 v c c 1p 2x M 31 v cc 1 p 2x N 32 v cc 1 p 8 P3 3 r a s # R 34 dq [ 3 2] L31 vs s M3 2 vcc1 p8 N 3 3 cs#[0 ] P 34 dq[ 33 ] R3 5 d q[37 ] L32 vcc1 p8 M3 3 v ss N 3 4 vss P 35 dm [4] R3 6 d q[45 ] L 3 3 w e# M 34 d q[ 3 8] N 35 dq s # [ 4 ] P3 6 d m[ 5 ] R 37 dq [ 4 0] L34 dq[ 39 ] M3 5 dqs[ 4] N 3 6 vss P 37 dq[ 41 ] T1 p_ se rr# L35 dq[ 34 ] M3 6 dq [46 ] N 3 7 d qs#[5] R1 p_pe rr # T2 v ss L36 dq[ 42 ] M3 7 dqs[ 5] P1 p _i r dy# R2 p_ pci xca p T3 p_s top# L37 dq[ 47 ] N1 p_ a d[17 ] P2 p_cb e#[2] R3 p_ devs el # T4 v ss M1 p_ ad[ 19 ] N2 v ss P3 p_a d[1 8] R4 p_ fram e# T5 p _t rdy# M2 p_ ad[ 21 ] N3 p_ a d[22 ] P4 p_a d[2 0] R5 p_ ad[ 16 ] T6 vcc3 p3 M3 p_ ad[ 23 ] N4 v ss P5 v ccvi o R6 vcc3 p3 T7 vcc1 p2 M4 p_ ad[ 24 ] N5 p_i ds el P6 v ccvi o R7 vs s T8 v ss M5 p_ ad[ 26 ] N6 vcc3 p3 P7 vc c1p2 R8 vcc1 p2 T9 vcc1 p2 M6 vccvi o N7 v ss P8 vss R9 vs s T1 0 v ss Table 1 5. In tel ® 8 13 4 8 I / O pr oc e s so r 1 35 7-Lead P ackage—Alph abetical Ball L istin gs (S heet 3 o f 8) B all Signa l Ball S ig n a l Ba ll Signal B all Signa l Ball S ig n a l

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 49 Da tas h e et —I nte l ® 813 48 T1 1 vcc1 p2 U1 2 vc c1p2 V13 vcc1 p2 W 1 4 vcc1 p2 Y1 5 vc c1p2 T1 2 v ss U1 3 vss V14 vs s W 1 5 v ss Y1 6 vss T1 3 vcc1 p2 U1 4 vc c1p2 V15 vcc1 p2 W 1 6 vcc1 p2 Y1 7 vc c1p2 T1 4 v ss U1 5 vss V16 vs s W 1 7 v ss Y1 8 vss T1 5 vcc1 p2 U1 6 vc c1p2 V17 vcc1 p2 W 1 8 vcc1 p2 Y1 9 vc c1p2 T1 6 v ss U1 7 vss V18 vs s W 1 9 v ss Y2 0 vss T1 7 vcc1 p2 U1 8 vc c1p2 V19 vcc1 p2 W 2 0 vcc1 p2 Y2 1 vc c1p2 T1 8 v ss U1 9 vss V20 vs s W 2 1 v ss Y2 2 vss T1 9 vcc1 p2 U2 0 vc c1p2 V21 vcc1 p2 W 2 2 v cc1p 2x Y2 3 vcc1 p2x T2 0 v ss U2 1 vss V22 vs s W 2 3 v ss Y2 4 vss T2 1 vcc1 p2 U2 2 vcc1 p2x V23 vcc 1p2 x W 2 4 v cc1p 2x Y2 5 vcc1 p2x T2 2 v ss U2 3 vss V24 vs s W 2 5 v ss Y2 6 vss T2 3 vc c1p2 x U2 4 vcc1 p2x V25 vcc 1p2 x W 2 6 v cc1p 2x Y2 7 vcc1 p2x T2 4 v ss U2 5 vss V26 vs s W 2 7 v ss Y2 8 vss T2 5 vc c1p2 x U2 6 vcc1 p2x V27 vcc 1p2 x W 2 8 v cc1p 2x Y2 9 vcc3 p3pl l x T2 6 v ss U2 7 vss V28 t he rmdc W 2 9 n c Y3 0 vss T2 7 vc c1p2 x U2 8 vcc1 p2x V29 t her mda W 3 0 v cc1p 2x Y3 1 vcc1 p2x T2 8 v ss U2 9 vs spl l x V30 vs s W 3 1 v ss Y3 2 vc c1p8 T2 9 vc c1p2 x U3 0 vcc1 p2x V31 vcc 1p2 x W 3 2 vcc1 p8 Y3 3 m a[1 ] T3 0 v ss U3 1 vss V32 vcc1 p8 W 3 3 v ss Y3 4 m a[2 ] T3 1 vc c1p2 x U3 2 vc c1p8 V33 ma[ 0] W 3 4 m_ ck[ 0] Y3 5 vss T 32 v c c 1p 8 U 33 b a[ 1] V 3 4 m _c k # [ 0] W 35 d m [ 8] Y 36 cb [ 5] T3 3 ma[ 10 ] U3 4 m _ck [2] V35 vs s W 3 6 dqs [8] Y3 7 c b[1 ] T3 4 v ss U3 5 m_c k#[2] V36 cb[7 ] W 3 7 dqs # [ 8] AA1 p_ ad[ 3] T3 5 dq [36 ] U3 6 c b[3] V37 cb[6 ] Y1 p_a d[8 ] AA2 p_ ad[ 1] T3 6 v ss U3 7 c b[2] W 1 vs s Y2 p_a d[7 ] AA3 p_ ad[ 2] T3 7 dq [44 ] V1 p_m 66 en W 2 vs s Y3 p_a d[5 ] AA4 p_ ad[ 0] U1 p_ ad [14 ] V2 p_a d[1 0] W 3 p_ cbe#[0 ] Y4 p_a d[6 ] AA5 v ccvi o U2 p_ cbe # [ 1] V3 p_a d[1 2] W 4 vs s Y5 p_a d[4 ] AA6 v ccvi o U3 p_ ad [15 ] V4 p_a d[1 1] W 5 p_ ad [9] Y6 vcc vi o AA7 vss U4 p_ par V5 p_a d[1 3] W 6 vcc3 p3 Y7 vcc1 p2 AA8 vc c1p2 U5 vcc vi o V6 vc c3p3 W 7 vs s Y8 v ss AA9 vss U6 vcc vi o V7 vc c1p2 W 8 vcc1 p2 Y9 vcc1 p2 A A1 0 vc c1p2 U 7 vs s V 8 v s s W 9 v ss Y 10 vs s A A 11 v s s U8 vcc1 p2 V9 vc c1p2 W1 0 vcc1 p2 Y1 1 vcc1 p2 A A1 2 vc c1p2 U 9 vs s V 10 v s s W 11 v ss Y 12 vs s A A 13 v s s U 10 vcc1 p2 V1 1 vc c1p2 W1 2 vcc1 p2 Y1 3 vcc1 p2 A A1 4 vc c1p2 U 11 v ss V1 2 vss W1 3 vs s Y1 4 v ss A A1 5 vss T able 1 5 . In tel ® 8 1 34 8 I /O pr o cesso r 1 3 57 -Le ad P ackage— Al p hab e tical Ball Listings ( She e t 4 o f 8) Ball S ig n a l Ba ll Signal B all Signa l Ball S ig n a l Ba ll Signal

Intel ® 8 134 8—Da ta sheet In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

50 O r d er N um b e r: 31 50 38 - 0 03 US

AA16 vcc1 p2 AB1 7 vcc1 p2 AC 18 vc c1p2 A D 19 vcc1 p2 AE2 0 vcc1 p2 AA17 vs s AB1 8 v ss AC 19 vss A D 20 vs s AE2 1 v ss AA18 vcc1 p2 AB1 9 vcc1 p2 AC 20 vc c1p2 A D 21 vcc1 p2 AE2 2 v cc1p 2x AA19 vs s AB2 0 v ss AC 21 vss A D 22 vs s AE2 3 v ss AA20 vcc1 p2 AB2 1 vcc1 p2 AC 22 vcc1 p2x A D 23 vcc 1p2 x AE2 4 v cc1p 2x AA21 vs s AB2 2 v ss AC 23 vss A D 24 vs s AE2 5 v ss AA22 vcc1 p2 x AB2 3 vc c1p2 x AC 24 vcc1 p2x A D 25 vcc 1p2 x AE2 6 v cc1p 2x AA23 vs s AB2 4 v ss AC 25 vss A D 26 vs s AE2 7 v ss AA24 vcc1 p2 x AB2 5 vc c1p2 x AC 26 vcc1 p2x A D 27 vcc 1p2 x AE2 8 v cc1p 2x AA25 vs s AB2 6 v ss AC 27 vss A D 28 vs s AE2 9 v ss AA26 vcc1 p2 x AB2 7 vc c1p2 x AC 28 vcc1 p2x A D 29 v cc1 p2pl l d AE3 0 v cc1p 2x AA27 vs s AB2 8 v ss AC 29 vsspl l d A D 30 vs s AE3 1 v ss AA28 vcc1 p2 x AB2 9 vc c1p2 x AC 30 vcc1 p2x A D 31 vcc 1p2 x AE3 2 vcc1 p8 AA29 vs s AB3 0 v ss AC 31 vss A D 32 vcc1 p8 AE3 3 ma [5] AA30 vcc1 p2 x AB3 1 vc c1p2 x AC 32 vc c1p8 A D 33 vs s AE3 4 v ss AA31 vs s AB3 2 vcc1 p8 AC 33 m a[6 ] A D 34 dq[ 22 ] AE3 5 dqs # [ 2] AA32 vcc1 p8 AB3 3 ma [4] AC 34 dq[2 3] A D 35 dqs[2 ] AE3 6 v ss AA33 m a[ 3] AB3 4 v ss AC 35 dq[1 8] A D 36 dq[ 30 ] AE3 7 dqs # [ 3] A A 3 4 m _c k # [ 1] A B 35 d q[ 1 9] A C3 6 d q [ 26 ] A D3 7 d q s [ 3] A F 1 p_ ad [ 5 5] AA35 m_ ck[1 ] AB3 6 v ss AC 37 dq[3 1] AE1 p_ ad[ 57 ] AF2 p _a d[53 ] AA36 cb[4 ] AB3 7 dq [27 ] AD 1 p_a d[6 1] AE2 vs s AF3 p _a d[51 ] AA37 cb[0 ] AC1 p_ cbe # [ 6] AD 2 p_a d[5 9] AE3 p_ ad[ 58 ] AF4 p _a d[54 ] AB1 p_ ac k64 # AC2 p_ cbe # [ 4] AD 3 p_a d[6 2] AE4 vs s AF5 p _a d[52 ] AB2 vs s AC3 p_ a d[63 ] AD 4 p_a d[6 0] AE5 p_ ad[ 56 ] AF6 vcc vi o AB3 p_ re q64 # AC4 p_ cbe # [ 5] AD 5 v ccvi o AE6 vcc3 p3 AF7 vcc1 p2 AB4 vs s AC5 p_ pa r6 4 AD 6 v ccvi o AE7 vs s AF8 v ss AB5 p_c be#[7 ] AC6 vcc vi o AD 7 vc c1p2 AE8 vcc1 p2 AF9 vcc1 p2 AB6 vcc3 p3 AC7 v ss AD 8 vss AE9 vs s AF 1 0 v ss AB7 vcc1 p2 AC8 vcc1 p2 AD 9 vc c1p2 AE10 vcc1 p2 AF 1 1 vcc1 p2 AB8 vs s AC9 v ss AD 10 vss AE11 vs s AF 1 2 v ss AB9 vcc1 p2 AC1 0 vcc1 p2 AD 11 vc c1p2 AE12 vcc1 p2 AF 1 3 vcc1 p2 AB10 vs s AC1 1 v ss AD 12 vss AE13 vs s AF 1 4 v ss AB11 vcc1 p2 AC1 2 vcc1 p2 AD 13 vc c1p2 AE14 vcc1 p2 AF 1 5 vcc1 p2 AB12 vs s AC1 3 v ss AD 14 vss AE15 vs s AF 1 6 v ss AB13 vcc1 p2 AC1 4 vcc1 p2 AD 15 vc c1p2 AE16 vcc1 p2 AF 1 7 vcc1 p2 AB14 vs s AC1 5 v ss AD 16 vss AE17 vs s AF 1 8 v ss AB15 vcc1 p2 AC1 6 vcc1 p2 AD 17 vc c1p2 AE18 vcc1 p2 AF 1 9 vcc1 p2 AB16 vs s AC1 7 v ss AD 18 vss AE19 vs s AF 2 0 v ss Table 1 5. In tel ® 8 13 4 8 I / O pr oc e s so r 1 35 7-Lead P ackage—Alph abetical Ball L istin gs (S heet 5 o f 8) B all Signa l Ball S ig n a l Ba ll Signal B all Signa l Ball S ig n a l

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 51 Da tas h e et —I nte l ® 813 48 AF 2 1 vcc1 p2 AG 22 vcc1 p2x AH23 vcc 1p2 x AJ 24 v cc1p 2x AK2 5 vcc1 p2x AF 2 2 v ss AG 23 vss AH24 vs s AJ 25 v ss AK2 6 vss AF 2 3 vc c1p2 x AG 24 vcc1 p2x AH25 vcc 1p2 x AJ 26 v cc1p 2x AK2 7 vcc1 p2x AF 2 4 v ss AG 25 vss AH26 vs s AJ 27 v cc1p 2x AK2 8 vss AF 2 5 vc c1p2 x AG 26 vcc1 p2x AH27 vcc 1p2 x AJ 28 v cc1p 2x AK2 9 vcc1 p2x AF 2 6 v ss AG 27 vss AH28 vs s AJ 29 v ss AK3 0 vss AF 2 7 vc c1p2 x AG 28 vcc1 p2x AH29 vcc 1p2 x AJ 30 v cc1p 2x AK3 1 vcc1 p2x AF 2 8 v ss AG 29 vss AH30 vs s AJ 31 v ss AK3 2 vc c1p8 AF 2 9 vc c1p2 x AG 30 vcc1 p2x AH31 vcc 1p2 x AJ 32 vcc1 p8 AK3 3 ma [1 2] AF 3 0 v ss AG 31 vss AH32 vcc1 p8 AJ 33 ma[ 11 ] AK3 4 dq[ 7] AF 3 1 vc c1p2 x AG 32 vc c1p8 AH33 ma[ 9] AJ 34 v ss AK3 5 dq[ 2] AF 3 2 vcc1 p8 AG 33 m a[7 ] AH34 vs s AJ 35 dq[3 ] AK3 6 dq[1 0] AF 3 3 ma [8] AG 34 dq[1 6] AH35 dq[ 20 ] AJ 36 v ss AK3 7 dq[1 5] AF 3 4 dq [17 ] AG 35 dq[2 1] AH36 vs s AJ 37 d q[11 ] AL1 p_a d[3 3] AF 3 5 dm[2 ] AG 36 dq[2 9] AH37 dq[ 28 ] AK1 p _a d[37 ] AL2 vss AF 3 6 dm[3 ] AG 37 dq[2 4] AJ 1 p_ ad[ 43 ] AK2 p _a d[35 ] AL3 p_a d[3 4] A F 37 d q[ 2 5] A H 1 p _ ad [ 45 ] A J2 p _a d [4 1] A K 3 p_ ad [ 3 8] A L 4 v s s A G1 p _a d[ 4 9] A H 2 v s s A J3 p _a d [3 9] A K 4 p_ ad [ 3 6] A L 5 p _ ad [ 32 ] AG 2 p_ ad [47 ] AH3 p_a d[4 6] AJ 4 p_ ad[ 42 ] AK5 vcc vi o AL6 vc c3p3 AG 3 p_ ad [50 ] AH4 vss AJ 5 p_ ad[ 40 ] AK6 vcc vi o AL7 vss AG 4 p_ ad [48 ] AH5 p_a d[4 4] AJ 6 vccv i o AK7 vcc1 p2 AL8 vc c1p2 AG 5 vcc vi o AH6 vc c3p3 AJ 7 vs s AK8 v ss AL9 vss AG 6 vcc vi o AH7 vc c1p2 AJ 8 vcc1 p2 AK9 vcc1 p2 AL1 0 vc c1p2 AG 7 v ss AH8 vss AJ 9 vs s AK1 0 v ss AL1 1 vss AG 8 vcc1 p2 AH9 vc c1p2 AJ1 0 vcc1 p2 AK1 1 vcc1 p2 AL1 2 vc c1p2 AG 9 v ss AH1 0 vss AJ1 1 vs s AK1 2 v ss AL1 3 vss AG1 0 vcc1 p2 AH1 1 vc c1p2 AJ1 2 vcc1 p2 AK1 3 vcc1 p2 AL1 4 vc c1p2 AG1 1 v ss AH1 2 vss AJ1 3 vs s AK1 4 v ss AL1 5 vss AG1 2 vcc1 p2 AH1 3 vc c1p2 AJ1 4 vcc1 p2 AK1 5 vcc1 p2 AL1 6 vc c1p2 AG1 3 v ss AH1 4 vss AJ1 5 vs s AK1 6 v ss AL1 7 vss AG1 4 vcc1 p2 AH1 5 vc c1p2 AJ1 6 vcc1 p2 AK1 7 vcc1 p2 AL1 8 vc c1p2 AG1 5 v ss AH1 6 vss AJ1 7 vs s AK1 8 v ss AL1 9 nc AG1 6 vcc1 p2 AH1 7 vc c1p2 AJ1 8 vcc1 p2 AK1 9 re fcl kn AL2 0 nc AG1 7 v ss AH1 8 vss AJ1 9 vs s AK2 0 re fcl kp AL2 1 vss AG1 8 vcc1 p2 AH1 9 vc c1p2 AJ2 0 vcc1 p2 AK2 1 vcc1 p2 AL2 2 vc c1p2 AG1 9 v ss AH2 0 vss AJ2 1 vs s AK2 2 v ss AL2 3 vss AG2 0 vcc1 p2 AH2 1 vc c1p2 AJ2 2 vcc1 p2 AK2 3 vcc1 p2 AL2 4 vcc1 p2x AG2 1 v ss AH2 2 vss AJ2 3 vs s AK2 4 v ss AL2 5 vss T able 1 5 . In tel ® 8 1 34 8 I /O pr o cesso r 1 3 57 -Le ad P ackage— Al p hab e tical Ball Listings ( She e t 6 o f 8) Ball S ig n a l Ba ll Signal B all Signa l Ball S ig n a l Ba ll Signal

Intel ® 8 134 8—Da ta sheet In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

52 O r d er N um b e r: 31 50 38 - 0 03 US

AL26 vcc1 p2 x AM2 7 vc c1p2 x A N2 8 sc l 2 AP2 9 sd a2 AR3 0 tdo AL27 vcc1 p2 x AM2 8 vcc3 p3 A N2 9 sc l 1 AP3 0 vcc3 p3 AR3 1 t ck AL28 vcc1 p2 x AM2 9 vcc3 p3 A N3 0 vc c3p3 AP3 1 vs s AR3 2 vcc1 p8 AL29 vs s AM3 0 vcc3 p3 A N3 1 vc c3p3 AP3 2 vcc1 p8 AR3 3 m _r st# AL30 vcc1 p2 x AM3 1 vcc3 p3 A N3 2 vc c1p8 AP3 3 cke[1 ] AR3 4 v ss AL31 vs s AM3 2 vcc1 p8 A N3 3 c k e [0 ] AP3 4 dq [0] AR3 5 dq[4 ] AL32 vcc1 p8 AM3 3 ba [2] A N3 4 dq[1 ] AP3 5 dq [5] AR3 6 d q[12 ] AL33 vs s AM3 4 v ss A N3 5 dm[ 0] AP3 6 dq[ 13 ] AR3 7 v ss AL34 dq [6] AM3 5 dqs # [ 0] A N3 6 dq[8 ] AP3 7 dm [1] A T1 – AL35 dqs[0 ] AM3 6 v ss A N3 7 dq[9 ] AR1 vs s A T2 v ss AL36 dq[ 14 ] AM3 7 dqs # [ 1] AP1 d[1 3] AR2 a[0 ] A T3 d[0 ] AL37 dqs[1 ] AN1 d[7 ] AP2 d[5 ] AR3 a [2 3] A T4 d[8 ] AM1 a [2 4] AN2 d[6 ] AP3 d[1 1] AR4 d [3] A T5 a [4] AM2 d[1 4] AN3 d [12 ] AP4 vss AR5 d [4] A T6 a [3] AM3 pwe # AN4 d[2 ] AP5 d[9 ] AR6 a [1 7] A T7 v ss AM4 p o e # AN5 vcc3 p3 AP6 a [16 ] AR7 a [1 5] A T8 a [1] AM5 d[1 0] AN6 d [15 ] AP7 vss AR8 pb _r stout # A T9 a [8] AM6 vcc3 p3 AN7 a[1 1 ] AP8 a [10 ] AR9 a [1 2] A T1 0 v ss AM7 vcc3 p3 AN8 P UR 1 AP9 a [9 ] AR10 pc e#[0] A T1 1 a[ 18 ] AM8 vcc3 p3 AN9 n c AP1 0 vss AR11 a [1 9] A T1 2 vcc1 p2 AM9 vcc3 p3 AN10 a[2 0 ] AP1 1 a [21 ] AR12 vcc1 p2 A T1 3 vsse AM 10 vcc3 p3 AN11 pce#[1 ] AP1 2 vc c1p2 AR13 v sse A T1 4 per n[0 ] AM 11 vcc3 p3 AN12 vcc1 p2 AP1 3 vs se AR14 pet p[0 ] A T1 5 per n[1 ] AM 12 vcc1 p2 AN13 vc c1p2 e AP1 4 p etn [0 ] AR15 pet p[1 ] A T1 6 vsse AM 13 vcc1 p2 e AN14 vc c1p2 e AP1 5 p etn [1 ] AR16 v sse A T1 7 per n[2 ] AM 14 vcc1 p2 e AN15 vc c1p2 e AP1 6 vs se AR17 pet p[2 ] A T1 8 per n[3 ] AM 15 vcc 1p2 ae AN16 vc c1p2 e AP1 7 p etn [2 ] AR18 pet p[3 ] A T1 9 vsse AM 16 vcc 1p2 ae AN17 vc c1p8 e AP1 8 p etn [3 ] AR19 v sse A T2 0 per n[4 ] AM 17 vcc 1p2 ae AN18 vc c1p8 e AP1 9 vs se AR20 pet p[4 ] A T2 1 per n[5 ] AM 18 vcc 1p2 ae AN19 pe_ cal n AP2 0 p etn [4 ] AR21 pet p[5 ] A T2 2 vsse A M1 9 nc A N 2 0 p e _c al p A P 21 pe t n[ 5] A R 2 2 vs s e A T 23 p e rn [ 6] AM 20 n c AN21 vc c1p8 e AP2 2 vs se AR23 pet p[6 ] A T2 4 per n[7 ] AM 21 vcc 1p2 ae AN22 vc c1p8 e AP2 3 p etn [6 ] AR24 pet p[7 ] A T2 5 vsse AM 22 vcc 1p2 ae AN23 vc c1p8 e AP2 4 p etn [7 ] AR25 v sse A T2 6 vc c1p8 e AM 23 vcc 1p2 ae AN24 vc c1p8 e AP2 5 vs se AR26 vcc1 p8 e A T2 7 v cc1p 2x AM 24 vcc 1p2 ae AN25 vc c1p8 e AP2 6 vcc1 p8e AR27 vcc 1p2 x A T2 8 v ss AM 25 vcc1 p8 e AN26 vc c1p8 e AP2 7 vcc1 p2x AR28 sd a0 A T2 9 scl 0 AM 26 vcc1 p8 e AN27 vc c1p2 x AP2 8 vss AR29 sd a1 A T3 0 tm s Table 1 5. In tel ® 8 13 4 8 I / O pr oc e s so r 1 35 7-Lead P ackage—Alph abetical Ball L istin gs (S heet 7 o f 8) B all Signa l Ball S ig n a l Ba ll Signal B all Signa l Ball S ig n a l

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 53 Da tas h e et —I nte l ® 813 48 A T3 1 v ss AU3 vss AU1 2 vcc1 p2 A U 21 per p[5 ] AU30 tdi A T3 2 vcc1 p8 AU4 d[1 ] AU1 3 v sse A U 22 vsse AU31 t rs t# A T3 3 m_ vr ef AU5 a [5 ] AU1 4 p erp[ 0] A U 23 per p[6 ] AU32 vc c1p8 A T3 4 m_ ca l [ 1] AU6 a [7 ] AU1 5 p erp[ 1] A U 24 per p[7 ] AU33 vss A T3 5 m_ ca l [ 0] AU7 a [2 ] AU1 6 v sse A U 25 vsse AU34 vss A T 36 vs s A U 8 a[ 6] A U 17 pe r p [2 ] A U2 6 v cc 1 p 8e A U 3 5 v s s A T3 7 – AU9 a [14 ] AU1 8 p erp[ 3] A U 27 v cc1p 2x AU36 – AU1 – AU10 a [13 ] AU1 9 v sse A U 28 smb dat AU37 – AU2 – AU11 a [22 ] AU2 0 p erp[ 4] A U 29 sm bcl k a . M A[14 ] i s o n l y n eed ed f o r 4G B m emory sup po r t. Wh en 4G B me mory i s not use d t hi s pi n i s NC. T able 1 5 . In tel ® 8 1 34 8 I /O pr o cesso r 1 3 57 -Le ad P ackage— Al p hab e tical Ball Listings ( She e t 8 o f 8) Ball S ig n a l Ba ll Signal B all Signa l Ball S ig n a l Ba ll Signal

Intel ® 8 134 8—Da ta sheet In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

54 O r d er N um b e r: 31 50 38 - 0 03 US

Table 1 6. In tel ® 8 13 4 8 I / O pr oc e s so r 1 35 7-Lead P ackage—Alph abetical Sign al Listin gs (S heet 1 o f 8) Signal Ball Signal B all Signal B all Signal B all Signal B all – A1 b a[0 ] R33 dm[ 5] P3 6 dq[3 3] P3 4 dqs#[6 ] F35 – A2 b a[1 ] U3 3 dm[ 6] G 35 dq[3 4] L35 dqs#[7 ] F37 – A36 b a[2 ] A M 33 dm[ 7] G 36 dq[3 5] K35 dqs#[8 ] W37 – A37 ca s# K33 dm[ 8] W3 5 dq[3 6] T35 d qs[0 ] A L 35 – B1 cb[0 ] AA37 dq[ 0] AP3 4 dq[3 7] R35 d qs[1 ] A L 37 – B37 cb[1 ] Y37 dq[ 1] AN34 dq[3 8] M 34 d qs[2 ] AD 35 – A T1 cb[2 ] U3 7 dq[ 2] AK35 dq[3 9] L34 d qs[3 ] AD 37 – A T37 cb[3 ] U3 6 dq[ 3] AJ3 5 dq[4 0] R37 d qs[4 ] M 35 – A U 1 cb[4 ] AA36 dq[ 4] AR35 dq[4 1] P3 7 d qs[5 ] M 37 – A U 2 cb[5 ] Y36 dq[ 5] AP3 5 dq[4 2] L36 d qs[6 ] E 35 – AU3 6 cb[6 ] V37 dq[ 6] AL34 dq[4 3] K37 d qs[7 ] E 37 – AU3 7 cb[7 ] V36 dq[ 7] AK34 dq[4 4] T37 d qs[8 ] W36 a[0 ] AR2 cke[0 ] AN33 dq[ 8] AN36 dq[4 5] R36 gpi o[0 ] A10 a[1 ] A T8 cke[1 ] AP3 3 dq[ 9] AN37 dq[4 6] M 36 gpi o[1 ] A11 a[2 ] A U 7 cs # [ 0] N33 dq[1 0] AK36 dq[4 7] L37 gpi o[2 ] C 10 a[3 ] A T6 cs # [ 1] G 3 3 dq[1 1] AJ3 7 dq[4 8] H34 gpi o[3 ] B11 a[4 ] A T5 d[ 0] A T3 dq[1 2] AR36 dq[4 9] G 34 gpi o[4 ] E 10 a[5 ] A U 5 d[ 1] AU 4 dq[1 3] AP3 6 dq[5 0] D 35 gpi o[5 ] D 11 a[6 ] A U 8 d[ 2] AN4 dq[1 4] AL36 dq[5 1] C 35 gpi o[6 ] E 11 a[7 ] A U 6 d[ 3] AR4 dq[1 5] AK37 dq[5 2] J3 5 gpi o[7 ] C 11 a[8 ] A T9 d[ 4] AR5 dq[1 6] AG 34 dq[5 3] H35 h pi # C7 a[9 ] AP 9 d[ 5] AP 2 dq[1 7] AF3 4 dq[5 4] E 34 h s_e nu m# A7 a [1 0] AP 8 d[ 6] AN2 dq[1 8] A C 35 dq[5 5] D 34 hs _fr eq[ 0] E6 a [1 1] AN7 d[ 7] AN1 dq[1 9] AB35 dq[5 6] H37 hs _fr eq[ 1] D6 a [1 2] AR9 d[ 8] A T4 dq[2 0] AH35 dq[5 7] G 37 hs_ l ed_ out E8 a [1 3] AU1 0 d[ 9] AP 5 dq[2 1] AG 35 dq[5 8] D 36 hs_ l st at C6 a [1 4] A U 9 d[1 0] AM5 dq[2 2] AD 34 dq[5 9] C 36 m _ca l [0 ] A T35 a[ 15 ] A R 7 d [ 11 ] A P3 d q [ 23 ] A C3 4 d q [ 60 ] J 37 m_ c al [ 1] A T 3 4 a [1 6] AP 6 d[1 2] AN3 dq[2 4] AG 37 dq[6 1] H36 m_c k#[0] V34 a [1 7] AR6 d[1 3] AP 1 dq[2 5] AF3 7 dq[6 2] E 36 m_c k#[1] AA 3 4 a [1 8] A T11 d[1 4] AM2 dq[2 6] A C 36 dq[6 3] D 37 m_c k#[2] U3 5 a [1 9] AR11 d[1 5] AN6 dq[2 7] AB37 dqs#[0 ] AM 35 m_c k[0 ] W34 a [2 0] AN10 dm [0] AN35 dq[2 8] AH37 dqs#[1 ] AM 37 m_c k[1 ] AA 3 5 a [2 1] AP 11 dm [1] AP3 7 dq[2 9] AG 36 dqs#[2 ] AE 35 m_c k[2 ] U3 4 a [2 2] AU1 1 dm [2] AF3 5 dq[3 0] AD 36 dqs#[3 ] AE 37 m_ rst # AR 33 a [2 3] AR3 dm [3] AF3 6 dq[3 1] A C 37 dqs#[4 ] N35 m_v ref A T33 a [2 4] AM1 dm [4] P 35 dq[3 2] R34 dqs#[5 ] N37 m a[0 ] V33

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 55 Da tas h e et —I nte l ® 813 48 ma [1] Y3 3 n c D3 3 p _a d[4] Y5 p_ ad[ 42 ] AJ4 p_ cl ko[3] B3 m a[ 2 ] Y 34 nc E3 p_ ad [ 5 ] Y 3 p _a d [4 3] A J 1 p _ cl k o ut D 2 ma [3] AA3 3 n c E2 8 p _a d[6] Y4 p_ ad[ 44 ] AH5 p_ devs el # R3 m a[ 4 ] A B 33 nc E 29 p_ ad [ 7 ] Y 2 p _a d [4 5] A H 1 p _f r a me # R 4 ma [5] AE3 3 n c E3 0 p _a d[8] Y1 p_ ad[ 46 ] AH3 p_ gnt #[0] J5 ma [6] AC3 3 n c E3 1 p _a d[9] W5 p_ ad[ 47 ] AG2 p_ gnt #[1] J4 ma [7] AG3 3 n c E3 2 p_ ad[ 10 ] V2 p_ ad[ 48 ] AG4 p_ gnt #[2] H3 ma [8] AF 3 3 n c F 1 5 p_ ad[ 11 ] V4 p_ ad[ 49 ] AG1 p_ gnt #[3] G5 m a[ 9 ] A H 33 nc F 16 p _a d [1 2] V 3 p _a d [5 0] A G 3 p _i d s el N 5 ma[ 10 ] T3 3 n c F 2 0 p_ ad[ 13 ] V5 p_ ad[ 51 ] AF3 p_i r dy# P 1 ma[ 11 ] A J 33 n c F 2 1 p_ ad[ 14 ] U1 p_ ad[ 52 ] AF5 p_ m6 6en V1 ma[ 12 ] AK3 3 n c F 2 8 p_ ad[ 15 ] U3 p_ ad[ 53 ] AF2 p_pa r U4 m a [1 3] H 33 nc F 29 p _a d [1 6] R 5 p _a d [5 4] A F 4 p _p a r6 4 A C 5 nc A 28 nc F 30 p _a d [1 7] N 1 p _a d [5 5] A F 1 p _p c i x c ap R 2 n c A2 9 n c F 3 1 p_ ad[ 18 ] P 3 p_ ad[ 56 ] AE5 p_pe rr # R1 n c A3 0 n c G 1 p_ ad[ 19 ] M 1 p_ ad[ 57 ] AE1 p_ re q#[0] J1 nc A 31 nc G 15 p _a d [2 0] P4 p _a d [5 8] A E 3 p _r eq # [ 1 ] H 1 nc A 32 nc G 16 p _a d [2 1] M2 p _a d [5 9] A D 2 p _r eq # [ 2 ] G 3 nc A 33 nc G 20 p _a d [2 2] N 3 p _a d [6 0] A D 4 p _r eq # [ 3 ] H 4 nc A 34 nc G 21 p _a d [2 3] M3 p _a d [6 1] A D 1 p _r eq 6 4# A B 3 n c B2 8 n c H2 p_ ad[ 24 ] M 4 p_ ad[ 62 ] AD3 p_ rst # F2 n c B2 9 n c J2 p_ ad[ 25 ] L2 p_ ad[ 63 ] AC3 p _rs tout # F1 n c B3 1 n c J3 p_ ad[ 26 ] M 5 p _bm i F4 p_ ser r# T1 nc B 32 nc W 29 p _a d [2 7] K 3 p _c a l [ 0] F 5 p_ s to p# T 3 nc B 33 nc A L 19 p _a d [2 8] L 3 p _c a l [ 1] F 3 p _t rd y # T 5 nc B 34 nc A L 20 p _a d [2 9] K 1 p _c a l [ 2] D 3 p b_ rs t o u t# A R 8 nc B 35 nc A M 19 p _a d [3 0] L 4 p _c b e # [ 0] W 3 p ce # [ 0 ] A R 10 nc C 28 nc A M 20 p _a d [3 1] K 5 p _c b e # [ 1] U 2 p ce # [ 1 ] A N 1 1 nc C 29 nc A N 9 p _a d [3 2] A L 5 p _c b e # [ 2] P2 pe _ ca l n A N 1 9 nc C 30 n m i 0# D8 p _a d [3 3] A L 1 p _c b e # [ 3] L 1 p e _c a l p A N 2 0 nc C 31 n m i 1# E7 p _a d [3 4] A L 3 p _c b e # [ 4] A C 2 p er n[ 0 ] A T 1 4 n c C3 2 odt[ 0] J 33 p_ ad[ 35 ] AK2 p_ cbe#[5 ] AC4 pe rn [1] A T15 ma[ 14 ] a C3 3 odt[ 1] F 3 3 p_ ad[ 36 ] AK4 p_ cbe#[6 ] AC1 pe rn [2] A T17 n c D 5 p _a ck6 4# AB1 p_ ad[ 37 ] AK1 p_ cbe#[7 ] AB5 pe rn [3] A T18 n c D2 8 p _a d[0 ] AA4 p_ ad[ 38 ] AK3 p_ cl ki n D1 pe rn [4] A T20 n c D2 9 p _a d[1 ] AA2 p_ ad[ 39 ] AJ3 p_ cl ko[0] C2 pe rn [5] A T21 n c D3 1 p _a d[2 ] AA3 p_ ad[ 40 ] AJ5 p_ cl ko[1] E1 pe rn [6] A T23 n c D3 2 p _a d[3 ] AA1 p_ ad[ 41 ] AJ2 p_ cl ko[2] C3 pe rn [7] A T24 T able 1 6 . In tel ® 8 1 34 8 I /O pr o cesso r 1 3 57 -Le ad P ackage— Al p hab e tical Sign al Li s tings ( She e t 2 o f 8) S i gn al B al l S i gn al B a l l S i g n al B a l l S i g n al B a l l S i g n al B a l l

Intel ® 8 134 8—Da ta sheet In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

56 O r d er N um b e r: 31 50 38 - 0 03 US

pe rp[ 0] AU1 4 s_a ct5 A26 s_ txp [1] C22 v cc1p 2 H23 vc c1p2 P 7 pe rp[ 1] AU1 5 s_a ct6 F2 5 s_ txp [2] C19 v cc1p 2 J 8 vc c1p2 P 9 pe rp[ 2] AU1 7 s_a ct7 D25 s_ txp [3] C23 v cc1p 2 J1 0 vc c1p2 P1 3 p er p [3 ] A U 18 s _c l k n0 H 2 0 s _t x p[ 4 ] C 1 4 vc c 1 p2 J 12 v cc 1 p 2 P 15 pe rp[ 4] AU2 0 s _cl kp 0 H21 s_ txp [5] C16 v cc1p 2 J1 4 vc c1p2 P1 7 pe rp[ 5] AU2 1 s _r xn[0 ] B20 s_ txp [6] C13 v cc1p 2 J1 8 vc c1p2 P1 9 pe rp[ 6] AU2 3 s _r xn[1 ] B22 s_ txp [7] C17 v cc1p 2 J2 2 vc c1p2 P2 1 pe rp[ 7] AU2 4 s _r xn[2 ] B19 sc l 0 A T29 v cc1p 2 J2 4 vc c1p2 R8 pet n[0 ] AP 14 s _r xn[3 ] B23 sc l 1 AN29 v cc1p 2 K7 vc c1p2 R 10 pet n[1 ] AP 15 s _r xn[4 ] B14 sc l 2 AN28 v cc1p 2 K9 vc c1p2 R 12 pet n[2 ] AP 17 s _r xn[5 ] B16 sda 0 AR28 v cc1p 2 K11 vc c1p2 R 14 pet n[3 ] AP 18 s _r xn[6 ] B13 sda 1 AR29 v cc1p 2 K13 vc c1p2 R 16 pet n[4 ] AP 20 s _r xn[7 ] B17 sda 2 AP2 9 v cc1p 2 K15 vc c1p2 R 18 pet n[5 ] AP 21 s_r xp[0 ] A20 smbc l k AU2 9 v cc1p 2 K17 vc c1p2 R 20 pet n[6 ] AP 23 s_r xp[1 ] A22 s mbda t AU2 8 v cc1p 2 K19 vc c1p2 T7 pet n[7 ] AP 24 s_r xp[2 ] A19 tck AR31 v cc1p 2 K21 vc c1p2 T9 pet p[0 ] AR14 s_r xp[3 ] A23 td i AU3 0 v cc1p 2 L8 vc c1p2 T11 pet p[1 ] AR15 s_r xp[4 ] A14 t do AR30 v cc1p 2 L10 vc c1p2 T13 pet p[2 ] AR17 s_r xp[5 ] A16 th er mda V29 v cc1p 2 L12 vc c1p2 T15 pet p[3 ] AR18 s_r xp[6 ] A13 t her mdc V28 v cc1p 2 L14 vc c1p2 T17 pet p[4 ] AR20 s_r xp[7 ] A17 t ms A T30 v cc1p 2 L16 vc c1p2 T19 pet p[5 ] AR21 s_ sta t0 A25 trs t# AU3 1 v cc1p 2 L18 vc c1p2 T21 p e tp [ 6] A R 2 3 s _s t at 1 E 2 5 u0 _c t s # A 5 vc c 1 p2 L 2 0 v cc 1 p 2 U 8 pet p[7 ] AR24 s_ sta t2 B26 u0_ rt s# A6 v cc1p 2 M7 vc c1p2 U1 0 p o e# A M 4 s _s t at 3 F 27 u0 _r x d B 6 vc c 1 p2 M 9 v cc 1 p 2 U 12 p w e# A M 3 s _s t at 4 F 26 u 0_ tx d B 5 vc c 1 p2 M1 1 v cc 1 p 2 U 14 ras# P 33 s_ sta t5 C27 u 1_ cts# A4 v cc1p 2 M 13 vc c1p2 U1 6 rbi a s[0 ] E2 0 s_ sta t6 E26 u1_ rt s# C4 v cc1p 2 M 15 vc c1p2 U1 8 rbi a s[1 ] E1 5 s_ sta t7 D26 u 1_ rxd C5 v cc1p 2 M 17 vc c1p2 U2 0 rbi a s_s ens e[0 ] E2 1 s_ txn [0] D20 u1 _t xd B4 v cc1p 2 M 19 vc c1p2 V7 rbi a s_s ens e[1 ] E1 6 s_ txn [1] D22 v cc1p 2 G8 v cc1p 2 M 21 vc c1p2 V9 r efc l kn AK19 s_ txn [2] D19 v cc1p 2 G 10 v cc1p 2 N8 vc c1p2 V11 ref cl kp AK20 s_ txn [3] D23 v cc1p 2 H7 v cc1p 2 N10 vc c1p2 V13 s_a ct 0 C26 s_ txn [4] D14 v cc1p 2 H9 v cc1p 2 N12 vc c1p2 V15 s_a ct 1 A27 s_ txn [5] D16 v cc1p 2 H11 v cc1p 2 N14 vc c1p2 V17 s_a ct 2 B25 s_ txn [6] D13 v cc1p 2 H13 v cc1p 2 N16 vc c1p2 V19 s_a ct 3 C25 s_ txn [7] D17 v cc1p 2 H17 v cc1p 2 N18 vc c1p2 V21 s_a ct 4 E2 7 s_ txp [0] C20 v cc1p 2 H19 v cc1p 2 N20 vc c1p2 W8 Table 1 6. In tel ® 8 13 4 8 I / O pr oc e s so r 1 35 7-Lead P ackage—Alph abetical Sign al Listin gs (S heet 3 o f 8) Signal Ball Signal B all Signal B all Signal B all Signal B all

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 57 Da tas h e et —I nte l ® 813 48 vcc1 p2 W10 vcc1 p2 AD1 1 vcc1 p2 AJ 12 v cc1p 2a s F 2 2 vcc 1p2 x L3 0 vcc1 p2 W12 vcc1 p2 AD1 3 vcc1 p2 AJ 14 v cc1p 2a s F 2 3 vcc 1p2 x M2 3 vcc1 p2 W14 vcc1 p2 AD1 5 vcc1 p2 AJ 16 v cc1p 2a s F 2 4 vcc 1p2 x M2 5 vcc1 p2 W16 vcc1 p2 AD1 7 vcc1 p2 AJ 18 v cc1p 2a s G2 2 vcc 1p2 x M2 7 vcc1 p2 W18 vcc1 p2 AD1 9 vcc1 p2 AJ 20 v cc1p 2a s G2 3 vcc 1p2 x M2 9 vcc1 p2 W20 vcc1 p2 AD2 1 vcc1 p2 AJ 22 v cc1p 2a s G2 4 vcc 1p2 x M3 1 vcc1 p2 Y7 vcc1 p2 AE8 vcc1 p2 AK7 vcc 1p2 ds E1 3 vcc 1p2 x N22 vcc1 p2 Y9 vcc1 p2 AE1 0 vcc1 p2 AK9 vcc 1p2 ds E1 7 vcc 1p2 x N24 vcc1 p2 Y1 1 vcc1 p2 AE1 2 vcc1 p2 AK1 1 vcc 1p2 ds F 1 2 vcc 1p2 x N26 vcc1 p2 Y1 3 vcc1 p2 AE1 4 vcc1 p2 AK1 3 vcc 1p2 ds F 1 4 vcc 1p2 x N28 vcc1 p2 Y1 5 vcc1 p2 AE1 6 vcc1 p2 AK1 5 vcc 1p2 ds G1 2 vcc 1p2 x N30 vcc1 p2 Y1 7 vcc1 p2 AE1 8 vcc1 p2 AK1 7 vcc 1p2 ds G1 3 vcc 1p2 x P 23 vcc1 p2 Y1 9 vcc1 p2 AE2 0 vcc1 p2 AK2 1 vcc 1p2 e AM1 3 vcc 1p2 x P 25 vcc1 p2 Y2 1 vcc1 p2 AF7 vcc1 p2 AK2 3 vcc 1p2 e AM1 4 vcc 1p2 x P 27 vcc1 p2 AA8 vcc1 p2 AF9 vcc1 p2 AL8 vcc 1p2 e AN13 vcc 1p2 x P 29 vcc1 p2 AA1 0 vcc1 p2 AF 1 1 vcc1 p2 AL1 0 vcc 1p2 e AN14 vcc 1p2 x P 31 vcc1 p2 AA1 2 vcc1 p2 AF 1 3 vcc1 p2 AL1 2 vcc 1p2 e AN15 vcc 1p2 x R2 2 vcc1 p2 AA1 4 vcc1 p2 AF 1 5 vcc1 p2 AL1 4 vcc 1p2 e AN16 vcc 1p2 x R2 4 vcc1 p2 AA1 6 vcc1 p2 AF 1 7 vcc1 p2 AL1 6 vcc1 p2pl l d AD2 9 vcc 1p2 x R2 6 vcc1 p2 AA1 8 vcc1 p2 AF 1 9 vcc1 p2 AL1 8 vcc1 p2pl l p P 11 vcc 1p2 x R2 8 vcc1 p2 AA2 0 vcc1 p2 AF 2 1 vcc1 p2 AL2 2 vcc1 p2p l l s0 J 20 vcc 1p2 x R3 0 vcc1 p2 AB7 vcc1 p2 AG 8 vcc1 p2 AM1 2 vcc1 p2p l l s1 J 15 vcc 1p2 x T23 vcc1 p2 AB9 vcc1 p2 AG1 0 vcc1 p2 AN12 vcc 1p2 x H25 vcc 1p2 x T25 vcc1 p2 AB1 1 vcc1 p2 AG1 2 vcc1 p2 AP 12 vcc 1p2 x H27 vcc 1p2 x T27 vcc1 p2 AB1 3 vcc1 p2 AG1 4 vcc1 p2 AR1 2 vcc 1p2 x H29 vcc 1p2 x T29 vcc1 p2 AB1 5 vcc1 p2 AG1 6 vcc1 p2 A T1 2 vcc 1p2 x H31 vcc 1p2 x T31 vcc1 p2 AB1 7 vcc1 p2 AG1 8 vcc1 p2 AU 12 vcc 1p2 x J 26 vcc 1p2 x U 22 vcc1 p2 AB1 9 vcc1 p2 AG2 0 vc c1p 2a e AM1 5 vcc 1p2 x J 28 vcc 1p2 x U 24 vcc1 p2 AB2 1 vcc1 p2 AH7 vc c1p 2a e AM1 6 vcc 1p2 x J 30 vcc 1p2 x U 26 vcc1 p2 AC 8 vcc1 p2 AH9 vc c1p 2a e AM1 7 vcc 1p2 x K2 3 vcc 1p2 x U 28 vcc1 p2 AC1 0 vcc1 p2 AH11 vc c1p 2a e AM1 8 vcc 1p2 x K2 5 vcc 1p2 x U 30 vcc1 p2 AC1 2 vcc1 p2 AH13 vc c1p 2a e AM2 1 vcc 1p2 x K2 7 vcc 1p2 x V23 vcc1 p2 AC1 4 vcc1 p2 AH15 vc c1p 2a e AM2 2 vcc 1p2 x K2 9 vcc 1p2 x V25 vcc1 p2 AC1 6 vcc1 p2 AH17 vc c1p 2a e AM2 3 vcc 1p2 x K3 1 vcc 1p2 x V27 vcc1 p2 AC1 8 vcc1 p2 AH19 vc c1p 2a e AM2 4 vcc 1p2 x L2 2 vcc 1p2 x V31 vcc1 p2 AC2 0 vcc1 p2 AH21 v cc1p 2a s E2 2 vcc 1p2 x L2 4 vcc 1p2 x W 2 2 vcc1 p2 AD 7 vcc1 p2 AJ8 v cc1p 2a s E2 3 vcc 1p2 x L2 6 vcc 1p2 x W 2 4 vcc1 p2 AD 9 vcc1 p2 AJ 10 v cc1p 2a s E2 4 vcc 1p2 x L2 8 vcc 1p2 x W 2 6 T able 1 6 . In tel ® 8 1 34 8 I /O pr o cesso r 1 3 57 -Le ad P ackage— Al p hab e tical Sign al Li s tings ( She e t 4 o f 8) S i gn al B al l S i gn al B a l l S i g n al B a l l S i g n al B a l l S i g n al B a l l

Intel ® 8 134 8—Da ta sheet In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

58 O r d er N um b e r: 31 50 38 - 0 03 US

vcc1 p2 x W2 8 vcc1 p2 x AG 2 8 v cc1p 8 W3 2 vcc1 p8s G 19 vc c3p3 AM 31 vcc1 p2 x W3 0 vcc1 p2 x AG 3 0 v cc1p 8 Y32 v cc3p 3 E5 vc c3p3 AN5 vcc1 p2 x Y23 vcc1 p2 x AH23 v cc1p 8 AA32 v cc3p 3 F 6 PU R1 AN8 vcc1 p2 x Y25 vcc1 p2 x AH25 v cc1p 8 AB32 v cc3p 3 F 7 vc c3p3 AN 3 0 vcc1 p2 x Y27 vcc1 p2 x AH27 v cc1p 8 A C 32 v cc3p 3 F 8 vc c3p3 AN 3 1 vcc1 p2 x Y31 vcc1 p2 x AH29 v cc1p 8 AD 32 v cc3p 3 F 9 vc c3p3 AP3 0 vcc1 p2 x AA22 vcc1 p2 x AH31 v cc1p 8 A E 32 v cc3p 3 F1 0 vcc3 p3pl l x Y29 vcc1 p2 x AA24 vcc1 p2 x AJ2 4 v cc1p 8 AF3 2 v cc3p 3 F1 1 v ccvi o H5 vcc1 p2 x AA26 vcc1 p2 x AJ2 6 v cc1p 8 AG 32 v cc3p 3 F3 2 v ccvi o H6 vcc1 p2 x AA28 vcc1 p2 x AJ2 7 v cc1p 8 AH32 v cc3p 3 G6 v ccvi o L5 vcc1 p2 x AA30 vcc1 p2 x AJ2 8 v cc1p 8 AJ3 2 v cc3p 3 G 25 v ccvi o L6 vcc1 p2 x AB23 vcc1 p2 x AJ3 0 v cc1p 8 AK32 v cc3p 3 G 26 v ccvi o M6 vcc1 p2 x AB25 vcc1 p2 x AK25 v cc1p 8 AL32 v cc3p 3 G 27 v ccvi o P 5 vcc1 p2 x AB27 vcc1 p2 x AK27 v cc1p 8 AM 32 v cc3p 3 G 28 v ccvi o P 6 vcc1 p2 x AB29 vcc1 p2 x AK29 v cc1p 8 AN32 v cc3p 3 G 29 v ccvi o U5 vcc1 p2 x AB31 vcc1 p2 x AK31 v cc1p 8 AP3 2 v cc3p 3 G 30 v ccvi o U6 vcc1 p2 x AC22 vcc1 p2 x AL24 v cc1p 8 AR32 v cc3p 3 G 31 v ccvi o Y6 vcc1 p2 x AC24 vcc1 p2 x AL26 v cc1p 8 A T32 v cc3p 3 G 32 v ccvi o AA5 vcc1 p2 x AC26 vcc1 p2 x AL27 v cc1p 8 AU3 2 v cc3p 3 J 6 v ccvi o AA6 vcc1 p2 x AC28 vcc1 p2 x AL28 vcc1 p8e AM 25 v cc3p 3 K6 v ccvi o AC6 vcc1 p2 x AC30 vcc1 p2 x AL30 vcc1 p8e AM 26 v cc3p 3 N6 v ccvi o AD5 vcc1 p2 x AD2 3 vcc1 p2 x A M 27 vcc1 p8e AN17 v cc3p 3 R6 v ccvi o AD6 vcc1 p2 x AD2 5 vcc1 p2 x AN27 vcc1 p8e AN18 v cc3p 3 T6 v ccvi o A F6 vcc1 p2 x AD2 7 vcc1 p2 x AP2 7 vcc1 p8e AN21 v cc3p 3 V6 v ccvi o AG5 vcc1 p2 x AD3 1 vcc1 p2 x AR27 vcc1 p8e AN22 v cc3p 3 W6 v ccvi o AG6 vcc1 p2 x AE22 vcc1 p2 x A T27 vcc1 p8e AN23 v cc3p 3 AB6 v ccvi o AJ6 vcc1 p2 x AE24 vcc1 p2 x AU2 7 vcc1 p8e AN24 v cc3p 3 AE6 v ccvi o AK5 vcc1 p2 x AE26 v cc1 p8 H32 vcc1 p8e AN25 v cc3p 3 AH6 v ccvi o AK6 vcc1 p2 x AE28 v cc1 p8 J3 2 vcc1 p8e AN26 v cc3p 3 AL6 vss A3 vcc1 p2 x AE30 v cc1 p8 K32 vcc1 p8e AP2 6 v cc3p 3 AM6 vss A35 vcc1 p2 x AF2 3 v cc1 p8 L32 vcc1 p8e AR26 v cc3p 3 AM7 vss B2 vcc1 p2 x AF2 5 v cc1 p8 M 3 2 vcc1 p8e A T26 v cc3p 3 AM8 vss B7 vcc1 p2 x AF2 7 v cc1 p8 N32 vcc1 p8e AU2 6 v cc3p 3 AM9 vss B10 vcc1 p2 x AF2 9 v cc1 p8 P 32 vcc1 p8 s E 18 v cc3p 3 AM 10 vss B27 vcc1 p2 x AF3 1 v cc1 p8 R32 vcc1 p8 s E 19 v cc3p 3 AM 11 vss B30 vcc1 p2 x A G 2 2 v cc1 p8 T32 vcc1 p8 s F1 8 v cc3p 3 AM 28 vss B36 vcc1 p2 x A G 2 4 v cc1 p8 U3 2 vcc1 p8 s F1 9 v cc3p 3 AM 29 vss C1 vcc1 p2 x A G 2 6 v cc1 p8 V32 vcc1 p8 s G 18 v cc3p 3 AM 30 vss C 34 Table 1 6. In tel ® 8 13 4 8 I / O pr oc e s so r 1 35 7-Lead P ackage—Alph abetical Sign al Listin gs (S heet 5 o f 8) Signal Ball Signal B all Signal B all Signal B all Signal B all

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 59 Da tas h e et —I nte l ® 813 48 vs s C 37 vs s J3 4 vs s M 22 v ss R 15 v ss V 1 0 v ss D 4 v ss J 36 v ss M2 4 vs s R1 7 vs s V12 vs s D7 vs s K 2 vs s M 26 v ss R 19 v ss V 1 4 vs s D 10 vs s K 4 vs s M 28 v ss R 21 v ss V 1 6 vs s D 27 vs s K 8 vs s M 30 v ss R 23 v ss V 1 8 vs s D 30 vs s K 10 vs s M 33 v ss R 25 v ss V 2 0 v ss E 2 v ss K1 2 v ss N2 vs s R2 7 vs s V22 vs s E 33 vs s K 14 vs s N 4 v ss R 29 v ss V 2 4 vs s F 3 4 vs s K 16 vs s N 7 v ss R 31 v ss V 2 6 vs s F 3 6 vs s K 18 vs s N 9 v ss T 2 v ss V 3 0 v ss G 2 v ss K2 0 v ss N13 vs s T4 vs s V35 v ss G 4 v ss K2 2 v ss N15 vs s T8 vs s W1 v ss G 7 v ss K2 4 v ss N17 vs s T10 vs s W2 v ss G 9 v ss K2 6 v ss N19 vs s T12 vs s W4 vs s G 11 vs s K 28 vs s N 2 1 v ss T 1 4 v ss W 7 v ss H8 v ss K3 0 v ss N23 vs s T16 vs s W9 vs s H 10 vs s K 34 vs s N 2 5 v ss T 1 8 v ss W 11 vs s H 12 vs s K 36 vs s N 2 7 v ss T 2 0 v ss W 13 vs s H 14 vs s L 7 vs s N 2 9 v ss T 2 2 v ss W 15 vs s H 15 vs s L 9 vs s N 3 1 v ss T 2 4 v ss W 17 vs s H 16 vs s L 11 vs s N 3 4 v ss T 2 6 v ss W 19 vs s H 18 vs s L 13 vs s N 3 6 v ss T 2 8 v ss W 21 vs s H 22 vs s L 15 vs s P8 v ss T 3 0 v ss W 23 vs s H 24 vs s L 17 vs s P1 0 v ss T 3 4 v ss W 25 vs s H 26 vs s L 19 vs s P1 2 v ss T 3 6 v ss W 27 vs s H 28 vs s L 21 vs s P1 4 v ss U 7 v ss W 31 vs s H 30 vs s L 23 vs s P1 6 v ss U 9 v ss W 33 v ss J7 v ss L2 5 v ss P 18 vs s U 11 vs s Y8 v ss J9 v ss L2 7 v ss P 20 vs s U 13 vs s Y10 v ss J11 v ss L2 9 v ss P 22 vs s U 15 vs s Y12 v ss J13 v ss L3 1 v ss P 24 vs s U 17 vs s Y14 vs s J 1 7 vs s M8 vs s P2 6 v ss U1 9 v ss Y 1 6 v ss J19 v ss M1 0 v ss P 28 vs s U 21 vs s Y18 v ss J23 v ss M1 2 v ss P 30 vs s U 23 vs s Y20 vs s J 2 5 vs s M 14 vs s R 7 v ss U2 5 v ss Y 2 2 vs s J 2 7 vs s M 16 vs s R 9 v ss U2 7 v ss Y 2 4 v ss J29 v ss M1 8 v ss R1 1 vs s U 31 vs s Y26 vs s J 3 1 vs s M 20 vs s R 13 v ss V 8 v ss Y 2 8 T able 1 6 . In tel ® 8 1 34 8 I /O pr o cesso r 1 3 57 -Le ad P ackage— Al p hab e tical Sign al Li s tings ( She e t 6 o f 8) S i gn al B al l S i gn al B a l l S i g n al B a l l S i g n al B a l l S i g n al B a l l

Intel ® 8 134 8—Da ta sheet In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

60 O r d er N um b e r: 31 50 38 - 0 03 US

vss Y30 vss AC21 vss AF1 4 vss AJ7 vss A L 33 vss Y35 vss AC23 vss AF1 6 vss AJ9 vss AM 34 vss AA7 vss AC25 vss AF1 8 vss AJ1 1 vss AM 36 vss AA9 vss AC27 vss AF2 0 vss AJ1 3 vss AP 4 vss AA11 vss AC31 vss AF2 2 vss AJ1 5 vss AP 7 vss AA13 vss AD8 vss AF2 4 vss AJ1 7 vss AP1 0 vss AA15 vss A D 10 vss AF2 6 vss AJ1 9 vss AP2 8 vss AA17 vss A D 12 vss AF2 8 vss AJ2 1 vss AP3 1 vss AA19 vss A D 14 vss AF3 0 vss AJ2 3 vss AR1 vss AA21 vss A D 16 vss AG7 vss AJ2 5 vss AR 34 vss AA23 vss A D 18 vss AG9 vss AJ2 9 vss AR 37 vss AA25 vss A D 20 vss AG 11 vss AJ3 1 vss A T2 vss AA27 vss A D 22 vss AG 13 vss AJ3 4 vss A T7 vss AA29 vss A D 24 vss AG 15 vss AJ3 6 vss A T10 vss AA31 vss A D 26 vss AG 17 vss AK8 vss A T28 vss AB2 vss A D 28 vss AG 19 vss A K 10 vss A T31 vss AB4 vss A D 30 vss AG 21 vss A K 12 vss A T36 vss AB8 vss A D 33 vss AG 23 vss A K 14 vss AU3 vss AB10 vss AE2 vss AG 25 vss A K 16 vss AU3 3 vss AB12 vss AE4 vss AG 27 vss A K 18 vss AU3 4 vss AB14 vss AE7 vss AG 29 vss A K 22 vss AU3 5 vss AB16 vss AE9 vss AG 31 vss A K 24 v ssa s A12 vss AB18 vss A E 11 vss AH2 vss A K 26 v ssa s A15 vss AB20 vss A E 13 vss AH4 vss A K 28 v ssa s A18 vss AB22 vss A E 15 vss AH8 vss A K 30 v ssa s A21 vss AB24 vss A E 17 vss AH10 vss AL2 v ssa s A24 vss AB26 vss A E 19 vss AH12 vss AL4 v ssa s B12 vss AB28 vss A E 21 vss AH14 vss AL7 v ssa s B15 vss AB30 vss A E 23 vss AH16 vss AL9 v ssa s B18 vss AB34 vss A E 25 vss AH18 vss A L 11 v ssa s B21 vss AB36 vss A E 27 vss AH20 vss A L 13 v ssa s B24 vss AC7 vss A E 29 vss AH22 vss A L 15 v ssa s C 12 vss AC9 vss A E 31 vss AH24 vss A L 17 v ssa s C 15 vss AC11 vss A E 34 vss AH26 vss A L 21 v ssa s C 18 vss AC13 vss A E 36 vss AH28 vss A L 23 v ssa s C 21 vss AC15 vss AF 8 vss AH30 vss A L 25 v ssa s C 24 vss AC17 vss AF1 0 vss AH34 vss A L 29 v ssa s D 12 vss AC19 vss AF1 2 vss AH36 vss A L 31 v ssa s D 15 Table 1 6. In tel ® 8 13 4 8 I / O pr oc e s so r 1 35 7-Lead P ackage—Alph abetical Sign al Listin gs (S heet 7 o f 8) Signal Ball Signal B all Signal B all Signal B all Signal B all

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 61 Da tas h e et —I nte l ® 813 48 vss as D1 8 vsse AP 13 vsse AR2 5 vsse AU 22 xi n t#[0 ] B8 vss as D2 1 vsse AP 16 vsse A T1 3 vsse AU 25 xi n t#[1 ] A9 vss as D2 4 vsse AP 19 vsse A T1 6 vs spl l d AC2 9 xi n t#[2 ] A8 vssds E1 2 vsse AP 22 vsse A T1 9 vs spl l p N11 xi n t#[3 ] B9 vssds E1 4 vsse AP 25 vsse A T2 2 v sspl l s0 J 21 xi n t#[4 ] D9 vssds F13 vsse AR1 3 vsse A T2 5 v sspl l s1 J 16 xi n t#[5 ] C9 vssds F17 vsse AR1 6 vsse AU 13 vsspl l x U 29 xi n t#[6 ] C8 vssds G1 4 vsse AR1 9 vsse AU 16 war m_ rst # E4 xi n t#[7 ] E9 vssds G1 7 vsse AR2 2 vsse AU 19 w e # L3 3 a . M A[14 ] i s o n l y n eed ed f o r 4G B m emory sup po r t. Wh en 4G B me mory i s not use d t hi s pi n i s NC. T able 1 6 . In tel ® 8 1 34 8 I /O pr o cesso r 1 3 57 -Le ad P ackage— Al p hab e tical Sign al Li s tings ( She e t 8 o f 8) S i gn al B al l S i gn al B a l l S i g n al B a l l S i g n al B a l l S i g n al B a l l

Inte l ® 81 348— E le ctr ical Spec i f icat ion s In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

62 O r d er N um b e r: 31 50 38 - 0 03 US

4.0 E lect rical Specif ication s

Table 1 7. Abso lute M axi m u m Ratin gs P a r a m e t e r M a x i m um R a t i ng Notice: This data sheet contains informa- tion on products in the design phase of development. Do not finalize a design with this informa- tion. Revised information will be published when the product becomes available. The specifica- tions are subject to change without notice. Contact your local Intel rep- resentative before finalizing a design. S to r ag e t e mp e r at u re –10 ° C t o + 4 5° C Su ppl y vol ta ge V CC3P3 wrt . V SS – 0.5 V to +4.1 V Su ppl y vol ta ge V CC1P8 S w r t. V SS AS – 0.5 V to +2.5 V Su ppl y vol ta ge V CC1P8 E wrt . V SS E – 0.5 V to +2.5 V Su ppl y vol ta ge V CC1P8 wrt . V SS – 0.5 V to +2.5 V Su ppl y vol ta ge V CCV IO wrt . V SS – 0.5 V to +4.1 V Su ppl y vol ta ge V CC1P2 X wrt . V SS – 0.5 V to +1.8 V Su ppl y vol ta ge V CC1P2 wrt . V SS – 0.5 V to +1.8 V Su ppl y vol ta ge V CC1P2 AE wrt . V SS E – 0.5 V to +1.8 V Su ppl y vol ta ge V CC1P2 E wrt . V SS E – 0.5 V to +1.8 V Su ppl y vol ta ge V CC1P2 AS w r t. V SSA S – 0.5 V to +1.8 V Su ppl y vol ta ge V CC1P2 DS w r t. V SS DS – 0.5 V to +1.8 V V o l t ag e on any bal l wr t. V SS –0. 5 V to V CCP +0 . 5 V † WA RNIN G: Str essin g t he device be yo n d t he “Absolut e Ma ximu m Ra tin gs” ma y ca use per ma nen t dam age . Th ese ar e str ess ra ting s only. Ope ra tion beyond th e “Oper at ing Condit io n s” is not re comme nde d a nd e xt ende d e xposur e be yond the “Ope ra tin g Cond itions” ma y a ffe ct d evice re liabilit y.

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 63 Elect rica l S p ecifica tions—Intel ® 81 348 T able 1 8 . O perat i n g Co nd i t i o n s Sym b ol P ar amet er M in imum M ax imu m U nits Notes V CC3P3 3 .3 V suppl y vol tag e for PC I - X c at egory 2 si gn al s a nd g ene ral pu rpose I/Os 3.0 3.6 V V CC1P8 S 1 .8 V suppl y vol tag e for stora ge in t e r f a c e 1.71 1.89 V V CC1P8 E 1 .8 V suppl y vol tag e for PC I E xpre ss* in t e r f a c e 1.71 1.89 V V CC1P8 1 .8 V suppl y vol tag e for DD R2 SDRAM me m o ry i n te rf ac e I / O s 1.71 1.89 V V CCV IO 3 .3 V suppl y vol tag e for PC I - X c at egory 1 s i gna l s 3.0 3.6 V V CC1P2 X 1 .2 V suppl y vol tag e for I n tel XS c al e ® pr o c e s so rs 1.164 1.236 V V CC1P2 1 .2 V suppl y vol tag e for most di gi ta l l ogi c 1.164 1.236 V V CC1P2 E 1 .2 V suppl y vol tag e for PC I E xpre ss* i n te rfa ce di gi ta l l ogi c 1.164 1.236 V V CC1P2 AE 1 .2 V suppl y vol tag e for PC I E xpre ss* i n te rfa ce an al og l ogi c 1.164 1.236 V V CC1P2 AS 1 .2 V suppl y vol tag e for stora ge i n te rfa ce an al og l ogi c 1.164 1.236 V V CC1P2 DS 1 .2 V suppl y vol tag e for stora ge i n te rfa ce di gi ta l l ogi c 1.164 1.236 V V CC1P2 PLL S 0 1 .2 V suppl y vol tag e for stora ge P LL 0 1.164 1.236 V V CC1P2 PLL S 1 1 .2 V suppl y vol tag e for stora ge P LL 1 1.164 1.236 V V CC1P2 PLL P 1 .2 V suppl y vol tag e for PC I - X PL L 1.164 1.236 V V CC1P2 PLL D 1 .2 V suppl y vol tag e for DD R2 SDRAM P LL proces sor l ogi c P LL. 1.164 1.236 V V CC3P3 PLL X 3 .3 V suppl y vol tag e for proce ssor l ogi c PLL 3.0 3.6 V M_VREF M em o r y I/O re fer en ce vol ta ge 0.49VCC1P8 0.51VCC1P8 V T C C ase t empe rat ure u nder bi a s 01 0 0 ° C

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1. 1 V CCPLL Pin R equ irements T o re du ce cl oc k jitter , th e V C C 1P 2P L L D , V CC 1 P2PLLP , an d V CC 3 P3PLLX , V CC1P2PLLS0 an d V CC1P2PLLS1 ba lls fo r th e ph a se-l oc k l oo p (PLL) c ircu its are iso la ted on th e pa ck age . The l ow -pas s fi lters, as s h ow n i n the f ol lo wi ng fi gu res , redu c e no is e-in du c ed c lo ck jitter a nd it s e ff e ct s on t im i ng r e l at io nsh ip s i n s y st e m d e si g n. Thi s p ar a graph p ertai ns to t h e V CC1P2PLLD , V CC1P2PLLP , V CC 3P3 PLLX fil t e rs. Th e fi lter co mp on en ts mu st be ab le t o h an dl e a DC c urre nt o f 30 m A. Us e a s hi eld ed type in du cto r to m in im ize ma gn etic pic ku p. The tota l se ries res is t a n ce fro m th e bo a rd V CC pla ne (be fore the fil t e r) to t h e VCCP LL ba ll m u st be les s t h a n 1. 5 o hm (in cl ud in g co mp on en t a nd tr a ce res ista nc e). Th e t o tal se ries res is t a n ce fro m t h e bo ard VC C pl an e (befo re t h e filter) t o th e to p p late of t h e ca pac ito r mu s t be g reate r t h a n 0 . 35 o hm (in clu di ng c o mp on en t an d tr ac e res is t a n ce). Th e n od es c on n ec t i ng VCCP LL an d V SSP LL t o th e c ap ac itor mu st be as s ho rt a s p os si ble (les s th an 0. 1 W). VCC PLL an d VS SP LL m us t be r ou t ed cl os e t o ea ch ot he r t o m in i mi ze l oop ar e a. Th e V SS PL L b al l s m us t be c onn ec t e d t o t he f il t e r onl y and no t t o an y ot h er g r oun d, a s s how n i n Fi gu r e 7 an d Fig ure 9 . The in du cto r a nd ca pa cito r mu s t be p la ced cl os e to ea ch o the r . A ny dis cre t e resi sto r m u st be p lac ed b etwe en th e V CC bo ard pla ne a n d the i nd uc tor . I f th e tr ac e a nd c om po ne nt r e si st anc e i s h ig h e no ugh , a d i sc r et e r e si st or mi g ht no t be r e qu ir e d . Thi s p ar a graph p ertai ns to t h e V CC1P2PLLS0 , V CC1P2PLLS1 fil t e rs. Th e re co mm en ded filter fo r the PLL s u ppli es is sh o wn i n Fi gu r e 8 . T he pu rpo se o f th is filter is t o a ch ie v e a t lea st 10 dB re j e ctio n o f fre qu en cie s b etw een 1 a nd 20 MHz . Th e c urre nt d r aw fo r th e IC is les s th an 85 mA . Th e bo a rd’ s su ppl y di stribu tio n sys tem mu st e ns u re tha t the min im um vo ltage in to t h e filter is e qu al to o r g reate r t h a n 1 . 14 V . Th e fi lter co mp on en ts are sel ecte d to ac hi eve a c orn er f requ en c y o f 100 KHz. Th e s eri es r e s is t a nce k e ep s t he Q of t hi s r e so nan t ci r c ui t sa fe l y be l ow un it y f o r a l l c omp on en t v ar i a t i ons . The byp as s c ap ac itor mu st be pl ac ed a s c lo s e to t h e su ppl y pi ns as po s sib le. Th e s eri es i m pe d an ce s t o bot h t h e s up pl y pi n a nd t he PC B ana l og g r ou nd pl an e m us t b e a n or d e r of ma gn itud e lo w er th an th e E SR an d E S L sp eci fied fo r the ca pa ci t o r . The S0/S 1 PLLs ha v e d edi ca t e d in tern al s up plie s, so t h e V SS PLLS0/S 1 p in s mu s t be s o lde red di rectly to t h e an al og gro u nd pla n e o f th e P CB. Figu re 7 . V CC3P3PLLX Lo w -Pass F i lter 3.3V (Board Plane) 22 µF ±20%, ESR < 0.3, 4.7 uH, ±25% VSSPLLX 6.3 V, ESL < 2.5nH (Not connected to board ground) VCC3P3PLLX

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 65 Elect rica l S p ecifica tions—Intel ® 81 348 Figu r e 8 . V C C1P2PLL S0 , V C C1P2PLL S1 Low -P ass Filter Figu r e 9 . V C C1P2PLL D , V CC 1P2 PLLP L o w -Pass Fil t e r 0.1 Ω, ±5% (Board Plane) 22 µF, ±20%, ESR < 0.3, 120 nH, ±20% RDCMAX < 0.3 1.2V VSSPLLS0/1 45 mA 6.3 V, ESL < 2.5nH (Board ground) VCC1P2PLLS0/1 (Board Plane) 22 µF, ±20%, ESR < 0.3, 4.7 uH, ±25% 1.2V 6.3 V, ESL < 2.5nH (Not connected to board ground) VSSPLLD/ VSSPLLP VCC1P2PLLD/ VCC1P2PLLP

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4 .2 Targeted D C S pec ifica tions Table 1 9. DC Char acter i s tics S ymb ol P ara mete r M inimu m M ax i mum U nits N ote s V IL1 I n put Low V o l t age (G en eral Pur pose). - 0.3 0.3 V CC3 P3 V 2 V IH 1 I np u t H i g h V o l t ag e ( G en er al Pu rp o se ) . 2. 0 V CC 3 P 3 + 0.3 V 2 V IL2 I n put Low V o l t age (P CI ) . - 0.5 0.3 V CC3 P3 V V IL3 In p u t L o w Volt a g e ( P C I-X ) . - 0 . 5 0 .3 5 V CC 3 P3 V V IH 3 I n put Hi gh V ol ta ge (PC I - X/PC I ). 0.5 V CC3P3 V CC 3 P 3 + 0.5 V V IL4 I n put Low V o l t age (D DR2 SDR AM). - 0.3 M_ VR E F - 0. 12 5 V V IH 4 I n put Hi gh V ol ta ge (DD R2 SDRAM ). M_VREF + 0. 1 25 V CC 1 P 8 + 0.3 V V OL 1 Output Low Voltage (General Purpose). –0 . 4 V I OL = 1 0 m A V OH 1 Output High Voltage (General Purpose). 2. 6 – V I OH = -1 0 mA V OL 2 Output Low Voltage (PCI-X). –0 . 1 V CC3 P3 V I OL = 1.50 mA V OH 2 Output High Voltage (PCI-X). 0.9 V CC3P3 – V I OH = -0 . 5 0 mA V OL 3 Output Low Voltage (DDR2 SDRAM driver set to 21Ω).

0.28 V I OL = 1 1 m A

(DDR2 SDRAM driver set to 21Ω).

1.42 V I OH = -1 1 mA

(DDR2 SDRAM driver set to 50Ω).

0.28 V I OL = 5 m A

(DDR2 SDRAM driver set to 50Ω).

1.42 V I OH = -5 mA

I n put Le aka ge Cur re nt for G en era l Pu rpose pi n s whe n i n te rna l pu l l up re si stor s ar e n ot en ab l ed. ±5 µA 0 ≤ V IN ≤ V CC3 P3 I LI 2 I n put Le aka ge Cur re nt for P CI - X p i ns wh en i n ter na l pu l l up res i s tors ar e n o t en abl e d. ±10 µA 0 ≤ V IN ≤ V CC3P3 ( Ca t . 0 ≤ V IN ≤ V CCV IO (C a t . I LI 3 I n put Le aka ge Cur re nt for D DR 2 pi n s wh en i n ter na l pu l l up res i s tors ar e n o t en abl e d. ±2 µA 0 ≤ V IN ≤ V CC1 P8 R GP I n te rna l pu l l up re si stor v a l ue for Gen era l Pu rp o se p i ns . 28 . 5 3 8.7 ΚΩ 1 R PCIX I n te rna l pul l u p re si stor val u e for P CI - X pi n s. 5 . 9 8.1 ΚΩ 1 C GP General Purpose pin Capacitance. 1 4.5 pF 1 C PCIX PCI-X pin Capacitance. 1 4.5 pF 1 C DDR2 DDR2 pin Capacitance. 1 4.5 pF 1 L PI N Ba l l I nd uct an ce. 11 2 n H 1 Note s: 1. N o t t e st e d, gu ar an te ed b y d e s i g n. 2 . G en era l Pu rpose si gn al s i n cl ud e a l l si gn al s t ha t ar e n o t pa rt o f th e D DR 2, P CI - X an d P CI -E xpre ss i n te rfa ces o r t he S t orage Tx /Rx pai r s a nd a na l o g pi ns . 3 . Inpu t l e ak age cur re nts i ncl u de hi -Z out put l ea kag e for al l bi -di re cti on al bu ffe rs w i t h tri - sta te outp uts.

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 67 Elect rica l S p ecifica tions—Intel ® 81 348 T able 2 0 . I CC Char acter i s ti cs S ymb ol P ar amet er Typ M a x Units Notes I cc1 2 A c ti ve (Po we r Su ppl y) Pow e r S u ppl y Cur re nt : Storag e P HY , P CI E xpre ss, I n tel XScal e ® mi c hroa rch i tec tur e:

• 8 0 0 M H z
• 1 20 0M H z 7.83 8.39 A 1 , 2 , 4 I cc1 8 A c ti ve (Po we r Su ppl y) Pow e r S u ppl y Cur re nt : Storag e P HY I / Os, PCI Ex pre ss I / Os, DDR -I I (5 33 ) 1.71 A 1 , 2 , 4 I cc3 3 A c ti ve (Po we r Su ppl y) P o we r Su p p ly C u r r e n t : P C I, P B I, G P IO, P C I-X I/ O s 0.69 A 1 , 2 I cc1 2 A c ti ve (The rma l ) The rm al C ur ren t: Storage PHY , P CI E xpr ess, I n te l XScal e ® m i croar chi t ect ur e:
• 8 0 0 M H z
• 1 20 0M H z 5.55 6.81 A 1 , 3 , 4 I cc1 8 A c ti ve (The rma l ) The rm al C ur ren t: Storage PHY I /Os, PC I E xpre ss I/Os, DD R -I I (5 33 ) 1.40 A 1 , 3 , 4 I cc3 3 A c ti ve (The rma l ) The rm al C ur ren t: PC I , PBI , G PIO , P C I-X I/ O s 0.60 A 1 , 3 No t e s : 1. Me asu red wi th th e de vi ce o p erat i ng an d out put s l oade d t o t he te st condi t i o n i n F i gu re 17 , “ AC T e st Load f o r a l l Si gna l s E xcept PC I , PC I -Exp res s a nd D DR2 a nd St orage PHY ” o n pa ge 8 2 . 2. I cc Ac ti ve (Po we r Su ppl y) v a l ue i s pr o vi d ed f o r sel e cti n g t he syst em pow e r s uppl y . Thi s i s bas ed o n th e worst cas e da ta pat te rns an d skew ma te ri a l at th e fol l o wi n g wo r st case vo l t ag es: Vcc 33 = 3 . 6 3 V , V c c 1 8 = 1. 89 V , V c c1 2 = 1 . 24 V a n d a mb i e nt te m pe r a tu re = 55 C. 3. I cc Act i ve ( Ther ma l ) val u e i s provi ded for se l ect i ng t he syst em th er mal desi gn power (TDP ). Thi s i s ba sed o n th e f o l l owi ng typi ca l vol ta ges: Vcc3 3 = 3.3 V , Vcc1 8 = 1.8V , Vcc1 2 = 1.2 V an d amb i ent t empe rat ure = 5 5C . 4. The Cus tomer Refe ren ce Bo a rds use a 1.2 V swi tch i ng reg ul at or for al l the 1 . 2 V su ppl i es (Vcc1 p2, Vcc1 p2 x, Vcc1p 2e, Vcc 1p2 ds, Vcc1 p2a e, Vcc1 p2 as) an d a 1.8 V swi tch i ng reg ul at or f o r al l 1 . 8 V s uppl i e s: (Vc c1p8 , Vcc1 p8e , Vcc 1p8 s).

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4 .3 Targeted AC Sp e cific ations 4. 3. 1 Clo c k S ig n al Ti mi ng s Table 2 1. PCI C l o ck T i m ing s S ymb ol Par ame ter PCI-X 133 P CI-X 10 0 PCI-X 6 6 PC I 66 P CI 33 Un i t s N o t e s T C1 PC I Cl o c k C y c l e T i m e Ji t ter Cl a ss 1 7 . 5 1 1 1 0 1 5 1 52 21 52 5 3 0 5 0 n s 1 T C2 PC I Cl o c k C y c l e T i m e T CH1 P CI c l ock Hi gh T i m e 2.5 3 5.5 5.5 1 0 n s TCL1 P CI c l ock Low Ti me 2.5 3 5.5 5.5 1 0 n s P CI c l ock Peri od Ji tt er 1 25 -12 5 12 5 - 12 5 20 0 -2 00 20 0 -2 00 30 0 -3 00 ps 3 TSR1 P CI c l ock Sl ew Rat e 1.5 4 1.5 4 1.5 4 1.5 4 1 4 V/ns 2 PCI Spr ead S p ect rum R e quireme n t s f mo d P CI c l ock modul a ti on fr equ enc y 3 0 33 30 3 3 30 33 30 3 3 KHz f sp read P CI c l ock fr eque ncy spr ea d - 10- 10 - 1 0 - 1 0 % PCI Ou t put Clock s P CI out pu t cl ock skew 2 50 3 50 35 0 35 0 35 0 ps P CI out pu t cl ock per i o d ji tt er 10 0 - 1 00 1 50 -1 50 1 50 - 15 0 1 50 - 15 0 1 50 - 15 0 p s 4, 5 Notes : 1 . The cl ock fre que ncy may not cha nge beyond th e sp rea d-sp ect rum l i mi t s e xcept whi l e P_RS T# or WA RM _ RST# is a sser te d. 2 . Thi s sl ew ra te mu st be m et acr oss t he mi ni m um pea k -to-pe ak po r ti on o f th e c l o ck w a veform . 3 . Per i o d ji tt er i s t he devi a ti on bet ween an y si n gl e pe ri od of the cl ock and th e a verage pe ri od of t he cl ock. 4 . I f a ji tt er cl ass 2 i npu t cl ock i s u sed, out put cl ocks can not sup po r t ji tt er cl ass 1. 5 . The de vi at i o n be twee n a ny s i ngl e per i o d o f th e c l o ck an d t he avera ge p eri od of th e cl ock.

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 69 Elect rica l S p ecifica tions—Intel ® 81 348 T able 2 2 . PC I Exp ress Clo ck Tim ings Sym b ol P ara mete r Min. Nom. M ax . Un its Note s TF 2 P CI Expr ess * C l o ck Freq uen cy 10 0 M Hz 4 TC2 P CI Expr ess * C l o ck Cycl e Ti me 9.87 2 n s D F0 Fre que ncy V a ri a ti on -30 0 3 00 ppm T CC J C ycl e t o Cycl e Ji tt er 1 25 ps TP PJ Pea k t o Pea k Ji t te r (5 – 50 MHz) 5 0 ps Dc C l o ck Du ty Cycl e 4 5 5 5 % T r i se RE FCLK Ri se Ti m e 1 75 3 50 ps 1 , 2 , 6 Tf al l RE FCLK F al l Ti me 1 75 3 50 ps 1 , 2 , 6 T vri s e RE FCLK Ri se Ti m e V ar i at i o n 1 25 ps T v f a ll R E F C L K F a ll T im e Va r ia t ion 1 2 5 p s R i se - F al l Ma tc h i ng 20 % Vca Absol u te Cross Po i n t 0.2 5 0.55 V 1 , 3 , 7 , 13 V c r Rel a ti ve Cross Po i n t C al c C al c 5 , 12 T vc T ota l V a ri a ti on o f Vc over al l e dges 0.14 V 13 Ri s i ng E dge Ri ngb ack 0.5 6 V Absol u te Mi n . Fa llin g Edge Ri n gba ck 0.25 V Absol u te Ma x. V h i H ig h L e v e l Volt a g e 0 . 6 6 0 .7 1 0 . 8 5 V 7 , 8 Vl i Low Le vel V o l t ag e -0 .15 0 0.15 V 7 , 9 V r b R in g b a c k Volt a g e 0 . 1 0 V 7 V o vs M ax i m um Over shoo t Vhi +0 . 3 V 7 , 10 V ud s M i ni mu m Unde rsh o ot -0 .30 V 7 , 11 No t e s : 1 . M e a s u r e d a t c r os s in g p oin t wh e r e t h e in s t a n t a n e o u s v o lt a g e v a lu e of t h e r is in g e d g e o f R E FC L K e q u a ls t h e f a llin g e d g e of R E FC L K # . 2. Me asu re d fr o m V OL = 0 .17 5 V to V OH = 0.5 25 V . V a l i d onl y f o r ri s i ng R EFCLK an d fa l l i ng REFCL K#. Si gn al mus t be monotoni c th rough t he V OL to V OH r egi on for T RISE a nd T FALL . 3. Thi s mea sur eme nt re fer s t o th e t o t al v a ri a ti on from the l owest cross i n g poi n t t o th e h i ghe st, r ega rdl e ss of wh i ch e dge i s crossi n g. 4. The avera ge peri od over an y 1 µs pe ri od of t i me mus t be gr eat er th an t he mi ni m um speci f i ed p eri od. 5. V CROSS (r el ) M i n an d M ax are de ri ved usi n g t he fol l o wi ng : V CROSS (r el ) M i n = 0.5 (V h avg - 0. 71 0) + 0 . 2 50 V CROSS (r el ) M a x = 0 . 5 (V hav g - 0.71 0) + 0.55 0 6. M e asu re men t t ake n f rom si n gl e- end ed wavef o r m. 7. Me asu re men t t ake n f rom di f fer en ti al w ave form . 8. V HIGH i s de fi ne d a s th e s ta ti st i cal avera ge Hi gh val u e a s obta i ne d by usi n g t he O s c illos c op e V HI G H M at h f unc ti on. 9. V LO W i s d efi n ed a s t he sta ti s ti ca l avera ge Low v a l ue as o b tai n ed by u si ng th e Osc illo s c o p e V LO W M at h fu nct i on. 10 . Overs hoo t i s defi n ed a s t he ab so l u te val ue of t he ma xi mu m vol ta ge. 11 . Un ders hoo t i s defi n ed a s t he ab so l u te val ue of t he mi ni m um vo l t ag e. 12 . The crossi n g poi nt mu st mee t the a bsol ute a nd r el a ti ve crossi n g poi nt spe ci fi ca ti ons si mu l ta neou sl y . 13 . ∆V CROSS is d e f in e d a s t h e t o t a l v a r ia t ion o f a ll c r os s in g v o lt a g e s o f R is in g R E F C L K a n d F a llin g R E F C L K #. T h is is t h e ma xi mu m a l l o wed vari a nc e i n V CROSS f o r an y pa rt i cul a r s yste m.

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Table 2 3. DDR2 O u tpu t Clock T imin gs Symbol Pa ra m e ter DDR2-4 00 DDR2-5 33 Un i t s No t e sMi n . M ax Mi n . M ax T C2 D DR 2 SD RAM cl ock Cyc l e Ti me Averag e 5.00 3.75 ns T CH2 D DR 2 SD RAM cl ock Hi gh Ti me 2.25 1.69 ns T CL2 D DR 2 SD RAM cl ock LowTi me 2.25 1.69 ns T CS2 D DR 2 SD RAM cl ock Per i o d Ji t ter 1 00 -1 00 10 0 -1 00 p s T skew2 D DR 2 SD RAM cl ock ske w for a ny d if f e r e n t ia l c lo c k p a ir t o a n y ot h e r cl o c k p ai r 2 50 2 50 ps T skew3 D DR 2 SD RAM cl ock ske w for a ny cl o c k p ai r to a n y s y s te m m e mo ry st ro b e 2 50 2 50 ps Note s: 1. N o t te s te d

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 71 Elect rica l S p ecifica tions—Intel ® 81 348 4. 3. 2 DDR2 S DRAM I n t er fa ce Si gnal T im in gs T able 2 4 . DDR2 SDR AM S ignal T i m ing s S ymbol P ara mete r Min. Ma x Units N ot es T vb1 DQ, CB a nd D M wri te out put val i d t i me bef o r e D QS 0.53 0 ns 1 , 3 T v a 1 DQ, CB a nd D M wri te out put val i d t i me af ter D Q S 0.53 0 ns 1 , 3 T vb2 DQS wr i te o u tpu t v a l i d ti m e b efore M_ CK (DQS e ar l y) 0.20 0 ns 1 , 3 T v a 2 DQS wr i te o u tpu t v a l i d ti m e a ft er M_ CK (DQS l a te ) 0.53 0 ns 1 , 3 Tv b 3 MA, BA, RA S# , CAS # , WE# w r i te out put val i d b efore M_ CK ri si n g e dge. 4.90 0 ns 1 , 3 Tv a 3 MA, BA, RA S# , CAS # , WE# w r i te out put val i d a ft er M_ CK ri si n g e dge. 1.53 0 ns 1 , 3 Tv b 4 CS#, CKE , ODT wr i te o u tpu t v a l i d be fo r e M _ CK r i si ng edge . Un buff ere d mode 2.09 0 ns 1 , 3 Tv a 4 CS#, CKE , ODT wr i te o u tpu t v a l i d a fte r M _C K r i si ng e dge. Un buff ere d mode 0.59 0 ns 1 , 3 Tv b 5 CS#, CKE , ODT wr i te o u tpu t v a l i d be fo r e M _ CK r i si ng edge . R e gi ste re d mode 1.15 0 ns 1 , 3 Tv a 5 CS#, CKE , ODT wr i te o u tpu t v a l i d a fte r M _C K r i si ng e dge. R e gi ste re d mode 1.53 0 ns 1 , 3 Ti s6 D Q , C B r e a d in p u t s e t u p t im e b e f o r e D Q S r is in g o r f a llin g edge s. -0 .67 0 ns 2 Ti h6 DQ, CB r ead i npu t hol d ti m e a ft er DQS r i si ng o r fa l l i ng e dges . 1.25 0 ns 2 To v 7 M_CK [ 2:0] o u tpu t va l i d fr o m P_CL KIN or RE FCLK 0.46 0 1.93 0 ns No t e s : 1. See Fi gu re 14 , “ D DR2 SDR AM W r i te Ti mi ng s” on pag e 8 1 . 2. See Fi gu re 16 , “ D DR2 SDR AM Rea d Ti mi n gs” o n pa ge 8 2 . T im in g s va lid w h e n t h e D Q S d e la y is program med for t he def au l t 9 0 degr ee pha se shi ft . 3. See Fi gu re 18 , “ AC T es t Loa d for DD R2 S D RAM Si gna l s” o n pa ge 8 2 .

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4 .3 .3 P er iphe ra l B us I n t er fa ce Sign al T im ings Table 2 5. Per i p her al B us In terface Sign al Tim i n gs S ymbol P ara mete r M in . N om. M ax . U nits A 2 D Addr ess to Da ta wai t-st at es 4 - 2 0 c l ks D2 D D at a to D a ta w ai t - s t at es 4 - 20 cl k s R E C R ec o v er y w ai t - s t at es 1 - 20 cl k s N Numb er o f Da ta ph ase s 1 - 4 ph as es T a sc Addr ess set up t o CE# 25 3 0 - n s T a so Addr ess set up t o OE# 10 1 5 - n s T a sw Addr ess set up t o WE# 25 3 0 - n s T a h Addr ess hol d fr o m CE # ,OE# Nom - 5 R EC × 15 - n s T a hw Addr ess hol d fr o m WE# Nom - 5 (RE C+1) × 1 5 - n s T wce CE # pul se wi dth Nom - 5 (A2 D + 2 + ( (N - T woe OE# pu l se w i d th Nom - 5 (A2 D + 3 + ( (N - T wwe WE# pu l se w i dt h Nom - 5 (A2D + 1 ) × 1 5 - n s Td sw W ri t e D at a set up t o WE# Nom - 5 (A2D + 1 ) × 1 5 - n s Tdhw W ri t e D at a hol d fr o m WE# 10 1 5 2 0 n s T a d1 1s t Rea d D at a a cce ss t i me from Ad dres s - (A2D + 4 ) × 1 5 Nom - 11 ns T adN Nth R e ad Da ta ac cess ti me fr o m Addr ess - ( D2 D + 2 ) × 15 Nom - 11 ns T cd R e ad Da ta ac cess ti me fr o m CE # - (A2D + 2 ) × 1 5 Nom - 11 ns T oe R e ad Da ta ac cess ti me fr o m OE# 0 (A2D + 3 ) × 1 5 Nom - 11 ns Tdh R e ad Da ta hol d t i me from Addre ss, CE # , OE # 0 (RE C + 2 ) × 1 5 N om - 5 n s Note s: 1. S ee Fi gu re 25 , “ PBI Out put Ti mi n gs” o n pa ge 8 5 an d Fi gur e 2 6, “ PBI Ext er na l De vi ce T i m i ngs (Fl ash )” o n pa ge 8 6 .

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 73 Elect rica l S p ecifica tions—Intel ® 81 348 4. 3. 4 I 2 C /S MB us I n t er fa ce Si gnal T im ings T able 2 6 . I 2 C/SM Bu s Sign al Tim ings S ymb ol Par amet er Std. M ode Fas t M ode Un it s No t e sMi n . M ax Mi n . M ax FSCL SCL Cl ock Fre que ncy 0 1 00 0 4 00 KHz T BUF Bus Free Ti me Bet w e en ST OP an d ST ART C o n d it io n 4.7 1.3 µs( 1 ) T HDST A Hol d Ti me (re pea te d) ST ART Condi t i on 4 0.6 µs( 1 , 3 ) T LO W SCL Cl ock Low Ti me 4.7 1.3 µs( 1 , 2 ) THIGH SCL Cl ock Hi gh Ti me 4 0.6 µs( 1 , 2 ) TSUST A Set up Ti me f o r a R e pea te d ST AR T Condi t i o n 4.7 0.6 µs( 1 ) THDDA T Da ta Hol d Ti me 0 3.45 0 0 . 9 µs( 1 ) TSUDA T Da ta Set up Ti me 25 0 10 0 ns (1) T SR SCL an d SDA Ri se Ti me 10 00 20 + 0. 1C b 30 0 n s ( 1 , 4) T SF SCL an d SDA F a ll T im e 3 0 0 20 + 0. 1C b 30 0 n s ( 1 , 4) T SUSTO Set up Ti me f o r ST OP Cond i t i on 4 0.6 µs( 1 ) No t e s : 1. See Fi gu re 13 , “ I 2 C I nt er fac e Si gn al Ti m i ngs ” on p age 80 . 2. N ot te ste d. 3. Afte r t hi s per i o d, t he fi rs t cl ock pul se i s g ene rat ed. 4. C b = th e t o t al capa ci t anc e of on e bu s l i n e, i n p F . 5. Std M ode I 2 C si gn al t i mi n gs a ppl y f o r SM Bus t i mi n g .

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1. 3. 5 PCI B us In ter fa c e Si g na l T im in g s Table 2 7. PCI S ign al T imin gs S ymbol P ara mete r PC I - X 1 3 3 PC I - X 1 0 0 P CI-X 66 P CI 66 PCI 33 Un i t s No t e s Mi n . Max M i n . Ma x Mi n . Ma x Mi n . M ax T OV1 Cl ock t o Out put V a l i d D el ay 0.7 3.7 0 . 7 3.7 1 6 2 1 1 n s 1, 3 T OF Cl ock t o Out put Fl o a t D el a y 7 7 14 2 8 n s 1, 4 T IS1 I np ut Setu p t o cl o c k 1.2 1 . 7 3 7 n s 2 T IH1 I np ut Ho l d ti me fr o m cl ock 0.5 0 . 5 0 0 n s 2 T RST R e s e t A c t i v e T i m e 111 1 m s T RF R e set Acti ve to out pu t fl oa t del ay 40 4 0 4 0 40 ns T IS3 REQ6 4# t o R e set set up ti m e 10 10 1 0 1 0 cl ocks T IH2 R e set to RE Q64 # hol d t i me 0 5 0 0 50 0 50 0 5 0 n s T IS4 P C I -X in it ia liz a t io n p a t t e r n t o R e set set up ti me 10 10 cl ocks T IH3 Re s e t t o P C I-X in it ia liz a t ion pat te rn hol d t i me 05 005 0 n s Note s: 1 . Se e t he ti mi n g m eas ure me nt condi t i o n s i n; Fi gur e 1 1, “ O u tp ut Ti mi ng Me asu re men t W avef o r ms” o n pa ge 79 . 2 . Se e t he ti mi n g m eas ure me nt condi t i o n s i n: Fi gur e 1 2, “ I npu t T i m i ng Mea su rem en t W avefor ms” o n pa ge 8 0 . 3. S ee Fi gur e 1 9 , “ PC I /P CI - X TOV(m ax) Ri si n g E dge AC T est Load ” on page 83 , Fig u r e 2 0 , “ P C I/ P C I-X T O V ( m a x ) Fa llin g E dge A C T est Loa d” on page 8 3 , Fi gur e 2 1, “ PCI/PC I - X T OV(m i n ) AC T est Load ” on p age 83 . 4 . F or pur poses of Acti ve/ F l oa t t i mi n g me asu re men ts, t he Hi -Z or “off ” sta te i s de fi ne d t o be wh en th e t o t al cur ren t de l i vere d t hr o u gh the compone nt pi n i s l e ss t ha n or equa l t o th e l ea ka ge c urr en t s peci f i c at i o n .

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 75 Elect rica l S p ecifica tions—Intel ® 81 348 4. 3. 6 PCI Ex pre s s Dif fe re nt i al T ran s mit t er (T x) Out pu t S peci fi cat i on s T able 2 8 . PC I Exp ress* Rx In pu t Sp eci ficatio ns S ymbol P ara mete r Min. Nom M ax U nits Note s V DI F F p - p Di ff ere nt i al i n put vol ta ge 0.17 5 1 . 2 00 V 1 J TO T AL T ot al out put ji t ter 0 .65 U I 2 V CM-AC AC comm o n mode 10 0 mV 3 T R eye R e cei ver eye open i ng 0 . 3 5 U I 4 RL -Di f f RX Di ff ere nt i al r et urn l oss 12 dB 5 RL -CM TX Common mode r et ur n l oss 6 dB 5 Z RX -O UT - DC DC di ffe ren ti a l out put i mpe dan ce 90 1 00 11 0 Oh m 6 Z RX -M atch- D C D+/D - i mpe dan ce ma tch i ng - 5 +5 % 7 V RX -SQUELCH Squel c h de te ct thr esh o l d 75 17 5 mV 8 Ci n RX AC coup l ed 75 nf 9 L SKEW - RX L a ne to l a ne s k ew a t R x 20 UI 1 0 No t e s : 1. P e ak -Pe ak di ffe ren ti a l vol ta ge. V DIFFp -p = 2 × V RM Ax . Me as u re d at t h e p ac k ag e p i ns o f th e r ec e i v er . See Fi gu re 12 . 2. Ma x Ji t te r t ol e rat ed b y Rx . Th i s i s the n o m i n al v a l ue tol era te d at t he pack age pi n o f th e r ece i ver devi c e. A re cei ve r m ust th er efore tol era te any ad di ti ona l ji tt er ge nera te d by the pa cka ge t o th e di e . 3. P e ak common mode va l ue. |V D+ + V D- |/ 2 - V CM -DC( av g ) 4. See Fi gu re 24 , “ Rece i ve r Eye Op eni n g (D i ffe ren ti a l )” o n pa ge 8 4 . 5. 50 MHz t o 1 . 6 G Hz. Th e dri ve r out put i m peda nce sha l l r esu l t i n a d i ffer en ti a l r et ur n l o s s grea te r th an o r equ al to 1 5 dB an d a common mode r et ur n l oss g rea te r t ha n o r equ al to 6 dB over a f requ en cy rang e o f 5 0 MHz to 1.8 GHz. Thi s out put i m peda nce r equ i re men t app l i es to al l v a l i d o u tpu t l eve l s. Th e ref ere nce i mpe dan ce for r et urn l oss m ea sur eme nt s i s 1 00 Ω for d i ffer en ti a l re tur n l o ss an d 2 5 Ω for co m mon m o de (i .e. as m eas ur ed by a V e ctor N e twork An al yz er wi t h 1 00 Ω di f fer en ti al probes) . Note th i s i s ba sed on a nomi n al PCI Ex pre ss* i nt erc o n nec t di f fer en ti al cha ract er i sti c i mped an ce of 1 0 0 Ω. Appl i cab l e du ri n g ac ti ve (L0 ) a nd Al i gn st at es o n l y . 6. DC Di ff ere nt i al M ode Imped anc e 1 00 Ω ± 10% to l er a n ce . 7. DC i mped an ce m at chi n g be twee n t w o l a ne s of a port . 8. P e ak -t o-Peak val u e. Me asu re d at t he pi n of th e r ecei ve r . Di f fer ent i al si gna l be l o w t hi s l evel w ill i ndi ca te a sque l ch co n di ti on . 9. Al l re cei ver s sh al l be AC coupl e d to t he me di a. 10 . Lan e s k e w at t he R e cei ver t hat m ust be tol era ted.

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Table 2 9. PCI E xpr ess* Tx O ut put S pecifi catio n s Symbol Pa ra m e ter M in. N om M ax Units N ot es UI Un i t I n te rv al 4 00 p s 1 V DIFF p- p D i ffe ren ti a l out put vol t ag e 0 .80 0 1.20 0 V 2 T rise , T fal l D r iv e r R is e / F a ll T im e 0 .2 0 .4 U I 3 V TX - C M- A C AC Common Mode 20 mV 4 V T X -CM - D C del ta C o m mon M ode Act i ve t o Sl eep mode del t a -50 +50 mV RL -D i f f TX D if f e r e n t ia l R e t u r n L o s s 1 5 d B 5 RL -C M TX C o m mon M ode Ret ur n Loss 6 dB 5 Z TX - O UT -D C D C D i ffe ren ti a l Out put I m peda nce 9 0 10 0 1 10 Ω 6 Z T X -M atch-DC D +/D- i mpe dan ce m at chi n g -5 +5 % 7 L SK E W- TX La n e to La ne S k e w at T x 50 0 p s 8 J TO TA L T ota l Out put Ji t te r . 0 . 3 5 UI 9 T Deye M i ni m um T ran smi tt er eye open i n g. 0.65 UI 1 0 I TX -SH OR T Sh o r t c i rcu i t C ur ren t - 10 0 1 00 mA 1 1 V T X -IDL E Sl e ep m o de V o l t age Out put 0 0 20 mV 1 2 Note s: 1 . ±3 00 ppm . U I does not accou nt for SSC d i cta te d var i ati on s. N o t est l oad i s ne cess ar i l y a ssoci at ed w it h t h is va lu e . T h is U I s p e c if ic a t io n is a “ b e f or e t r a n s m is s ion ” s p e c if ic a t io n a n d r e p r e s e n t s t h e n o m i na l ti m e of e ach bi t tra nsm i ssi on or wi dth . 2 . Pea k -Pea k di f fer ent i al vo l t age . V DIF Fp- p = 2 × V DMAx. S p eci fi e d a t t he pac kag e pi n s i n to a 10 0 Ω te s t l oad as shown i n Fi gur e 22 , “ T ran smi t te r T es t Loa d (1 00 Ω di ff Lo a d)” on pa ge 83 . Ma x l eve l se t by m axi m um si ngl e en ded vo l t age a fte r a re fl ec ti on f rom a n o pe n. Thi s v a l ue i s f o r th e f i rst bi t af ter a t ran si ti on o n th e d at a l i n es. Sub sequ ent bi t s of t he sa me p o l a ri t y sh al l h ave an am pl i tu de of 6 dB (±0 . 5 db) l ess as me asu red di ffe re nti a l l y p eak to pe ak th an th e s peci fi e d val u e. 3. 20 –8 0% at t r an s mi tt er . S l o w er ri s e /f a l l ti m es ar e b e tt e r . 4 . Pea k c o m mon m o d e val u e. |V D+ + V D- |/2 - V CM -D C (a v g) 5 . 5 0 M H z t o 1 . 6 G H z . T h e d r iv e r ou t p u t im p e d a n c e s h a ll r e s u lt in a d if f e r e n t ia l r e t u r n lo s s g r e a t e r t h a n or equ al t o 15 dB a nd a c o m mon m o de r etu rn l oss gr ea ter t han or equa l t o 6 dB o ve r a fr equ enc y ra nge o f 5 0 MHz t o 1 . 8 G Hz. Th i s outp ut i m peda nc e re qui r eme nt a ppl i e s to al l val i d out put l evel s . The re f er e nc e i m p e da nc e fo r r et ur n l o ss m ea s ur em e nt s i s 10 0 Ω fo r d i f fe r en ti a l re tu rn l o s s an d 2 5 Ω for comm o n mode (i .e. as me asu red by a V ect o r Net w or k Ana l yze r wi t h 1 00 Ω d if f e r e n t ia l p r ob e s ) . N ot e t hi s i s ba sed o n a nomi n al P CI Expr ess * i n te rconn ect di ff ere nt i al c hara ct eri st i c i m peda nce of 1 00 Ω. Appl i c abl e dur i ng act i ve ( L0) an d Al i gn sta te s onl y . 6 . D C D i ffe ren ti a l M o de I m peda nce 10 0 Ω ±1 0% tol era nce . Al l devi c es sh al l empl oy on- chi p ada pti ve i m peda nce ma tch i ng ci r cu i t s t o e nsu re th e be st possi b l e te rm i nat i on/Z out for i t s T ra nsm i tt ers (as w e l l as re c ei v er s ). 7 . D C i m peda nce ma tch i ng bet w e en two l a nes o f a port. 8 . Be twee n a ny t wo l an es wi t hi n a s i ngl e tra nsm i tt er . 9 . C l o ck sour ce P P M m i sma tch i s i n a ddi ti on to th i s val u e. M ea sur ed over 25 0 UI . 10 . S ee Fi gur e 2 3 , “ T ran smi t ter E ye D i agra m” o n pa ge 8 4 . 1 1. Be twee n a ny vol t age from ma x su ppl y t o gnd wi th pow e r on o r off . 1 2. Squ el ch condi t i o n . Bo t h si gna l s br o u ght t o V C M -D C - |V D + - V D -|

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 77 Elect rica l S p ecifica tions—Intel ® 81 348 4. 3. 7 P CI Ex pre s s* Di ff er en t ia l R ece ive r (Rx) I npu t S peci fi cat i on s T able 3 0 . PC I Exp ress* Rx In pu t Sp eci ficatio ns S ymbol P ara mete r Min. Nom M ax U nits Notes V DI F F p - p Di ff ere nt i al i n put vol ta ge 0.17 5 1 . 2 00 V 1 J TO T AL T ot al Ou tpu t J i tt er . 0 .65 U I 2 V CM-AC AC Comm o n M o d e 10 0 mV 3 T R eye R e cei ver eye open i ng. 0 . 3 5 U I 4 RL -Di f f RX Di ff ere nt i al Ret ur n Loss 15 dB 5 RL -CM TX Common Mode R e tur n Lo s s 6 dB 5 Z RX -O UT - DC DC Di ff ere nt i al Ou tpu t Impe dan ce 90 1 00 11 0 Ω 6 Z RX -M atch- D C D+/D - i mpe dan ce ma tch i ng 0 -5 +5 % 7 V RX -SQUELCH Squel c h de te ct thr esh o l d 75 17 5 mV 8 Ci n RX AC coup l ed 4 00 pf 9 L SKEW - RX L a ne to L a ne S k ew a t R x 20 UI 1 0 No t e s : 1. P e ak -Pe ak di ffe ren ti a l vol ta ge. V DIFFp -p = 2 * V RMAx. Me asu re d a t t he pac kage pi n s of t he rec ei ver . See Fi gu re 12 . 2. Ma x Ji t te r t ol e rat ed b y Rx . Th i s i s the n o m i n al v a l ue tol era te d at t he pack age pi n o f th e r ece i ver devi c e. A re cei ve r m ust th er efore tol era te any ad di ti ona l ji tt er ge nera te d by the pa cka ge t o th e di e . 3. P e ak common mode va l ue. |V D+ + V D- |/ 2 - V CM -DC( av g ) 4. See Fi gu re 24 , “ Rece i ve r Eye Op eni n g (D i ffe ren ti a l )” o n pa ge 8 4 . 5. 50 MHz to 1.6 GHz. The dri ve r out put i mped an ce sh al l r esu l t i n a di ffe re nt i al re tu rn l o ss grea te r t ha n o r equ al to 1 5 dB an d a common mode r et ur n l oss g rea te r t ha n o r equ al to 6 dB over a f requ en cy rang e of 50 M H z to 1.8 GHz. Thi s out put i mpe dan ce r equi r em ent app l i es to a l l va l i d o u tpu t l eve l s. Th e ref ere nce i mpe dan ce for r et urn l oss m ea sur eme nt s i s 1 00 Ω for d i ffer en ti a l re tur n l o ss an d 2 5 Ω for co m mon m o d e (i .e. a s m eas ure d by a V ect or Net wo r k An al yz er w i t h 10 0 Ω di ff ere nt i al pr obes). Note th i s i s ba sed on a nomi n al PCI Ex pre ss* i nt erc o n nec t di f fer en ti al cha ract er i sti c i mped an ce of 1 0 0 Ω. Appl i cab l e du ri n g ac ti ve (L0 ) a nd Al i gn st at es o n l y . 6. DC Di ff ere nt i al M ode Imped anc e 1 00 Ω ± 10% to l er a n ce . 7. DC i mped an ce m at chi n g be twee n t w o l a ne s of a port . 8 . Pe a k t o P e a k v a lu e . M e a s u r e d a t t h e p in of t h e r e c e iv e r . D if f e r e n t ia l s ig n a l b e lo w t h is le v e l will in d ic a t e a s quel c h con di ti on. 9. Al l re cei ver s sh al l be AC coupl e d to t he me di a. 10 . Lan e s k e w at t he R e cei ver t hat m ust be tol era ted.

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4 .3 .8 B oun dar y S can T es t Sign al T im ings Table 3 1. Bo u ndar y S can T est Sign al Tim i n gs S ymbol Pa ra m e ter M in. Ma x Units Note s T JT F TCK F re q ue n cy 0 66 MH z T JT C H TCK H i gh T i me 7. 0 n s Me a su r ed at 1. 5 V (1 ) TJTCL TCK L o w T i me 7. 0 n s Me a su r ed at 1. 5 V (1 ) T JT C R TCK Ri se Ti me 5 ns 0 . 8 V t o 2 .0 V (1) T JT C F TCK F a ll T im e 5 n s 2 .0 V t o 0 . 8 V ( 1 ) T JT I S 1 I n put Set up to TCK — TDI , TM S 3. 0 n s ( 3) T JT I H 1 I n put Ho l d fr o m TCK — TDI , TM S 2. 0 n s ( 3) T JT O V 1 TDO O u t p u t Va lid D e la y 4 . 2 5 1 3 .2 5 n s R e la t iv e t o f a lli n g e d g e of TCK (2 ) T OF1 TDO F loa t D e la y 4 . 2 5 1 3 .2 5 n s R e la t iv e t o f a lli n g e d g e of TCK (4 ) Note s: 1. N o t te s te d . 2. S ee Fi gur e 1 1 , “ Out put Ti mi n g Me as ure men t W ave fo r ms ” on p age 79 . 3. S ee Fi gur e 1 2 , “ I np ut Ti mi ng Me asu re men t W avef o r ms” on pa ge 80 . 4 . A f l o a t co n di ti on o c cur s whe n t he o u tpu t cur ren t b ecomes l ess th an I LO . Fl oat de l ay i s not t est ed . See Fi gu re 11 , “Out put Ti mi n g M eas ure me nt W ave forms ” on page 79 .

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4.4 AC Timing Wavefo r ms

Figu r e 1 0 . Clo ck Tim i n g Meas ur emen t Wavefo rm s Figu r e 1 1 . O ut put T imin g Measu r e m en t W avefor m s TCH TCL TC Vt ch Vih(min) Vil(max) Vt es t Vt cl Vtes tCLK OUT PUT FL OA T Vtr is e OUT PUT DELAY RISE OUT PUT DELAY F ALL Vtfall TO V1 TOV1 TO F Vtl Vth

Inte l ® 81 348— E le ctr ical Spec i f icat ion s In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

80 O r d er N um b e r: 31 50 38 - 0 03 US

Figu re 1 2. In pu t T imin g Measu r emen t Wavefo rm s Figu re 1 3. I 2 C I nter face S ign al T imin gs CLK INPUT Valid V testVtest Vtest TIS1 TIH1 Vtl Vth Vth Vtl Vmax SD A SCL TBU F St op Start TLO W THD ST A THI GH TSR THD D A T TSF TSU D A T TSUS T A R ep e at ed THD STA TSP Sto p TSU S T O St art

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 81 Elect rica l S p ecifica tions—Intel ® 81 348 Figu r e 1 4 . DDR2 SDR AM Wr ite Tim i n gs Figu r e 1 5 . DQ S F al lin g Edg e O u tpu t Access Tim e to /fro m M_ CK Rising E dge M_CK DQ S DQ TVA 1 TVB1 TVB 4/5 TVA4/5CS # TVB3 TVA3ADDR/CMD DQS# M_CK DQS Max DQS Min TVB2 TVA2

Inte l ® 81 348— E le ctr ical Spec i f icat ion s In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

82 O r d er N um b e r: 31 50 38 - 0 03 US

Figu re 1 6. DDR2 S DRA M Read T i m ing s Table 3 2. AC Measu rem ent Co n dition s S ymb ol PCI-X PCI DD R 2 PBI Units N ot es Vth 0. 6 V CC3P3 0. 6 V CC3P3 M_VREF +0.25 0 2.0 V V tl 0. 25 V CC3 P3 0. 2 V CC3P3 M_ VR E F -0 .25 0 0.8 V V test 0. 4 V CC3P3 0. 4 V CC3P3 0. 5 V CC1P8 1.5 V V tr is e 0.28 5 V CC 3 P3 0.28 5 V CC 3 P3 0. 5 V CC1P8 1.5 V V tfal l 0.61 5 V CC 3 P3 0.61 5 V CC 3 P3 0. 5 V CC1P8 1.5 V V ma x 0. 35 V CC3 P3 0. 4 V CC3P3 1. 0 1 . 2 V S l ew R at e 1. 5 1. 5 1. 0 1 . 0 V / n S 1 Note s: 1 . Inpu t si g nal sl ew ra te i s m eas ure d be twee n V il a nd V ih Figu re 1 7. AC Test Lo ad f o r al l S i g nals E xcept PCI , P CI-E xpres s and DDR 2 an d S to r age PHY Figu re 1 8. AC Test Lo ad f o r DDR2 SDRA M Sign als DQS DQ TVB6 TVA6 Output 50 pF Test Point 25 Ω VTT Output Te st Point

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 83 Elect rica l S p ecifica tions—Intel ® 81 348 Figu r e 1 9 . PC I/PCI -X T O V(max) Risin g Ed ge A C T est Lo ad Figu r e 2 0 . PC I/PCI -X T O V(max) Fallin g Edge AC T est L o ad Figu r e 2 1 . PC I/PCI -X T OV ( m i n ) AC Test Lo ad Figu r e 2 2 . Tr an sm i tt e r Test Lo ad (1 0 0 Ω dif f Lo ad) Output Test Point 10 pF25 Ω Output 10 pF 25 Ω VCC33 Test Point Output Te st Point 10 pF 1K Ω 1K Ω VCC33 Vcm-dc 50 Ω 50 Ω

Inte l ® 81 348— E le ctr ical Spec i f icat ion s In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

84 O r d er N um b e r: 31 50 38 - 0 03 US

Figu re 2 3. Tr ans mitter Eye Diagr am Figu re 2 4. Recei v er E ye O penin g (Diffe r en ti al) Note: Transmitter Vdiffp-p = 2 * VDmax UI VDmax VDminTDeye Note: Transmitter Vdiffp-p = 2 * VRmax UI VRmax VRminTReye

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 85 Elect rica l S p ecifica tions—Intel ® 81 348 F i g ure 25. P BI Out p ut Ti m i ng s pbi_clk A CE# OE# DATA(rd) Address Address++ DD A2D w/s D2D w/s Recovery w/sREAD pbi_clk A CE# Address WE# DATA(wr) A2D w/s Recovery w/s WRITE Tasc Taso Twoe Twce Tah Twwe Tdsw Tdhw Tasw Tahw PBI Output Timings - READ PBI Output Timings - WRITE Notes: (1) pbi_clk is provided as a virtual clock and is not available as an external signal. (2) D2D Wait State Register is not available until B-step. A2D must be used for this value for A-step. (3) Timings are based on 66 MHz PBI_CLK.

Inte l ® 81 348— E le ctr ical Spec i f icat ion s In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

86 O r d er N um b e r: 31 50 38 - 0 03 US

Figu re 2 6. PB I Ext e r n al Dev i ce T i m in gs (Flash ) pbi_clk A CE# OE# DATA(rd) Address Address++ DD A2D w/s D2D w/s Recovery w/sREAD Tad1 Tcd Toe Tdh Tdh TadN PBI External Device Timings (Flash) Notes: (1) pbi_clk is provided as a virtual clock and is not available as an external signal. (2) D2D Wait State Register is not available until B-step. A2D must be used for this value for A-step. (3) Timings are based on 66 MHz PBI_CLK.

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 87 Elect rica l S p ecifica tions—Intel ® 81 348

4.5 S to r a ge Interfac e Elec t ric al Specific ations

T able 3 3 . S tor age In terface Referen ce Clock E lectrical Char acter i s tics [S _CLKP0 / S _CLKN 0] Pa ra m e ter Li m i t Un it Condition Min. T yp . M ax . S_C LKP0 /S_ CLKN0 Di ff ere nt i al Inpu t vol t age 25 0 3 50 1 00 0 mV di ff - pk S_C LKP0 /S_ CLKN0 I n pu t C o m m o n M o d e V o l t ag e V CC 1 P8S × 0.66 5 V CC 1 P 8 S × 0.7 V CC 1 P 8 S × 0. 73 5 V S_C LKP0 /S_ CLKN0 In p u t B ia s V o lt a g e V C C1P8S /2 - 10 0 m V V CC 1 P 8 S /2 V CC1P8S /2 + 10 0 m V V Th i s i s t he vol t ag e t o w h i ch both S_CL KP0 / S_ CLKN0 ar e i n te rn al l y b i ase d. S_C LKP0 /S_ CLKN0 I np ut Cl ock Fr equ ency 15 0 - 10 0 p pm 15 0 15 0 + 1 00 ppm MH z 1. 5G , 3G 12 5 - 10 0 p pm 12 5 12 5 + 1 00 ppm 1G , 1. 5G , 2G , 3G , 4G S_C LKP0 /S_ CLKN0 Du ty C ycl e 45 5 5 % S_C LKP0 /S_ CLKN0 R is e a n d F a ll T t im e 0. 35 0. 5 5 n S 20 % t o 80 % S_C LKP0 /S_ CLKN0 In p u t J it t e r 2 pS rm s 1 0 K Hz–2 0 M Hz ba ndwi dt h S_C LKP0 /S_ CLKN0 Di ff ere nt i al Inpu t Res i s ta nce 80 10 0 12 0 Ω S_C LKP0 /S_ CLKN0 Di ff ere nt i al Inpu t Ca paci t an ce 1.5 p F No t e s : 1. S_C LKP0 /S_ CLKN0 ar e AC coupl e d wi th a 10 0 nF ca pac i tor . 2. S_C LKP0 /S_ CLKN0 ar e d ri ven fr o m 1 00 ± 5% Ω di f fer en ti a l sourc e

Inte l ® 81 348— E le ctr ical Spec i f icat ion s In t e l ® 81 34 8 I /O P roces so r Da ta she et D e ce m b er 20 07

88 O r d er N um b e r: 31 50 38 - 0 03 US

Table 3 4. Sto r age I n terface Tr ans mitter Ou tpu t Electr ical Ch ar acteristics [ S_ TX P[ 7:0 ] S_ TX N [7 :0] Pa ra meter Limit Unit Condit ion Min. Typ. M ax . S_ TXP [7: 0] S_ TXN [7 :0] Di ff ere nt i al Ou tpu t Vo lt a g e 40 0 50 0 60 0 mV pk -pk S A T A Ge n 1 i . Ge n 1 m 80 0 1 60 0 S A T A Ge n 1 x, Ge n 2x 40 0 70 0 S A T A Ge n 2 i , Ge n 2 m 4 00 16 00 SA S (i ncl u di ng emp ha si s) S_ TXP [7: 0] S_ TXN [7 :0] De - em p ha s i s 04 4 % S e e Fi gur e 2 7 o n pa ge 8 8 . S_ TXP [7: 0] S_ TXN [7 :0] D if f e r e n t ia l O u t p u t R is e & F a ll Ti m e 47 1 30 pS S_ TXP [7: 0] S_ TXN [7 :0] D i ffe re nti a l Out pu t Impeda nc e 85 1 00 1 15 Ω S_ TXP [7: 0] S_ TXN [7 :0] Si n gl ed End ed Imped an ce 40 Ω Note s: 1 . T r a ns mi tt er outp uts ar e AC coupl e d wi th a 10 n F c apa ci tor . Figu re 2 7. Maxim um Amp l itu de Maximum Amplitude De-emphasis: percentage of maximum voltage below maximum One bit (UI) Wh en emp ha si s i s en abl e d, t he de- emph asi z ed o u tpu t l evel i s d efi n ed as a per cen ta ge o f t he ma xi mu m v ol t age be l o w t he ma xi mu m out put l eve l .

In t e l ® 81 34 8 I /O P roces so r De c e mb e r 2 007 D at ash eet Ord er N u mbe r: 31 50 38 -00 3U S 89 Elect rica l S p ecifica tions—Intel ® 81 348 T able 3 5 . S tor age In terface Receiver I n put E lectrical Cha racter istics [S _RX P [7 :0] S_ R XN[ 7: 0 ] Pa ra m e t er Li m i t U nit Con d ition Mi n . T y p. M ax . S_RXP [7 :0 ] S_RXN [ 7:0 ] Di ff ere nt i al Inpu t V ol ta ge 3 25 600 mV pk -pk SA T A Ge n 1 i 2 40 600 S A T A G en 1m 27 5 1 60 0 SA T A Ge n 1 x, 2x 2 75 750 S A T A G en 2i 2 40 750 S A T A G en 2m 27 5 1 60 0 SAS (i n cl udi n g em pha si s) S_RXP [7 :0 ] S_RXN [ 7:0 ] Di ff ere nt i al Inpu t Impe dan ce 85 10 0 1 1 5 Ω S_RXP [7 :0 ] S_RXN [ 7:0 ] Common Mode I mpe dan ce 20 30 40 Ω No t e s : 1. R e cei ve r i n put s a re AC coup l ed wi t h a 10 n F capa ci t o r . Figu r e 2 8 . In tel® 81 3 48 I/O Pr ocess or S to r age PHY 1. 2 V /1. 8 V Po w er S e q uen cing S ystem R equir emen ts  Signal/Ball names concerned: vcc1p8s, vcc1p2as and vcc1p2ds  1.8V supply should never exceed the 1.2V supply (analog or digital) when vcc1p2 < nominal  The 3.3V supplies and VccVio supplies don’t have any sequencing requirements. 1.2 1.8 1.8V safe 1.8V safe1.8V unsafe 1.8V unsafe 1.2 1.8