313278-008 INTEL | Alldatasheet
Document overview
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- PDF pages: 118
Technical content
Datasheet sections
- 1.1 Terminology
- 1.1.1 Processor Terminology
- 1.2 References
- 2 Electrical Specifications
- 2.1 Power and Ground Lands
- 2.2 Decoupling Guidelines
- 2.2.1 VCC Decoupling
- 2.2.2 Vtt Decoupling
- 2.2.3 FSB Decoupling
- 2.3 Voltage Identification
- 2.4 Market Segment Identification (MSID)
- 2.5 Reserved, Unused, and TESTHI Signals
- 2.6 Voltage and Current Specification
- 2.6.1 Absolute Maximum and Minimum Ratings
- 2.6.2 DC Voltage and Current Specification
- 2.6.4 Die Voltage Validation
- 2.7 Signaling Specifications
- 2.7.1 FSB Signal Groups
- 2.7.2 CMOS and Open Drain Signals
- 2.7.3 Processor DC Specifications
- 2.7.3.1 GTL+ Front Side Bus Specifications
- 2.7.4 Clock Specifications
- 2.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
- 2.7.6 FSB Frequency Select Signals (BSEL[2:0])
- 2.7.7 Phase Lock Loop (PLL) and Filter
- 2.7.8 BCLK[1:0] Specifications (CK505 based Platforms)
- 2.7.9 BCLK[1:0] Specifications (CK410 based Platforms)
- 2.8 PECI DC Specifications
- 3 Package Mechanical Specifications
- 3.1 Package Mechanical Drawing
- 3.1.1 Processor Component Keep-Out Zones
- 3.1.2 Package Loading Specifications
- 3.1.3 Package Handling Guidelines
- 3.1.4 Package Insertion Specifications
- 3.1.5 Processor Mass Specification
- 3.1.6 Processor Materials
- 3.1.7 Processor Markings
- 3.1.8 Processor Land Coordinates
- 4 Land Listing and Signal Descriptions
- 4.1 Processor Land Assignments
- 4.2 Alphabetical Signals Reference
- 5 Thermal Specifications and Design Considerations
- 5.1 Processor Thermal Specifications
- 5.1.1 Thermal Specifications
- 5.1.2 Thermal Metrology
- 5.2 Processor Thermal Features
- 5.2.1 Thermal Monitor
- 5.2.2 Thermal Monitor
- 5.2.3 On-Demand Mode
Document Number: 313278-008 Intel® Core™2 Extreme Processor X6800Δ and Intel® Core™2 Duo Desktop Processor E6000Δ and E4000Δ Series Datasheet —on 65 nm Process in the 775-land LGA Package and supporting Intel® 64 Architecture and supporting Intel® Virtualization Technology± March 2008
2 Datasheet
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/ processor_number for details. Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or consult with your system vendor for more information. No computer system can provide absolute security under all conditions. Intel® Trusted Execution Technology (Intel® TXT) is a security technology under development by Intel and requires for operation a computer system with Intel® Virtualization Technology, a Intel Trusted Execution Technology-enabled Intel processor, chipset, BIOS, Authenticated Code Modules, and an Intel or other Intel Trusted Execution Technology compatible measured virtual machine monitor. In addition, Intel Trusted Execution Technology requires the system to contain a TPMv1.2 as defined by the Trusted Computing Group and specific software for some uses. ±Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain platform software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. The Intel® Core™2 Duo desktop processor E6000 and E4000 series and Intel ® Core™2 Extreme processor X6800 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Intel Core, Core Inside, Intel Inside, Intel Leap ahead, Intel SpeedStep, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2006–2008 Intel Corporation.
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5.4.1.1 Key Difference with Legacy Diode-Based Thermal
6.2.4 Extended HALT State, HALT Snoop State, Extended Stop Grant Snoop
6.2.4.2 Extended HALT Snoop Stat e, Extended Stop Grant Snoop
6.3 Enhanced Intel
7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip
7.3.2 Fan Speed Control Operation (Intel ® Core2 Extreme Processor
7.3.3 Fan Speed Control Operation (Intel ® Core2 Duo Desktop Processor
8.1.1 Balanced Technology Extended (BTX ) Type I and Type II Boxed Processor
11 Processor Top-Side Markings Example for the Intel
® Core™2 Duo Desktop
12 Processor Top-Side Markings Example for the Intel ® Core™2 Duo Desktop
13 Processor Top-Side Markings Example for the Intel ® Core™2 Duo Desktop
14 Processor Top-Side Markings Example for the Intel ® Core™2 Duo Desktop
41 Requirements for the Balanced Technology Extended (BTX) Type I Keep-out
42 Requirements for the Balanced Technology Extended (BTX) Type II Keep-out
45 Balanced Technology Extended (BTX) Mainboard Power Header Placement
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40 TMA Set Points for 3-wire operatio n of BTX Type I and Type II Boxed
Revision History
-001 • Initial release July 2006 -002 • Corrected L1 Cache information September 2006 -003
- A d d e d I n t e l® Core™2 Duo Desktop Processor E4300 information
- Updated Table 5, DC Voltage and Current Specification
- Added Section 2.3, PE CI DC Specifications
- Updated Section 5.3, Platform Environment Control Interface (PECI)
- Updated Section 7.1.2, Boxed Processor Fan Heatsink Weight
- Updated Table 37, Fan Heatsink Power and Signal Specifications
- Added Section 7.3.2, Fan Speed Control Operation Intel ® Core2 Extreme Processor X6800 Only) and Section 7.3.3, Fan Speed Control Operation (Intel® Core2 Duo Desktop Processor E6000 and E4000 series Only) January 2007 -004 • Added Intel ® Core™2 Duo Desktop Processor E6420, E6320, and E4400 information April 2007 -005
- A d d e d I n t e l® Core™2 Duo Desktop Processor E6850, E6750, E6550, E6540, and E4500 information.
- Added specifications for 1333 MHz FSB.
- Added support for Extended Stop Grant State, Extended Stop Grant Snoop States.
- Added new thermal profile table and figure. July 2007 -006 • Added Intel ® Core™2 Duo Desktop Processor E4400 with CPUID = 065Dh. August 2007 -007 • Added Intel ® Core™2 Duo Desktop Processor E4600 October 2007 -008 • Added Intel ® Core™2 Duo Desktop Processor E4700 March 2008
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Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Series Features The Intel Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000, E4000 series deliver Intel's advanced, powerful processors for desktop PCs. The processor is designed to deliver performance across applications and usages where end-users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multitasking user environments. Intel® 64 architecture enables the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. The processor supporting Enhanced Intel SpeedStep® technology allows tradeoffs to be made between performance and power consumption. The Intel Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000, E4000 series also include the Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as executable or non-executable. The Intel Core™2 Extreme processor X6800 and Intel ® Core™2 Duo desktop processor E6000 series support Intel® Virtualization Technology. Virtualization Technology provides silicon-based functionality that works together with compatible Virtual Machine Monitor (VMM) software to improve on software- only solutions. The Intel Core™2 Duo desktop processors E6850, E6750, and E6550 support Intel® Trusted Execution Technology (Intel® TXT). Intel® Trusted Execution Technology (Intel® TXT) is a security technology. § §
- Available at 2.93 GHz (Intel Core™2 Extreme processor X6800 only)
- Available at 3.00 GHz, 2.66 GHz, 2.40 GHz, 2.33 GHz, 2.13 GHz, and 1.86 GHz (Intel Core™2 Duo desktop processor E6850, E6750, E6700, E6600, E6540, E6540, E6420, E6400, E6320, and E6300 only)
- Available at 2.40 GHz, 2.20 GHz, 2.00 GHz, and
1.80 GHz and (Intel Core™2 Duo desktop processor
E4700, E4600, E4500, E4400, and E4300 only)
- Enhanced Intel SpeedStep ® Technology
- Supports Intel ® 64 architecture
- Supports Intel ® Virtualization Technology (Intel Core™2 Extreme processor X6800 and Intel Core™2 Duo desktop processor E6000 series only)
- Supports Execute Disable Bit capability
- Supports Intel ® Trusted Execution Technology (Intel® TXT) (Intel Core2 Duo desktop processors E6850, E6750, and E6550 only)
- FSB frequency at 1333 MHz (Intel Core2 Duo desktop processors E6850, E6750, E6550, and E6540 only)
- FSB frequency at 1066 MH z (Intel Core™2 Extreme processor X6800 and Intel Core™2 Duo desktop processor E6700, E6600, E6420, E6400, E6320, and E6300 only)
- FSB frequency at 800 MH z (Intel Core™2 Duo desktop processor E4000 series only)
- Binary compatible with applications running on previous members of the Intel microprocessor line
- Advance Dynamic Execution
- Very deep out-of-order execution
- Enhanced branch prediction
- Optimized for 32-bit a pplications running on advanced 32-bit operating systems
- Two 32-KB Level 1 data caches
- 4 M B I n t e l ® Advanced Smart Cache (Intel Core™2 Extreme processor X6800 and Intel Core™2 Duo desktop processor E6850, E6750, E6700, E6540, E6540, E6600, E6420, and E6320, only)
- 2 M B I n t e l® Advanced Smart Cache (Intel Core™2 Duo desktop processor E6400, E6300, E4700, E4600, E4500, E4400, and E4300 only)
- I n t e l ® Advanced Digital Media Boost
- Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance
- Power Management capabilities
- System Management mode
- Multiple low-power states
- 8-way cache associativity provides improved cache hit rate on load/store operations
- 775-land Package
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1 Introduction
The Intel® Core™2 Extreme processor X6800 and Intel ® Core™2 Duo desktop processor E6000 and E4000 series combine the performance of the previous generation of desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems. These processors are 64-bit processors that maintain compatibility with IA-32 software. The Intel ® Core™2 Extreme processor X6800 and Intel ® Core™2 Duo desktop processor E6000 and E4000 series use Flip-Chip Land Grid Array (FC-LGA6) package technology, and plugs into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the LGA775 socket. Note: In this document, unless otherwise specified, the Intel ® Core™2 Duo desktop processor E6000 series refers to Intel® Core™2 Duo desktop processors E6850, E6750, E6550, E6540, E6700, E6600, E6420, E6400, E6320, and E6300. The Intel® Core™2 Duo desktop processor E4000 series refers to Intel® Core™2 Duo desktop processor E4700, E4600, E4500, E4400, and E4300. Note: In this document, unless otherwise specified, the Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000 and E4000 series are referred to as “processor.” The processors support several Advanced Technologies including the Execute Disable Bit, Intel® 64 architecture, and Enhanced Intel SpeedStep® Technology. The Intel Core™2 Duo desktop processor E6000 series and Intel Core™2 Extreme processor X6800 support Intel® Virtualization Technology (Intel VT). In addition, the Intel Core™2 Duo desktop processors E685 0, E6750, and E6550 support Intel® Trusted Execution Technology (Intel® TXT). The processor's front side bus (FSB) uses a split-transaction, deferred reply protocol like the Intel® Pentium® 4 processor. The FSB uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "double- clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 10.7 GB/s. Intel has enabled support components for the processor including heatsink, heatsink retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling. The processor includes an address bus power-down capability which removes power from the address and data signals when the FSB is not in use. This feature is always enabled on the processor.
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1.1 Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level). The phrase “Front Side Bus” refers to the interface between the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O.
1.1.1 Processor Terminology
Commonly used terms are explained here for clarification:
- Intel® Core™2 Extreme processor X6800 — Dual core processor in the FC- LGA6 package with a 4 MB L2 cache.
- Intel® Core™2 Duo desktop processor E6850, E6750, E6550, E6540, E6700, E6600, E6420, and E6320, — Dual core processor in the FC-LGA6 package with a 4 MB L2 cache.
- Intel® Core™2 Duo desktop processor E6400, E6300, E4700, E4600, E4500, E4400, and E4300— Dual core processor in the FC-LGA6 package with a 2M B L 2 c a c h e .
- Processor — For this document, the term processor is the generic form of the Intel® Core™2 Duo desktop processor E6000 and E4000 series and the Intel ® Core™2 Extreme processor X6800. The processor is a single package that contains one or more execution units.
- Keep-out zone — The area on or near the processor that system design can not use.
- Processor core — Processor core die with integrated L2 cache.
- LGA775 socket — The processors mate with the system board through a surface mount, 775-land, LGA socket.
- Integrated heat spreader (IHS) —A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.
- Retention mechanism (RM) — Since the LGA775 socket does not include any mechanical features for heatsink attach, a retention mechanism is required. Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket.
- FSB (Front Side Bus) — The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB.
- Storage conditions — Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks. Upon exposure to “free air”(i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.
- Functional operation — Refers to normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical and thermal are satisfied.
- Execute Disable Bit — Allows memory to be marked as executable or non- executable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system. See the Intel® Architecture Software Developer's Manual for more detailed information.
- Intel® 64 Architecture — An enhancement to Intel's IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of Intel 64 architecture. Further details on Intel 64 architecture and programming model can be found in the Intel® Extended Memory 64 Technology Software Developer Guide at http://www.intel.com/technology/intel64/index.htm.
- Enhanced Intel SpeedStep® Technology — Enhanced Intel Speedstep ® technology allows trade-offs to be made between performance and power consumptions, based on processor utilization. This may lower average power consumption (in conjunction with OS support).
- Intel ® Virtualization Technology (Intel VT) — Intel Virtualization Technology provides silicon-based functionality that works together with compatible Virtual Machine Monitor (VMM) software to improve upon software-only solutions. Because this virtualization hardware provides a new architecture upon which the operating system can run directly, it removes the need for binary translation. Thus, it helps eliminate associated performance overhead and vastly simplifies the design of the VMM, in turn allowing VMMs to be written to common standards and to be more robust. See the Intel® Virtualization Technology Specification for the IA-32 Intel® Architecture for more details.
- Intel® Trusted Execution Technology (Intel® TXT)— Intel® Trusted Execution Technology (Intel® TXT) is a security technology under development by Intel and requires for operation a computer system with Intel® Virtualization Technology, a Intel Trusted Execution Technology-enabled Intel processor, chipset, BIOS, Authenticated Code Modules, and an Intel or other Intel Trusted Execution Technology compatible measured virtual machine monitor. In addition, Intel Trusted Execution Technology requires the system to contain a TPMv1.2 as defined by the Trusted Computing Group and specific software for some uses.
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1.2 References
Table 1. Reference Documents
2 Electrical Specifications
This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided.
2.1 Power and Ground Lands
The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to V CC, while all VSS lands must be connected to a system ground plane. The processor VCC lands must be supplied the voltage determined by the Voltage IDentification (VID) lands. The signals denoted as VTT provide termination for the front side bus and power to the I/O buffers. A separate supply must be implemented for these lands, that meets the VTT specifications outlined in Table 5.
2.2 Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings. This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic or aluminum-polymer capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 5. Failure to do so can result in timing violations or reduced lifetime of the component.
2.2.1 V CC Decoupling
VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications. This includes bulk capacitance with low effective series resistance (ESR) to keep the voltage rail within specifications during large swings in load current. In addition, ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity. Consult the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket.
2.2.2 V TT Decoupling
Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. To insure compliance with the specifications, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors.
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2.2.3 FSB Decoupling
frequency capacitance required for the FSB is included on the processor package. also be provided by the motherboard for proper [A]GTL+ bus operation.
2.3 Voltage Identification
for each processor frequency is provided in Table 5. Technology, or Extended HALT State). result in as many VID transitions as necessary to reach the target core voltage. Table 6 and Figure 1 as measured across the VCC_SENSE and VSS_SENSE lands. Table 6. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for further details.
Table 2. Voltage Identification Definition
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2.4 Market Segment Identification (MSID)
2.5 Reserved, Unused, and TESTHI Signals
processor and the location of all RESERVED lands. should be left as no connects as GTL+ termination is provided on the processor silicon. However, see Table 8 for details on GTL+ signals that do not include on-die termination. Unused active high inputs, should be connected through a resistor to ground (VSS). same value as the on-die termination resistors (RTT). For details, see Table 14. that matches the nominal trace impedance. Table 3. Market Segment Select ion Truth Table for MSID[1:0]1, 2, 3, 4
- The MSID[1:0] signals are provided to indicate the Market Segment for the processor
motherboard may use these signals to identify the processor installed.
- These signals are not connected to the processor die.
- A logic 0 is achieved by pulling the signal to ground on the package.
- A logic 1 is achieved by leaving the signal as a no connect on the package.
00 Intel® Core™2 Duo desktop processor E6000 and E4000 series and the
01 R e s e r v e d
10 R e s e r v e d
11 R e s e r v e d
The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group:
- TESTHI[1:0]
- TESTHI[7:2]
- TESTHI8/FC42 – cannot be grouped with other TESTHI signals
- TESTHI9/FC43 – cannot be grouped with other TESTHI signals
- TESTHI10 – cannot be grouped with other TESTHI signals
- TESTHI11 – cannot be grouped with other TESTHI signals
- TESTHI12/FC44 – cannot be grouped with other TESTHI signals
- TESTHI13 – cannot be grouped with other TESTHI signals However, utilization of boundary scan test will not be functional if these lands are connected together. For optimum noise margin, all pull-up resistor values used for TESTHI[13:0] lands should have a resistance value within ± 20% of the impedance of the board transmission line traces. For example, if the nominal trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω should be used.
2.6 Voltage and Current Specification
2.6.1 Absolute Maximum and Minimum Ratings
Table 4 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded. Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields.
20 Datasheet
2.6.2 DC Voltage and Current Specification
Table 4. Absolute Maximum and Minimum Ratings
- For functional operation, all processor electrical, signal quality, mechanical and thermal
specifications must be satisfied.
- Excessive overshoot or undershoot on any signal will likely result in permanent damage to the
- Storage temperature is applicable to storage conditions only. In this scenario, the processor must
processor case temperature specifications.
- This rating applies to the processor an d does not include any tray or packaging.
- Failure to adhere to this specification can affect the long term reliability of the processor.
Table 5. Voltage and Current Specifications
3.00 GHz
2.66 GHz
2.40 GHz
2.33 GHz
2.13 GHz
1.86 GHz
2.93 GHz
2.60 GHz
2.20 GHz
2.00 GHz
1.80 GHz
4.6 A 10
- Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data.
These specifications will be updated with characterized data from silicon measurements at a later date.
- Adherence to the voltage specifications for the processo r are required to ensure reliable processor operation.
- Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
SpeedStep® Technology, or Extended HALT State).
- These voltages are targets only. A variable voltage source should exist on systems in the event that a different
voltage is required. See Section 2.3 and Table 2 for more information.
- The voltage specification requiremen ts are measured across VCC_SENSE and VSS_SENSE lands at the socket
is not coupled into the oscilloscope probe.
- Refer to Table 6 and Figure 1 for the minimum, typical, and maximum VCC allowed for a given current. The
- ICC_MAX specification is based on the VCC_MAX loadline. Refer to Figure 1 for details.
- VTT must be provided via a separate voltage source and not be connected to VCC. This specification is measured
- Baseboard bandwidth is limited to 20 MHz.
system. This parameter is based on design characterization and is not tested.
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Table 6. V CC Static and Transient Tolerance
- The loadline specification includes both static and transient limits except for overshoot allowed
- This table is intended to aid in reading discrete points on Figure 1.
- The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE
- Adherence to this loadline specification is re quired to ensure reliable processor operation.
- The loadline specification includes both static and transient limits except for overshoot
allowed as shown in Section 2.6.3.
- This loadline specification shows the deviation from the VID set point.
- The loadlines specify voltage limits at the die measured at the VCC_SENSE and
guidelines and VR implementation details. Figure 1. V CC Static and Transient Tolerance
24 Datasheet
2.6.3 V CC Overshoot
cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage). processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.
- V OS is measured overshoot voltage.
- T OS is measured time duration above VID.
2.6.4 Die Voltage Validation
Table 7. V
- Adherence to these specificat ions is required to ensure reliable processor operation.
Figure 2. V CC Overshoot Example Waveform
2.7 Signaling Specifications
critical than with previous processor families. bus on the motherboard for most GTL+ signals.
2.7.1 FSB Signal Groups
group as well as the GTL+ I/O group when driving. Table 8. FSB Signal Groups (Sheet 1 of 2)
26 Datasheet
- Refer to Section 4.2 for signal descriptions.
- In processor systems where no debug port is implemented on the system board, these
implemented on the system board, these signals are no connects.
- The value of these signals during the acti ve-to-inactive edge of RESET# defines the
processor configuration options. See Section 6.1 for details.
- PROCHOT# signal type is open drain output and CMOS input.
Table 8. FSB Signal Groups (Sheet 2 of 2) Table 9. Signal Characteristics
- Signals that do not have RTT, nor are actively driven to their high-voltage level.
Table 10. Signal Reference Voltages
- These signals also have hysteresis added to the reference voltage. See Table 12 for more
2.7.2 CMOS and Open Drain Signals
requirements for entering and leaving the low power states.
2.7.3 Processor DC Specifications
Table 11. GTL+ Signal Group DC Specifications
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low
- The VTT referred to in these specifications is the instantaneous VTT.
- VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high
- VIH and VOH may experience excursions above VTT.
- Leakage to VSS with land held at VTT.
- Leakage to VTT with land held at 300 mV.
Table 12. Open Drain and TAP Output Signal Group DC Specifications
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- VOH is determined by the value of the external pull-up resister to VTT.
- For Vin between 0 and VOH.
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2.7.3.1 GTL+ Front Side Bus Specifications
precision voltage divider circuits. Table 13. CMOS Signal Group DC Specifications
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low
- The VTT referred to in these specifications refers to instantaneous VTT.
- VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high
- VIH and VOH may experience excursions above VTT.
- All outputs are open drain.
- Leakage to VSS with land held at VTT.
- Leakage to VTT with land held at 300 mV.
Table 14. GTL+ Bus Voltage Definitions
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- GTLREF is to be generated from VTT by a voltage divider of 1% resistors (one divider for each
- RTT is the on-die termination resistance measured at VTT/3 of the GTL+ output driver.
- COMP resistance must be provid ed on the system board with 1% resistors. See the applicable
2.7.4 Clock Specifications
2.7.5 Front Side Bus Clock (BCL K[1:0]) and Processor Clocking
Clock Synthesizer/Driver should comply with the specifications in Section 2.7.8.
2.7.6 FSB Frequency Select Signals (BSEL[2:0])
Table 15. Core Frequency to FS B Multiplier Configuration
800 MHz FSB)
1066 MHz FSB)
1333 MHz FSB)
- Individual processors operate only at or below the rated frequency.
- Listed frequencies are not necessarily committed production frequencies.
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2.7.7 Phase Lock Lo op (PLL) and Filter
used for the PLL. Refer to Table 5 for DC specifications.
2.7.8 BCLK[1:0] Specificatio ns (CK505 based Platforms)
Table 16. BSEL[2:0] Frequency Table for BCLK[1:0] Table 17. Front Side Bus Diffe rential BCLK Specifications
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- "Steady state" voltage, not in cluding overshoot or undershoot.
- Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0
equals the falling edge of BCLK1.
- VHavg is the statistical average of the VH measured by the oscilloscope.
- The crossing point must meet the absolute and relative crossing point specifications
- Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as
the absolute value of the minimum voltage.
- Measurement taken from differential waveform.
- Cpad includes die capacitance only. No package parasitics are included.
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2.7.9 BCLK[1:0] Specificatio ns (CK410 based Platforms)
Table 18. Front Side Bus Diffe rential BCLK Specifications
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the
- The crossing point must meet the absolute and rela tive crossing point specifications simultaneously.
- VHavg is the statistical average of the VH measured by the oscilloscope.
- VHavg can be measured directly using “Vtop” on Agilent* oscilloscopes and “High” on Tektronix* oscilloscopes.
- Overshoot is defined as the absolute value of the maximum voltage.
- Undershoot is defined as the absolute value of the minimum voltage.
- Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback
and the maximum Falling Edge Ringback.
- Threshold Region is defined as a region entered around the crossing point voltage in which the differential
receiver switches. It includes input threshold hysteresis. Figure 6. Differential Clock Crosspoint Specification
2.8 PECI DC Specifications
Control Interface (PECI) Specification. Table 19. PECI DC Electrical Limits
- VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. Refer
to Table 4 for VTT specifications.
- The input buffers use a Schmitt-triggered input design for improved noise immunity.
- The leakage specification applies to powered devices on the PECI bus.
- One node is counted for each client and one no de for the system host. Extended trace lengths
might appear as additional nodes.
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3 Package Mechanical
LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket.
- Integrated Heat Spreader (IHS)
- Thermal Interface Material (TIM)
- Processor core (die)
- Package substrate
- Capacitors NOTE: 1. Socket and System Board are included fo r reference and are not part of processor package.
3.1 Package Mechanical Drawing
- Package reference with tolerances (total height, length, width, etc.)
- IHS parallelism and tilt
- Land dimensions
- Top-side and back-side component keep-out dimensions
- Reference datums
- All drawing dimensions are in mm [in].
- Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and Mechanical Design Guidelines.
Figure 7. Processor Package Assembly Sketch
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Figure 8. Processor Package Drawing Sheet 1 of 3
Figure 9. Processor Package Drawing Sheet 2 of 3
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Figure 10. Processor Package Drawing Sheet 3 of 3
3.1.1 Processor Compon ent Keep-Out Zones
manufacturing efficiencies but will remain within the component keep-in.
3.1.2 Package Loading Specifications
Table 20 provides dynamic and static load specifications for the processor package. maintained by any thermal and mechanical solutions.
3.1.3 Package Handling Guidelines
handling loads may be experienced during heatsink removal. Table 20. Processor Lo ading Specifications
- These specifications apply to uniform compressive loading in a direction normal to the
- This is the maximum force that can be applied by a heatsink retention clip. The clip must also
provide the minimum specified load on the processor package.
- These specifications are based on limited testing for design characterization. Loading limits are
for the package only and do not include the limits of the processor socket.
- Dynamic loading is defined as an 11 ms duration average load superimposed on the static load
Table 21. Package Handling Guidelines
- A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.
- These guidelines are based on limited testing for design characterization.
- A tensile load is defined as a pulling load appl ied to the IHS in a direction normal to the IHS
- A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the
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3.1.4 Package Insertion Specifications
3.1.5 Processor Mass Specification
the components that are included in the package.
3.1.6 Processor Materials
Table 22 lists some of the package components and associated materials.
3.1.7 Processor Markings
are to aid in the identification of the processor. Table 22. Processor Materials Figure 11. Processor Top-Side Ma rkings Example for the Intel® Core™2 Duo Desktop
Figure 12. Processor Top-Side Ma rkings Example for the Intel® Core™2 Duo Desktop Figure 13. Processor Top-Side Ma rkings Example for the Intel® Core™2 Duo Desktop
6700 SLxxx [COO]
6400 SLxxx [COO]
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Figure 14. Processor Top-Side Ma rkings Example for the Intel® Core™2 Duo Desktop Figure 15. Processor Top-Side Markings for the Intel ® Core™2 Extreme Processor X6800
6800 SLxxx [COO]
3.1.8 Processor Land Coordinates
referred to throughout the document to identify processor lands. Figure 16. Processor La nd Coordinates and Quadrants (Top View)
Package Mechanical Specifications
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Land Listing and Signal Descriptions
4 Land Listing and Signal
This chapter provides the processor land assignment and signal descriptions.
4.1 Processor Land Assignments
This section contains the land listings for the processor. The land-out footprint is shown in Figure 17 and Figure 18. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view). Table 23 provides a listing of all processor lands ordered alphabetically by land (signal) name. Table 24 provides a listing of all processor lands ordered by land number.
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Figure 17. land-out Diagram (Top View – Left Side)
Figure 18. land-out Diagram (Top View – Right Side)
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Table 23. Alphabetical Land
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Table 24. Numerical Land
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4.2 Alphabetical Signals Reference
Table 25. Signal Description (Sheet 1 of 9) configuration. See Section 6.1 for more details. Output Write bus transaction. operations associated with the new transaction. drive their outputs and latch their inputs. current bus owner cannot issue any new transactions.
appropriate pins/lands of all processor FSB agents. These signals do not have on-die termination. completed, then releases the bus by de-asserting BPRI#. signal is sampled to determine the agent ID = 0. board using precision resistors.
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asserts DRDY# to indicate a valid data transfer. data signals correspond to a pair of one DSTBP# and one DSTBN#. group is inverted and therefore sampled active high. signals for that particular sub-phase for that 16-bit group. connect in the system. DBR# is not a processor signal.
of all processor FSB agents. clock data transfer, DRDY# may be de-asserted to insert idle clocks. DSTBN[3:0]# are the data strobes used to latch in D[63:0]#. DSTBP[3:0]# are the data strobes used to latch in D[63:0]#. Identification and the CPUID Instruction application note. signal is a logical 0 or logical 1.
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be continued by reasserting HIT# and HITM# together. for termination requirements. no effect when the NE bit in control register 0 (CR0) is set. Output Write bus transaction. appropriate pins/lands of all processor FSB agents. systems where no debug port is implemented on the system board. Pentium processor. Both signals are asynchronous.
end of the last transaction. the processor FSB, it will wait until it observes LOCK# de-asserted. to Table 3 for additional information. before a subsequent rising edge of PWRGOOD. should be driven high throughout boundary scan operation. signals are source synchronous to ADSTB0#. asserted for more than 10 ms while PWRGOOD is asserted. configuration options are described in the Section 6.1. terminated on the system board.
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if the processor is present. processor begins program execution from the SMM handler. processor will tri-state its outputs. signals to all processor core units except the FSB and APIC units. STPCLK# is an asynchronous input. (also known as the Test Access Port). provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. Section 2.5 for more details. THERMDA Other Thermal Diode Anode. See Section 5.3. THERMDC Other Thermal Diode Cathode. See Section 5.3.
temperature approximately 20 °C above the maximum TC. assertion of PWRGOOD (provided VTT and VCC are valid). must connect the appropriate pins/lands of all FSB agents. must be driven low during power on Reset. these pins is determined by the VID[7:0] pins. VCCPLL Input VCCPLL provides isolated po wer for internal processor FSB PLLs. the silicon with little noise.
11.0 Processor Power Delivery Design Guidelines For Desktop
disabled until the voltage supply for the VID signals becomes valid. specification variations. See Table 2 for definitions of these signals. Desktop LGA775 Socket for more information.
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VSSA Input VSSA is the isolated ground for internal PLLs. VTT Input Miscellaneous voltage supply.
Thermal Specifications and Design Considerations
5 Thermal Specifications and
5.1 Processor Thermal Specifications
The processor requires a thermal solution to maintain temperatures within the operating limits as described in Section 5.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of system fans combined with ducting and venting. For more information on designing a component level thermal solution, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). Note: The boxed processor will ship with a component thermal solution. Refer to Chapter 7 for details on the boxed processor.
5.1.1 Thermal Specifications
To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (T specifications when operating at or below the Thermal Design Power (TDP) value listed per frequency in Table 26. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). The processor uses a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control. Selection of the appropriate fan speed is based on the relative temperature data reported by the processor’s Platform Environment Control Interface (PECI) bus as described in Section 5.4.1.1. The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT# (see Section 5.2). Systems that implement fan speed control must be designed to take these conditions in to account. Systems that do not alter the fan speed only need to ensure the case temperature meets the thermal profile specifications. To determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions. Refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) and the Processor Power Characterization Methodology for the details of this methodology. The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that
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Table 26. Processor Thermal Specifications
- Thermal Design Power (TDP) should be used for processor ther mal solution design targets. The TDP is not the maximum power
that the processor can dissipate.
- This table shows the maximum TDP for a given frequency range. Individual processors may have a lower TDP.
figure and associated table for the allowed combinations of power and TC.
- Refer to the “Component Identification Information” section of the Intel® Core™2 Extreme and Intel ® Core™2 Duo Desktop
Processor Specification Update for processor specific Idle power.
06 Guidance4
- 775_VR_CONFIG_06/775_VR_CONFIG_05B guidelin es provide a design target for meeting future thermal requirements.
- Specification is at 35 °C T C and typical voltage loadline.
- These processors have CPUID = 06FBh.
- Specification is at 50 °C T C and typical voltage loadline.
- These processors have CPUID = 06F6h.
- These processors have CPUID = 06FDh.
10.These processors have CPUID = 06F2h.
Table 27. Thermal Profile 1 Figure 19. Thermal Profile 1
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Table 28. Thermal Profile 2 Figure 20. Thermal Profile 2
Table 29. Thermal Profile 3 Figure 21. Thermal Profile 3
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series with 2 MB L2 Cache and CPUID = 06F6h. series with 2 MB L2 Cache and CPUID = 06F6h. Table 30. Thermal Profile 4 Figure 22. Thermal Profile 4
NOTE: For the Intel® Core™2 Extreme processor X6800. NOTE: For the Intel® Core™2 Extreme processor X6800. Table 31. Thermal Profile 5 Figure 23. Thermal Profile 5
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5.1.2 Thermal Metrology
Table 26. This temperature specification is meant to help ensure proper operation of refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2).
5.2 Processor Thermal Features
5.2.1 Thermal Monitor
Figure 24. Case Temperature (T
Thermal Specifications and Design Considerations and in some cases may result in a TC that exceeds the specified maximum temperature and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2) for information on designing a thermal solution. The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and cannot be modified. The Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines.
5.2.2 Thermal Monitor 2
The processor also supports an additional power reduction capability known as Thermal Monitor 2. This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor. When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust its operating frequency (via the bus multiplier) and input voltage (via the VID signals). This combination of reduced frequency and VID results in a reduction to the processor power consumption. A processor enabled for Thermal Monitor 2 includes two operating points, each consisting of a specific operating frequency and voltage. The first operating point represents the normal operating condition for the processor. Under this condition, the core-frequency-to-FSB multiple used by the processor is that contained in the appropriate MSR and the VID is that specified in Table 5. These parameters represent normal system operation. The second operating point consists of both a lower operating frequency and voltage. When the TCC is activated, the processor automatically transitions to the new frequency. This transition occurs very rapidly (on the order of 5 μs). During the frequency transition, the processor is unable to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency. Once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator. The voltage regulator must support dynamic VID steps to support Thermal Monitor 2. During the voltage change, it will be necessary to transition through multiple VID codes to reach the target operating voltage. Each step will likely be one VID table entry (see Table 5). The processor continues to execute instructions during the voltage transition. Operation at the lower voltage reduces the power consumption of the processor. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the operating frequency and voltage transition back to the normal system operating point. Transition of the VID code will occur first, to insure proper operation once the processor reaches its normal operating frequency. Refer to Figure 25 for an illustration of this ordering.
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regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled.
5.2.3 On-Demand Mode
selected by the On-Demand mode. Figure 25. Thermal Monitor 2 Frequency and Voltage Ordering
Thermal Specifications and Design Considerations
5.2.4 PROCHOT# Signal
An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or de- assertion of PROCHOT#. As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled, for both cores. The TCC will remain active until the system de-asserts PROCHOT#. PROCHOT# allows for some protection of various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor (either core) has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal protection of system components. PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power. With a properly designed and characterized thermal solution, it is anticipated that PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for details on implementing the bi-directional PROCHOT# feature.
5.2.5 THERMTRIP# Signal
Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 25). At this point, the FSB signal THERMTRIP# will go active and stay active as described in Table 25. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles.
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5.3 Thermal Diode
- Intel does not support or re commend operation of the thermal diode under reverse bias.
- Characterized across a temperature range of 50 – 80 °C.
- Not 100% tested. Specified by design characterization.
- The ideality factor, n, represents the deviat ion from ideal diode behavior as exemplified by
k = Boltzmann Constant, and T = absolute temperature (Kelvin).
- The series resistance, R T, is provided to allow for a more accurate measurement of the
Constant, q = electronic charge. Table 32. Thermal “Diode” Pa rameters using Diode Model
Thermal Specifications and Design Considerations NOTES: 1. Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Same as I FW in Table 32. 3. Characterized across a temperature range of 50–80 °C. 4. Not 100% tested. Specified by design characterization. 5. The ideality factor, nQ, represents the devi ation from ideal transistor model behavior as exemplified by the equation for the collector current: IC = IS * (e qVBE/nQkT –1) Where IS = saturation current, q = electronic charge, VBE = voltage across the transistor base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute temperature (Kelvin). 6. The series resistance, R T, provided in the Diode Model Table (Table 32) can be used for more accurate readings as needed. The processor does not support the diode correction offset that exists on other Intel processors Table 33. Thermal “Diode” Parame ters using Transistor Model Table 34. Thermal Diode Interface
Description
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5.4 Platform Environment Control Interface (PECI)
5.4.1 Introduction
5.4.1.1 Key Difference with Legacy Diode-Based Thermal Management
fan control diagram using PECI temperatures. Figure 26. Processor PECI Topology
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5.4.2 PECI Specifications
5.4.2.1 PECI Device Address
refer to the Platform Environment Control Interface Specification.
5.4.2.2 PECI Command Support
5.4.2.3 PECI Fault Handling Requirements
however, certain scenarios where the PECI is know to be unresponsive. data is not available via PECI. event of a critical or continuous fault condition.
5.4.2.4 PECI GetTemp0() Error Code Support
Table 35. GetTemp0() Error Codes
Features
6 Features
6.1 Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 36. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor; for reset purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset.
6.2 Clock Control and Low Power States
The processor allows the use of AutoHALT and Stop Grant states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 29 for a visual representation of the processor low power states. Table 36. Power-On Configuration Option Signals
- Asserting this signal du ring RESET# will select the corresponding option.
- Address signals not identified in this table as configuration options should not
- Disabling of any of the cores within the processor must be handled by
for the disabling of a single core.
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6.2.1 Normal State
This is the normal operating state for the processor.
6.2.2 HALT and Extended HALT Powerdown States
The processor supports the HALT or Extended HALT powerdown state. The Extended HALT Powerdown must be enabled via the BIOS for the processor to remain within its specification. The Extended HALT state is a lower power state as compared to the Stop Grant State. If Extended HALT is not enabled, the default Powerdown state entered will be HALT. Refer to the following sections for details about the HALT and Extended HALT states.
6.2.2.1 HALT Powerdown State
HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions. When one of the processor cores executes the HALT instruction, that processor core is halted; however, the other processor continues normal operation. The processor transitions to the Normal state upon the occurrence of SMI#, INIT#, or LINT[1:0] (NMI, INTR). RESET# causes the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. Figure 29. Processor Low Power State Machine
The system can generate a STPCLK# while the processor is in the HALT powerdown state. When the system de-asserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in HALT Power powerdown, the processor processes bus snoops.
6.2.2.2 Extended HALT Powerdown State
Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS. When one of the processor cores executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation. The Extended HALT Powerdown state must be enabled via the BIOS for the processor to remain within its specification. The processor automatically transitions to a lower frequency and voltage operating point before entering the Extended HALT state. Note that the processor FSB frequency is not altered; only the internal core frequency is changed. When entering the low power state, the processor first switches to the lower bus ratio and then transitions to the lower VID. While in Extended HALT state, the processor processes bus snoops. The processor exits the Extended HALT state when a break event occurs. When the processor exits the Extended HALT state, it will resume operation at the lower frequency, transitions the VID to the original value and then changes the bus ratio back to the original value.
6.2.3 Stop Grant and Extended Stop Grant States
The processor supports the Stop Grant and Extended Stop Grant states. The Extended Stop Grant state is a feature that must be configured and enabled via the BIOS. Refer to the following sections for details about the Stop Grant and Extended Stop Grant states.
6.2.3.1 Stop Grant State
When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Since the GTL+ signals receive power from the FSB, these signals should not be driven (allowing the level to return to V TT) for minimum power drawn by the termination resistors in this state. In addition, all other input signals on the FSB should be driven to the inactive state. RESET# causes the processor to immediately initialize itself, but the processor will stay in Stop Grant state. A transition back to the Normal state occurs with the de-assertion of the STPCLK# signal. A transition to the Grant Snoop state occurs when the processor detects a snoop on the FSB (see Section 6.2.4). While in the Stop Grant State, SMI#, INIT#, and LINT[1:0] is latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop Grant state, the processor processes a FSB snoop.
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6.2.3.2 Extended Stop Grant State
Extended Stop Grant is a low power state entered when the STPCLK# signal is asserted and Extended Stop Grant has been enabled via the BIOS. The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended Stop Grant state. When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower VID. The processor exits the Extended Stop Grant state when a break event occurs. When the processor exits the Extended Stop Grant state, it will resume operation at the lower frequency, transition the VID to the original value, and then change the bus ratio back to the original value.
6.2.4 Extended HALT State, HALT Snoop State, Extended Stop
Grant Snoop State, and Stop Grant Snoop State The Extended HALT Snoop State is used in conjunction with the new Extended HALT state. If Extended HALT state is not enabled in the BIOS, the default Snoop State entered will be the HALT Snoop State. Refer to the following sections for details on HALT Snoop State, Stop Grant Snoop State and Extended HALT Snoop State, and Extended Stop Grant Snoop State.
6.2.4.1 HALT Snoop State, Stop Grant Snoop State
The processor will respond to snoop transactions on the FSB while in Stop Grant state or in HALT Power Down state. During a snoop transaction, the processor enters the HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB). After the snoop is serviced, the processor returns to the Stop Grant state or HALT Power Down state, as appropriate.
6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State
The processor will remain in the lower bus ratio and VID operating point of the Extended HALT state or Extended Stop Grant state. While in the Extended HALT Snoop State or Extended Stop Grant Snoop State, snoops are handled the same way as in the HALT Snoop State or Stop Grant Snoop State. After the snoop is serviced, the processor will return to the Extended HALT state or Extended Stop Grant state.
6.3 Enhanced Intel ® SpeedStep® Technology
The processor supports Enhanced Intel SpeedStep® Technology. This technology enables the processor to switch between multiple frequency and voltage points, which results in platform power savings. Enhanced Intel SpeedStep Technology requires support for dynamic VID transitions in the platform. Switching between voltage/ frequency states is software controlled. Note: Not all processors are capable of supporting Enhanced Intel SpeedStep® Technology. More details on which processor frequencies support this feature is provided in the Intel® Core™2 Duo Desktop Processor E6000 and E4000 Series and Intel ® Core™2 Extreme Processor X6800 Specification Update. Enhanced Intel SpeedStep® Technology creates processor performance states (P- states) or voltage/frequency operating points. P-states are lower power capability states within the Normal state as shown in Figure 29. Enhanced Intel SpeedStep® Technology enables real-time dynamic switching between frequency and voltage
points. It alters the performance of the processor by changing the bus to core frequency ratio and voltage. This allows the processor to run at different core frequencies and voltages to best serve the performance and power requirements of the processor and system. The processor has hardware logic that coordinates the requested voltage (VID) between the processor cores. The highest voltage that is requested for either of the processor cores is selected for that processor package. Note that the front side bus is not altered; only the internal core frequency is changed. To run at reduced power consumption, the voltage is altered in step with the bus ratio. The following are key features of Enhanced Intel SpeedStep ® Technology:
- Multiple voltage/frequency operating points provide optimal performance at reduced power consumption.
- Voltage/frequency selection is software controlled by writing to processor MSRs (Model Specific Registers), thus eliminating chipset dependency. — If the target frequency is higher than the current frequency, VCC is incremented in steps (+12.5 mV) by placing a new value on the VID signals and the processor shifts to the new frequency. Note that the top frequency for the processor can not be exceeded. — If the target frequency is lower than the current frequency, the processor shifts to the new frequency and VCC is then decremented in steps (-12.5 mV) by changing the target VID through the VID signals. § §
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7 Boxed Processor Specifications
representation of a boxed processor. Guidelines (see Section 1.2) for further guidance. NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Figure 30. Mechanical Represen tation of the Boxed Processor
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7.1 Mechanical Specifications
7.1.1 Boxed Processor Cooling Solution Dimensions
mechanical representation of the boxed processor. assembled fan heatsink are shown in Figure 31 (Side View), and Figure 32 (Top View). (marked with alphabetic designations) to clarify relative dimensioning.
- Diagram does not show the attached hardware fo r the clip design and is provided only as a
Figure 31. Space Requir ements for the Boxed Processor (Side View) Figure 32. Space Requir ements for the Boxed Processor (Top View)
7.1.2 Boxed Processor Fan Heatsink Weight
details on the processor weight and heatsink requirements.
7.1.3 Boxed Processor Retent ion Mechanism and Heatsink
will ship with the heatsink attach clip assembly.
7.2 Electrical Requirements
7.2.1 Fan Heatsi nk Power Supply
contains specifications for the input and output signals at the fan heatsink connector. connector labeled as CONTROL. Figure 33. Space Requir ements for the Boxed Processor (Overall View)
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does not support variable voltage control or 3-pin PWM control. Figure 34. Boxed Processor Fan Heatsi nk Power Cable Connector Description Table 37. Fan Heatsink Power and Signal Specifications
- Baseboard should pull this pin up to 5 V with a resistor.
- Open drain type, pulse width modulated.
- Fan will have pull-up resistor for this signal to maximum of 5.25 V.
polarizing ribs and friction locking ramp. 0.100" pitch, 0.025" square pin width.
7.3 Thermal Specifications
7.3.1 Boxed Processor Cooling Requirements
responsibility of the system integrator. Figure 35. Baseboard Power Header Plac ement Relative to Processor Socket
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Figure 36. Boxed Processor Fan Heatsink Ai rspace Keepout Requirements (side 1 view) Figure 37. Boxed Processor Fan Heatsink Ai rspace Keepout Requirements (Side 2 View)
7.3.2 Fan Speed Control Operation (Intel ® Core2 Extreme
temperature specification (see Chapter 5) is the responsibility of the system integrator.
7.3.3 Fan Speed Control Operation (Intel ® Core2 Duo Desktop
to fan heatsink. The internal chassis temperature should be kept below 38 ºC. responsibility of the system integrator. Table 38 for the specific requirements. Figure 38. Boxed Processo r Fan Heatsink Set Points
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- Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink.
system integrators to have a quieter system in the most common usage. temperature instead of internal ambient chassis temperatures. measured by a thermistor located at the fan inlet. Table 38. Fan Heatsink Power and Signal Specifications this set point, the fan operates at its lowest speed. nominal operating environment. fan operates between its lowest and highest speeds. worst-case operating environment.
8 Balanced Technology Extended
intended for system integrators who build systems from largely standard components. representation of a boxed processor in the 775-land LGA package with a Type I TMA. LGA package with Type II TMA. Guidelines (see Section 1.2) for further guidance. the basic shape and size will remain the same. Figure 39. Mechanical Representation of the Boxed Processor with a Type I TMA
108 Datasheet
the basic shape and size will remain the same.
8.1 Mechanical Specifications
8.1.1 Balanced Technology Extend ed (BTX) Type I and Type II
dimensions for the boxed processor with assembled fan thermal module are shown. Figure 40. Mechanical Representation of the Boxed Processor with a Type II TMA
Figure 41. Requirements for the Balanced Technology Extended (BTX) Type I Keep-out
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8.1.2 Boxed Processor Therma l Module Assembly Weight
thermal module assembly requirements. Figure 42. Requirements for the Balanced Tech nology Extended (BTX) Type II Keep-out
8.1.3 Boxed Processo r Support and Retention Module (SRM)
and screws for attachment. The SRM must be supplied by the chassis hardware vendor. keepout zones. Figure 43 illustrates the assembly stack including the SRM. Figure 43. Assembly Stack Including the Support and Retention Module
- H e a t s i n k & F a n
- C l i p
- S t r u c t u r a l D u c t Motherboard SRM Chassis Pan
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8.2 Electrical Requirements
8.2.1 Thermal Module Assembly Power Supply
The boxed processor's Thermal Module Assembly (TMA) requires a +12 V power supply. Figure 44. Baseboards must provide a compatible power header to support the boxed processor. Table 39contains specifications for the input and output signals at the TMA. th pin of the connector labeled as CONTROL. support variable voltage control or 3-pin PWM control. should be positioned within 4.33 inches from the center of the processor socket. Figure 44. Boxed Processor TMA Po wer Cable Connector Description polarizing ribs and friction locking ramp. 0.100" pitch, 0.025" square pin width.
Table 39. TMA Power and Signal Specifications
- Baseboard should pull this pin up to 5V with a resistor.
- Open Drain Type, Pulse Width Modulated.
- Fan will have a pull-up resistor for this signal to maximum 5.25 V.
Figure 45. Balanced Technology Extended (BTX) Mainboard Power Header Placement
Balanced Technology Extended (BTX) Boxed Processor Specifications
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8.3 Thermal Specifications
This section describes the cooling requirements of the thermal module assembly solution used by the boxed processor.
8.3.1 Boxed Processor Cooling Requirements
The boxed processor may be directly cooled with a TMA. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor case temperature specification is listed in Chapter 5. The boxed processor TMA is able to keep the processor temperature within the specifications (see Table 26) for chassis that provide good thermal management. For the boxed processor TMA to operate properly, it is critical that the airflow provided to the TMA is unimpeded. Airflow of the TMA is into the duct and out of the rear of the duct in a linear flow. Blocking the airflow to the TMA inlet reduces the cooling efficiency and decreases fan life. Filters will reduce or impede airflow which will result in a reduced performance of the TMA. The air temperature entering the fan should be kept below 35.5 °C. Meeting the processor's temperature specification is the responsibility of the system integrator. In addition, Type I TMA must be used with Type I chassis only and Type II TMA with Type II chassis only. Type I TMA will not fit in a Type II chassis due to the height difference. In the event a Type II TMA is installed in a Type I chassis, the gasket on the chassis will not seal against the Type II TMA and poor acoustic performance will occur as a result.
8.3.2 Variable Speed Fan
The boxed processor fan operates at different speeds over a short range of temperatures based on a thermistor located in the fan hub area. This allows the boxed processor fan to operate at a lower speed and noise level while thermistor temperatures are low. If the thermistor senses a temperatures increase beyond a lower set point, the fan speed will rise linearly with the temperature until the higher set point is reached. At that point, the fan speed is at its maximum. As fan speed increases, so do fan noise levels. These set points are represented in Figure 46 and Table 40. The internal chassis temperature should be kept below 35.5 ºC. Meeting the processor’s temperature specification (see Chapter 5) is the responsibility of the system integrator. Note: The motherboard must supply a constant +12 V to the processor’s power header to ensure proper operation of the variable speed fan for the boxed processor (refer to Table 40) for the specific requirements).
- Set point variance is approximately ±1°C from Thermal Module Assembly to Thermal
boxed processor will operate as described in the following paragraphs. system integrators to have a quieter system in the most common usage. Figure 46. Boxed Processor TMA Set Points Table 40. TMA Set Points for 3-wire oper ation of BTX Type I and Type II Boxed operates between its lowest and highest speeds. worst-case operating environment.
Balanced Technology Extended (BTX) Boxed Processor Specifications
116 Datasheet
the motherboard that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL. The fan speed is based on a combination of actual processor temperature and thermistor temperature. If the 4-wire PWM controlled fan in the TMA solution is connected to a 3-pin baseboard processor fan header it will default back to a thermistor controlled mode, allowing compatibility with existing 3-pin baseboard designs. Under thermistor controlled mode, the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet. For more details on specific motherboard requirements for 4-wire based fan speed control, refer to the appropriate Thermal and Mechanical Design Guidelines (see Section 1.2). § §
Debug Tools Specifications
9 Debug Tools Specifications
9.1 Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of systems, the LAI is critical in providing the ability to probe and capture FSB signals. There are two sets of considerations to keep in mind when designing a system that can make use of an LAI: mechanical and electrical.
9.1.1 Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI lands plug into the processor socket, while the processor lands plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keepout volume remains unobstructed inside the system. Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor’s heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as part of the LAI.
9.1.2 Electrical Considerations
The LAI will also affect the electrical performance of the FSB; therefore, it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution it provides. § §
Debug Tools Specifications