305433

80333 INTEL | Alldatasheet

Document overview

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• PDF pages: 75

Technical content

Datasheet sections

• 1.0 Introduction
• 1.1 About This Document
• 1.1.1 Terminology
• 1.1.2 Other Relevant Documents
• 1.2 About the Intel
• 2.0 Features
• 2.1 Intel XScale ® Core
• 2.2 PCI Express*-to-PCI Bridge Units
• 2.3 Address Translation Unit
• 2.4 Memory Controller
• 2.5 Application Accelerator Unit
• 2.6 Peripheral Bus Interface
• 2.7 DMA Controller
• 2.9 Messaging Unit
• 2.10 Internal Bus
• 2.11 UART Units
• 2.12 Interrupt Controller Unit
• 2.13 GPIO
• 2.14 SMBus Unit
• 3.0 Package Information
• 3.1 Functional Signal Descriptions
• 3.2 Package Thermal Specifications
• 4.0 Electrical Specifications
• 4.1 Absolute Maximum Ratings
• 4.2 V CCPLL Pin Requirements
• 4.3 Targeted DC Specifications
• 4.4 Targeted AC Specifications
• 4.4.1 Clock Signal Timings
• 4.4.2 DDR/DDR-II SDRAM Interface Signal Timings
• 4.4.3 Peripheral Bus Interface Signal Timings
• 4.4.5 UART Interface Signal Timings
• 4.4.6 PCI Express* Differential Transmitter (Tx) Output Specifications
• 4.4.7 PCI Express* Differential Receiver (Rx) Input Specifications
• 4.4.8 Boundary Scan Test Signal Timings
• 4.6 AC Test Conditions
• 1 Intel ® 80333 I/O Processor Functional Block Diagram

Order Number: 305433, Revision: 003US July 2005 Intel® 80333 I/O Processor Datasheet Product Features ■ Integrated Intel XScale® core —500, 667 and 800 MHz —ARM* V5TE Compliant —32 KByte, 32-way Set Associative Instruction Cache with cache locking —32 KByte, 32-way Set Associative Data Cache with cache locking. Supports write through or write back —2 KByte, 2-way Set Associative Mini- Data Cache —128-Entry Branch Target Buffer —8-Entry Write Buffer —4-Entry Fill and Pend Buffer —Performance Monitor Unit ■ Internal Bus 333 MHz/64-bit ■ PCI Express*-to-PCI Bridges —x8 PCI Express* Upstream Link —PCI Express* Specification 1.0a compliant —PCI-X Bus A (IOP bus - ATU interface) —PCI-X Bus B (Slot Expansion bus) supports standard PCI Hot-Plug Controller —Four output clocks per PCI-X bus ■ Address Translation Unit —2 KB or 4 KB Outbound Read Queue —4 KB Outbound Write Queue —4 KB Inbound Read and Write Queue —Connects Internal Bus to PCI/X Bus A —Messaging Unit and Expansion ROM ■ Two Programmable 32-bit Timers and Watchdog Timer ■ Eight General Purpose I/O Pins ■ Two I2C Bus Interface Units ■ Dual-Ported Memory Controller —PC2700 Double Data Rate (DDR333) SDRAM —DDRII 400 SDRAM —Up to 2 GB of 64-bit DDR333 —Up to 1 GB of 64-bit DDRII400 —Optional Single-bit Error Correction, Multi-bit Detection Support (ECC) —Supports Unbuffered or Registered DIMMs and Discrete SDRAM —32-bit memory support ■ DMA Controller —Two Independent Channels Connected to Internal Bus —Two 1KB Queues in Ch0 and Ch1 —CRC-32C Calculation ■ Application Accelerator Unit —RAID6 support —Performs optional XOR on Read Data —Compute Parity Across Local Memory Blocks —1 KB/512 byte Store Queue ■ Two UART (16550) Units —64-byte Receive and Transmit FIFOs —4-pin, Master/Slave Capable ■ Peripheral Bus Interface — 8-/16-bit Data Bus with Two Chip Selects ■ Interrupt Controller Unit —Four Priority Levels —Vector Generation —Sixteen External Interrupt Pins with High Priority Interrupt (HPI#) ■ 829-Ball, Flip Chip Ball Grid Array (FCBGA) —37.5 mm 2 and 1.27 mm ball pitch

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Legal Lines and Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY , RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY , OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained b y calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile , i386, i486, i960, iCOMP, InstantIP, Intel, Intel Centrino, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, VoiceBrick, VTune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2005, Intel Corporation. All Rights Reserved.

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Datasheet Intel® 80333 I/O Processor Datasheet July 2005 Order Number: 305433, Revision: 003US 5

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Revision History

July 2005 003 Updated voltages in Section 4.3 May 2005 002 Revised: Table 16, modified pin mode behavior for DQ[63:32] for 32-bit DDR. Table 21, modified Case Temperature Under Bias to 95 C Max Table 22, modified Case Temperature Under Bias to 95 C Max Table 25, added note 4 March 2005 001 Initial release

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1.0 Introduction

1.1 About This Document

This document is the Intel® 80333 I/O Processor Datasheet. This document contains a functional overview, package signal locations, targeted electrical specifications, and bus functional waveforms. Detailed functional descriptions other than parametric performance are published in the Intel® 80333 I/O Processor Developer’ s Manual. Intel Corporation assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notice. In particular, descriptions of features, timings, packaging, and pin-outs does not imply a commitment to implement them. In fact, this specification does not imply a commitment by Intel to design, manufacture, or sell the product described herein.

1.1.1 Terminology

To aid the discussion of the Intel® 80333 I/O processor (80333) architecture, the following terminology is used: Core processor Intel XScale ® core within the 80333 Local processor Intel XScale ® core within the 80333 Host processor Processor loca ted upstream from the 80333 Local bus 80333 Internal Bus Local memory Memory subsystem on the Intel XScale ® core DDR SDRAM or Peripheral Bus Interface busses Inbound At or toward the Internal Bus of the 80333 from the PCI interface of the ATU Outbound At or toward the PCI interface of the 80333 ATU from the Internal Bus Downstream At or toward a PCI Express* port directed away from the root complex (to a bus with a higher number) Upstream At or toward a PCI Express* port directed to the PCI Express* root complex (to a bus with a lower number). QWORD 64-bit data quantity (8 bytes). DWORD 32-bit data quantity (4 bytes). word 16-bit data quantity (2 bytes).

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1.1.2 Other Relevant Documents

1. Intel XScale® Core Developer’ s Manual (273473) — Intel Corporation 2. PCI Hot-Plug Specification, Revision 1.1 — PCI Special Interest Group 3. PCI Express* Specification, Revision 1.0a — PCI Special Interest Group 4. Intel® 80333 I/O Processor Developer’ s Manual (305432) — Intel Corporation 5. Intel® 80333 I/O Processor Design Guide (305434) — Intel Corporation 6. Intel® 80333 I/O Processor Specification Update (305435) — Intel Corporation 7. PCI Local Bus Specification, Revision 2.3 — PCI Special Interest Group 8. PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a — PCI Special Interest Group 9. PCI Bus Power Management Interface Specification, Revision 1.1 — PCI Special Interest Group

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1.2 About the Intel ® 80333 I/O Processor

The 80333 is a multi-function device that integrates the Intel XScale® core (ARM* architecture compliant) with intelligent peripherals and PCI Express*-to-PCI Bridges. The 80333 consolidates, into a single system:

• Intel XScale® core
• ×8 PCI Express* Upstream Link
• Two PCI Express*-to-PCI Bridges supporting PCI-X interface on both segments
• PCI Standard Hot-Plug Controller (segment B)
• Address Translation Unit (PCI-to-Internal Bus Application Bridge) interfaced to the segment A
• High-Performance Memory Controller
• Interrupt Controller with up to 16 external interrupt inputs
• Two Direct Memory Access (DMA) Controllers
• Application Accelerator
• Messaging Unit
• Peripheral Bus Interface Unit
• Two I2C Bus Interface Units
• Two 16550 compatible UARTs with flow control (four pins)
• Eight General Purpose Input Output (GPIO) ports The 80333 is an integrated processor that addresses the needs of intelligent I/O applications and helps reduce intelligent I/O system costs. PCI Express* is an industry-standard, high-performance, low-latency system interconnect. The PCI Express* upstream link of the 80333 is capable of ×8 lane widths at 2.5 GHz operation, as defined by the PCI Express* Specification, Revision 1.0a. The addition of the Intel XScale® core brings intelligence to the PCI Express*-to-PCI Bridges. The 80333 integrates PCI Express*-to-PCI Bridges with the ATU as an integrated secondary PCI device. The Upstream PCI Express* port implements the PCI-to-PCI Bridge programming model according to the PCI Express* Specification, Revision 1.0a. The Primary Address Translation Unit is compliant with the definitions of an “application bridge” as found in the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. Figure 1 on page 10 is a functional block diagram of the 80333.

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Figure 1. Intel ® 80333 I/O Processor Functional Block Diagram

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2.0 Features

The Intel® 80333 I/O processor combines the Intel XScale® core with powerful new features to create an intelligent I/O processor. This multi-device I/O processor is fully compliant with the PCI Local Bus Specification, Revision 2.3 and the PCI Express* Specification, Revision 1.0a. Features specific to the 80333 include the following: The subsections that follow briefly overview each feature. Refer to the Intel® 80333 I/O Processor Developer’ s Manual for full technical descriptions.

2.1 Intel XScale ® Core

The 80333 is based upon the Intel XScale® core. The core processor operates at a maximum frequency of 800 MHz. The instruction cache is 32 Kbytes in size and is 32-way set associative. Also, the core processor includes a data cache that is 32 Kbytes and is 32-way set associative, and a mini data cache that is 2 Kbytes and is two-way set associative.

2.2 PCI Express*-to-PCI Bridge Units

The 80333 provides PCI Express*-to-PCI Bridge units. These bridge units share a common upstream PCI Express* interface compliant with the PCI Express* Specification, Revision 1.0a. The PCI Express* interface supports a port lane width of eight, for up to 2 Gbytes/s per direction (4 Gbytes/s total) at 2.5 Gbits/s bit rate. The PCI-X secondary interfaces support 64-bit 133 MHz, compliant with the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. These two secondary PCI bus interfaces are referred to as the ‘A’ and ‘B’ segment, where the 80333 Address Translation Unit resides on ‘A’ segment. The ‘B’ PCI bus interface can be used for slot expansion.

• Intel XScale® core
• Application Accelerator Unit
• Address Translation Unit
• Memory Controller
• Peripheral Bus Interface
• Two I2C Bus Interface Units
• PCI Express* 2.5 GHz ×8 link
• Interrupt Controller Unit
• Messaging Unit
• Internal Bus
• Two DMA Controllers
• Two UART Units
• Eight GPIOs
• Two PCI Express*-to-PCI Bridges to secondary PCI-X 133 MHz Bus interfaces

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2.3 Address Translation Unit

An Address Translation Unit (ATU) allows PCI transactions direct access to the 80333 local memory. The ATU supports transactions between PCI address space and 80333 address space. Address translation for the ATU is controlled through programmable registers accessible from both the PCI interface and the Intel XScale ® core. The PCI interface of the ATU is connected to the 80333 “A” Secondary PCI interface of the bridge. Upstream access to the PCI Express* interface is controlled by inverse decode with the address windows of the bridge. Dual access to registers allows flexibility in mapping the two address spaces. The ATU also supports the power management extended capability configuration header that as defined by the PCI Bus Power Management Interface Specification, Revision 1.1.

2.4 Memory Controller

The Memory Controller allows direct control of a DDR SDRAM memory subsystem. It features programmable chip selects and support for error correction codes (ECC). The memory controller may be configured for DDR SDRAM at 333 MHz (with 500 MHz and 667 MHz processors) or DDR-II SDRAM at 400 MHz (with 500 MHz and 800 MHz processors). The memory controller is dual-ported, with a dedicated interface for the Intel XScale ® core Bus Interface Unit and a second interface to the Internal Bus. The memory controller supports pipelined access and arbitration control to maximize performance. The memory controller interface configuration support includes Unbuffered DIMMs, Registered DIMMs, and discrete DDR SDRAM devices. External memory may be configured as host addressable memory or private 80333 memory utilizing the Address Translation Unit and Bridges.

2.5 Application Accelerator Unit

The Application Accelerator Unit (AA) provides low-latency, high-throughput data transfer capability between the AA unit, the 80333 local memory and the PCI bus. It executes data transfers from and to the 80333 local memory, from the PCI bus to the 80333 local memory, or from the 80333 local memory to the PCI bus. The AA unit performs XOR operations, computes parity, generates and verifies an eight byte data integrity field, performs memory block fills, and provides the necessary programming interface. The AA unit in the 80333 has been enhanced to support RAID 6 functionality.

2.6 Peripheral Bus Interface

The Peripheral Bus Interface Unit is a data communication path to the flash memory components or other peripherals of an 80333 hardware system. The PBI includes support for either 8/16 bit devices. To perform these tasks at high bandwidth, the bus features a burst transfer capability which allows successive 8/16-bit data transfers.

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2.7 DMA Controller

The DMA Controller allows low-latency, high-throughput data transfers between PCI bus agents and the local memory. Two separate DMA channels accommodate data transfers to the PCI bus. Both channels include a local memory to local memory transfer mode. The DMA Controller supports chaining and unaligned data transfers. It is programmable through the Intel XScale® core only.

2.8 I 2C Bus Interface Unit

The I2C (Inter-Integrated Circuit) Bus Interface Unit allows the Intel XScale® core to serve as a master and slave device residing on the I2C bus. The I2C unit uses a serial bus developed by Philips Semiconductor*, consisting of a two-pin interface. The bus allows the 80333 to interface to other I2C peripherals and microcontrollers for system management functions. It requires a minimum of hardware components for an economical system to relay status and reliability information on the I/O subsystem to an external device. Also refer to I2C Peripherals for Microcontrollers (Philips Semiconductor). The 80333 includes two I2C bus interface units.

2.9 Messaging Unit

The Messaging Unit (MU) provides data transfer between the PCI system and the 80333. It uses interrupts to notify each system when new data arrives. The MU has four messaging mechanisms:

• Message Registers
• Doorbell Registers
• Circular Queues
• Index Registers Each messaging mechanism allows a host processor or external PCI device and the 80333 to communicate through message passing and interrupt generation.

2.10 Internal Bus

The Internal Bus is a high-speed interconnect between internal units and Intel XScale® core processor. The Internal Bus operates at 333 MHz and is 64 bits wide.

2.11 UART Units

The 80333 includes two UART unit. The UART units allow the Intel XScale® core to serve as a master and slave device residing on the UART bus. The UART units use a serial bus consisting of a four-pin interface. The bus allows the 80333 to interface to other peripherals and microcontrollers. Also refer to 16550 Device Specification (National Semiconductor*).

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2.12 Interrupt Controller Unit

The Interrupt Controller Unit (ICU) aggregates interrupt sources both external and internal of the 80333 to the Intel XScale® core processor. The ICU supports high performance interrupt processing with direct interrupt service routine vector generation on a per source basis. Each source has programmability for masking, core processor interrupt input, and priority.

2.13 GPIO

The 80333 includes eight General Purpose I/O (GPIO) pins which can also be used as external interrupt inputs.

2.14 SMBus Unit

The SMBus (System Management Bus) Interface Unit allows the 80333 to serve as a slave device on the SMBus. SMBus is based on the principles of the I 2C bus and allows the 80333 to interface to system SMBus for external access and control of internal registers.

3.0 Package Information

package with 829 ball connections.

3.1 Functional Signal Descriptions

Table 1. Pin Description Nomenclature I/O Pin may be either an input or output.

• Pin must be connected as described.

Synchronous. Signal meets timings relative to a clock. Rst(R) The pin is reset with PWRGD or RSTIN#. asserted or is asserted with software. Rst(T) The pin is reset with TRST#.

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Table 2. DDR SDRAM Signals clocks to the external SDRAM memory subsystem. clocks to the external SDRAM memory subsystem. been reset with RSTIN# or PWRGD or a software reset. column addresses to the SDRAM memory banks. valid row address on the Multiplexed Address Bus MA[12:0]. transaction is a write operation. memory access (Physical banks 0 and 1). SDRAM Data Bus carries 64-bit data to and from memory. are driven to determinate values. from memory during data cycles. devices do not accept valid data from the byte lanes.

Table 3. DDR-II SDRAM Signals source synchronous data transfer. DDRRES[2:1] 2I / O Compensation For DDR OCD (analog) DDR-II mode only. Table 4. MISC SDRAM Signals rate control connected through a resistor to DDRCRES0. impedance control connected through a resistor to DDRCRES0.

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Table 5. Peripheral Bus Interface Signals 8 Mbytes per peripheral device. “Reset Strap Signals” on page 29” for a functional description. write data, depending on the corresponding bus width. drives unused bus pins high or low. specifies the number of data transfers during the bus transaction. “Reset Strap Signals” on page 29” for a functional description. represent the current byte address in the bursted transaction. for an 8-bit wide peripheral. Strap Signals” on page 29” for a functional description. Address Latch Enable indicates the transfer of a physical address. during the second address cycle. input on peripheral devices. and controls the WE# input on the ROM. valid during the entire bus access. valid during the entire bus access.

**Table 6. PCI Express* Signals**

• ×8 Mode: All PE0Tp[7:0] and PE0Tn[7:0] signals are used.
• ×4 Mode: Only PE0Tp[3:0] and PE0Tn[3:0] signals are used. PE0Rp[7:0]/ PE0Rn[7:0] 16 I PCI Express* Serial Data Receive: These eight differential input pairs receive data and embedded clock for port 0.
• ×8 Mode: All PE0Rp[7:0] and PE0Rn[7:0] signals are used.
• ×4 Mode: Only PE0Rp[3:0] and PE0Rn[3:0] signals are used. PE_RCOMPO 1I PCI EXPRESS RCOMP: Connected to external reference resistor. Output current path, used to compensate PCI Express* driver and RX termination. PE_ICOMPI 1I PCI EXPRESS RCOMP IN: Connected to the same external resistor as PE_RCOMPO on the board, for input voltage sensing comparator. Total 36

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Table 7. B PCI (Slot Expansion) Bus Signals (Sheet 1 of 2) driven during the data phase. capable. This signal is only valid for Hot-Plug 1-slot mode. B-segment secondary PCI bus.

it indicates that valid data is present on the Address/Data bus. it indicates that valid data is present on the Address/Data bus. During a write, it indicates the target is ready to accept the data. whether or not an agent has been selected. establishing a LOCK across the bridge. occurs during a PCI bus transaction. B PCI Bus 66 MHz Enable indicates the speed of the PCI bus. when low, the bus speed is 33 MHz. the device or system power state. frequency capabilities. Non-standard, special purpose analog pin. secondary bus clocks are enabled. transactions. Typically connected on the board to B_CLKOUT. Provides timing clock for all B-segment PCI interfaces.

• PCI output signals are driven to a known consistent state.
• PCI bus interface output signals are three-stated.
• open drain signals such as B_SERR# are floated B_RST# may be asynchronous to B_CLKIN when asserted or deasserted. Although asynchronous, deassertion must be guaranteed to be a clean, bounce-free edge. B_RCOMP 1I / O PCI Resistor Compensation Pin is an analog pad that connects to a board resistor to control all B segment PCI output driver strengths (analog). Total 106

Table 7. B PCI (Slot Expansion) Bus Signals (Sheet 2 of 2)

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Table 8. A PCI (IOP) Bus Signals (Sheet 1 of 2) A PCI Address/Data is the upper 32 bits of the PCI data bus. during secondary PCI data phases. transaction on the secondary PCI bus. whether or not an agent has been selected.

• PCI output signals are driven to a known consistent state.
• PCI bus interface output signals are three-stated.
• Open drain signals such as A_SERR#are floated. A_RST# may be asynchronous to A_CLKIN when asserted or deasserted. Although asynchronous, deassertion must be ensured to be a clean, bounce-free edge. A_PERR# 1 I/O Sync(A) Rst(A) A PCI Bus Parity Error is asserted when a data parity error during a secondary PCI bus transaction. A_LOCK# 1 I/O Sync(A) Rst(A) A PCI Bus Lock indicates the need to perform an atomic operation on the secondary PCI bus. A_CLKO[3:0] 4O A PCI Bus Output Clocks are used to drive external logic on the secondary PCI bus. A_CLKOUT 1O A PCI Bus Output Clock is used to drive A_CLKIN when the IO processor provides secondary bus clocks. A_CLKIN 1I A PCI Bus Input Clock provides the timing for all PCI transactions. Typically connected on the board to A_CLKOUT. Provides the timing clock for all A segment PCI interfaces. A_M66EN 1I / O A PCI Bus 66 MHz Enable indicates the speed of the secondary PCI bus. When this signal is high, the bus speed is 66 MHz and when it is low, the bus speed is 33 MHz. A_PME# 1 I Sync(A) Power Management Event signal is used to request a change in the device or system power state. A_REQ[3:0]# 4 I Sync(A) A PCI Bus Requests are the request signals from devices 3 through 0 on the A PCI bus. A_GNT[3:0]# 4 O Sync(A) Rst(A) A PCI Bus Grant are grant signals sent to devices 3 through 0 on the A PCI bus. A_PCIXCAP 1I A PCI-X Capability is an analog pad that selects PCI/X mode and frequency capabilities. Non-standard, special purpose analog pin. A_RCOMP 1I / O PCI Resistor Compensation Pin is an analog pad that connects to the board resistor to control all A segment PCI output driver strengths (analog). Total 103

Table 8. A PCI (IOP) Bus Signals (Sheet 2 of 2)

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Table 9. Interrupt Signals the FIQ or IRQ internal interrupt input of the core. These interrupt pins are level sensitive. Table 10. I 2C/SMBus Signals SCL0 1I / O I 2C Clock provides synchronous operation of the I 2C bus zero. SCD0 1I / O I 2C Data is used for data transfer and arbitration of the I2C bus zero. SCL1/SCLK 1I / O I2C Clock provides synchronous operation of the I 2C bus zero. SM Bus Clock provides synchronous operation of the SM bus. SCD1/SDTA 1I / O I2C Data is used for data transfer and arbitration of the I2C bus zero. SM Bus Data is used for data transfer and arbitration of the SM bus.

Table 11. Hot-Plug Controller Signa ls for Parallel 1-slot, No-Glue may assert a slot reset and disconnects the slot from the bus. signals are directly connected to the present bits on the PCI card. signals are directly connected to the present bits on the PCI card. “on”, therefore, it does not tri-state during boundary scan.

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Table 12. UART Signals (Sheet 1 of 2) MARKING (logic 1) state upon a Reset operation. disabling the UART with the IER register. CTS# is high, no data is transmitted. level back to the threshold.

Serial Input: Serial data input from device pin to receive shift register. MARKING (logic 1) state upon a Reset operation. disabling the UART with the IER register. CTS# is high, no data is transmitted. level back to the threshold. Table 12. UART Signals (Sheet 2 of 2)

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Table 13. Test and Miscellaneous Signals ensure proper operation when this pin is not being driven. behavior of TDO is independent of RSTIN# or PWRGD. the operation of the test logic for IEEE 1149 Boundary Scan testing. This pin has a weak internal pull-up. N/C 7- No Connect. Do not connect to any signal, power or ground. command to be sent to the DDR SDRAM array.

• PCI output signals are driven to a known consistent state.
• PCI bus interface output signals are three-stated.
• Open drain signals such as B_SERR# are floated. RSTIN# may be asynchronous to B_CLKIN when asserted or deasserted. Although asynchronous, deassertion must be ensured to be a clean, bounce-free edge. Total 15

Table 14. Reset Strap Signals (Sheet 1 of 2) the PCI configuration and status register. for Functional Modes” on page 36. for Functional Modes” on page 36. sets the default bus width for the PBI Memory Boot window. for Functional Modes” on page 36. for Functional Modes” on page 36. maximum PCI-X mode operating frequency. 0 = 100 MHz enabled (Requires pull down resistor). 1 = 133 MHz enabled (Default mode). for Functional Modes” on page 36. PCI-X mode operating frequency. for Functional Modes” on page 36.

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Multiplexing for Functional Modes” on page 36. Multiplexing for Functional Modes” on page 36. valid for both A and B segments. 0 = ODT disabled (Requires pull-down resistor). 1 = ODT enabled (Default mode). for Functional Modes” on page 36. Pull-down Resistor is required for default mode. for Functional Modes” on page 36. Table 14. Reset Strap Signals (Sheet 2 of 2)

Table 15. Power and Ground Pins loop clock generator. It is to be connected to the board VCC15 plane. ® 80333 I/O Processor Design Guide for more information. VCC33 49 PWR 3.3 V Power balls to be connected to a 3.3 V power board plane. board plane, dependent on DDR or DDRII mode. 1.5 V Power balls to be connected to a 1.5 V power board plane. CC13 7P W R 1.3 V Power balls to be connected to a 1.35 V power board plane. analog reference circuit, separated from all other VCC signals. to the differential inputs of the memory controller pins. SS 218 GND Ground balls to be connected to a ground board plane. VCCPLL filter, and not to board ground. reference circuit, separated from all other VSS signals.

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Table 16. Pin Mode Behavior (Sheet 1 of 4)

1. Clocks become valid right before M_RST# deasserts.
2. ODT signal to be low during power up and initialization per DDR-II JEDEC specification.
3. High impedance common mode DC voltage driven per PCI Express* Specification, Revision 1.0.
4. Input Disabled, but termination on, per PCI Express* Specification, Revision 1.0.
5. Hot-Plug Controller signals are pulled up when SHPC is disabled (B_HSLOT[3] = 0 on rising edge of

Table 16. Pin Mode Behavior (Sheet 2 of 4)

1. Clocks become valid right before M_RST# deasserts.
2. ODT signal to be low during power up and initialization per DDR-II JEDEC specification.
3. High impedance common mode DC voltage driven per PCI Express* Specification, Revision 1.0.
4. Input Disabled, but termination on, per PCI Express* Specification, Revision 1.0.
5. Hot-Plug Controller signals are pulled up when SHPC is disabled (B_HSLOT[3] = 0 on rising edge of

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Table 16. Pin Mode Behavior (Sheet 3 of 4)

1. Clocks become valid right before M_RST# deasserts.
2. ODT signal to be low during power up and initialization per DDR-II JEDEC specification.
3. High impedance common mode DC voltage driven per PCI Express* Specification, Revision 1.0.
4. Input Disabled, but termination on, per PCI Express* Specification, Revision 1.0.
5. Hot-Plug Controller signals are pulled up when SHPC is disabled (B_HSLOT[3] = 0 on rising edge of

Table 16. Pin Mode Behavior (Sheet 4 of 4)

1. Clocks become valid right before M_RST# deasserts.
2. ODT signal to be low during power up and initialization per DDR-II JEDEC specification.
3. High impedance common mode DC voltage driven per PCI Express* Specification, Revision 1.0.
4. Input Disabled, but termination on, per PCI Express* Specification, Revision 1.0.
5. Hot-Plug Controller signals are pulled up when SHPC is disabled (B_HSLOT[3] = 0 on rising edge of

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Table 17. Pin Multiplexing for Functional Modes

Figure 2. 829-Ball FCBGA Package Diagram Table 18. FC-style, H-PBGA Package Dimensions

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Figure 3. Intel ® 80333 I/O Processor Signal Group Locations (Bottom View)

Figure 4. Intel ® 80333 I/O Processor Ballout — Left Side (Bottom View)

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Figure 5. Intel ® 80333 I/O Processor Ballout — Right Side (Bottom View)

Table 19. 829-Lead Package — Alphabetical Ball Listings (Sheet 1 of 7)

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Table 19. 829-Lead Package — Alphabetical Ball Listings (Sheet 2 of 7)

Table 19. 829-Lead Package — Alphabetical Ball Listings (Sheet 3 of 7)

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Table 19. 829-Lead Package — Alphabetical Ball Listings (Sheet 4 of 7)

Table 19. 829-Lead Package — Alphabetical Ball Listings (Sheet 5 of 7)

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Table 19. 829-Lead Package — Alphabetical Ball Listings (Sheet 6 of 7)

Table 19. 829-Lead Package — Alphabetical Ball Listings (Sheet 7 of 7)

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Table 20. 829-Lead Package — Alphabetical Signal Listings (Sheet 1 of 7)

Table 20. 829-Lead Package — Alphabetical Signal Listings (Sheet 2 of 7)

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Table 20. 829-Lead Package — Alphabetical Signal Listings (Sheet 3 of 7)

Table 20. 829-Lead Package — Alphabetical Signal Listings (Sheet 4 of 7)

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Table 20. 829-Lead Package — Alphabetical Signal Listings (Sheet 5 of 7)

Table 20. 829-Lead Package — Alphabetical Signal Listings (Sheet 6 of 7)

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Table 20. 829-Lead Package — Alphabetical Signal Listings (Sheet 7 of 7)

Datasheet Intel® 80333 I/O Processor Datasheet May 2005 Order Number: 305433, Revision: 002 55

3.2 Package Thermal Specifications

See Intel® 80333 I/O Processor Thermal Design Guidelines Application Note (306630).

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4.0 Electrical Specifications

4.1 Absolute Maximum Ratings

4.2 V CCPLL Pin Requirements

Table 21. Absolute Maximum Ratings WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. exposure beyond the Operating Conditions may affect device reliability. Table 22. Operating Conditions

1.35 V Intel XScale® core Supply

1. ±3% DC; additional ±2% for AC transients. Under no circumstance may the supply voltage go past the

4.3 Targeted DC Specifications

Table 23. DC Characteristics

1. For 2.5 V DDR SDRAM support.
2. For 1.8 V DDR-II SDRAM support.
3. Miscellaneous signals include all signals that are not PCI-X or SDRAM signals.
4. Includes PCI-X Express Auxiliary signals; PWRGD

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Table 24. I CC Characteristics

800 MHz

667 MHz

500 MHz

1. Measured with device operating and outputs loaded to the test condition in Figure 14, “AC Test Load

for All Signals Except PCI and DDR SDRAM” on page 73.

1. I CC Active (Thermal) value is provided for selecting the system thermal design power (TDP). This is
2. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.

4.4 Targeted AC Specifications

4.4.1 Clock Signal Timings

Table 25. PCI Clock Timings

1. Clock frequency may not change beyond spread-spectrum limits except while RSTIN# is asserted or PWRGD
2. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform.
3. The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter.
4. Clock jitter class 2, per PCI-X Electr ical and Mechanical Rev 2.0a specification

Table 26. DDR Clock Timings

1. This specification applies for writes only; that is, when the 80333 is driving the strobes as well as the clocks. Refer to the

JEDEC specification for an explanation of strobe to clock timing for DDR reads.

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**Table 27. PCI Express* Clock Timings**

1. Spread spectrum clocking is allowed with the following three requirements;

the existing non-spread spectrum specifications. for modulation above the nominal frequency. This technique is often called “down-spreading”.

1. Measured at crossing point.
2. Measured from V OL = 0.2 V to VOH =0 . 8V .
3. Determined as a fraction of 2 × (Trise - Tfall)/(Trise + Tfall).

4.4.2 DDR/DDR-II SDRAM Interface Signal Timings

Table 28. DDR SDRAM Signal Timings

1. See Figure 7, “Output Timing Measurement Waveforms” on page 69.
2. See Figure 8, “Input Timing Measurement Waveforms” on page 70.
3. Clock to output valid times are specified with a 0 pF loading.
4. See Figure 11, “DDR SDRAM Write Timings” on page 71.
5. See Figure 13 “DQS falling edge output access time to M_CK rising edge.
6. See Figure 12, “DDR SDRAM Read Timings” on page 71. Data to strobe read setup and data from
7. See Figure 13, “Write PreAmble/PostAmble Durations” on page 72.
8. See Figure 15, “AC Test Load for DDR SDRAM Signals” on page 73.
9. Address/Command pin group;

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Table 29. DDR-II SDRAM Signal Timings

1. See Figure 7, “Output Timing Measurement Waveforms” on page 69.
2. See Figure 8, “Input Timing Measurement Waveforms” on page 70.
3. Clock to output valid times are specified with a 0 pF loading.
4. See Figure 11, “DDR SDRAM Write Timings” on page 71.
5. See Figure 13 “DQS falling edge output access time to M_CK rising edge.
6. See Figure 12, “DDR SDRAM Read Timings” on page 71. Data to strobe read setup and data from
7. See Figure 15, “AC Test Load for DDR SDRAM Signals” on page 73.
8. Address/Command pin group: RAS#, CAS#, WE#, MA[12:0], BA[1:0], ODT[1:0] .
9. See Figure 13, “Write PreAmble/PostAmble Durations” on page 72.

4.4.3 Peripheral Bus Interface Signal Timings

Table 30. Peripheral Bus Signal Timings

1. See Figure 7, “Output Timing Measurement Waveforms” on page 69.
2. See Figure 8, “Input Timing Measurement Waveforms” on page 70.
3. See Figure 14, “AC Test Load for All Signals Except PCI and DDR SDRAM” on page 73.
4. See Table 32, AC Measurement Conditions.
5. All timing referenced to M_CK is for functional testing, for the cases where M_CK × N = IBCLK.
6. PBI Clock is internal only; 66 MHz with 333 MHz internal bus.

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Table 31. PCI Signal Timings

1. See the timing measurement conditions in; Figure 7, “Output Timing Measurement Waveforms” on
2. See Figure 16, “PCI/PCI-X TOV(max) Rising Edge AC Test Load” on page 73, Figure 17, “PCI/PCI-X
3. Setup time for point-to-point signals applies to REQ# and GNT# only. All other signals are bused.
4. See the timing measurement conditions in Figure 8, “Input Timing Measurement Waveforms” on
5. RST# is asserted and deasserted asynchronously with respect to CLK.
6. All output drivers must be floated when RST# is active.
7. For purposes of Active/Float timing measurements, the HI-Z or ‘off’ state is defined to be when the
8. Setup time applies only when the device is not dr iving the pin. Devices cannot drive and receive

4.4.4 I 2C/SMBus Interface Signal Timings

4.4.5 UART Interface Signal Timings

Table 32. I 2C/SMBus Signal Timings

1. See Figure 9, “I2C/SMBus Interface Signal Timings” on page 70.
2. After this period, the first clock pulse is generated.

b = the total capacitance of one bus line, in pF.

1. Std. Mode I 2C signal timings apply for SMBus timing.

Table 33. UART Signal Timings

1. See Figure 10, “UART Transmitter Receiver Timing” on page 70.
2. All timings referenced to M_CK for functional testing, is for cases where M_CK × N = IBCLK.

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4.4.6 PCI Express* Differential Transmitter (Tx) Output Specifications

**Table 34. PCI Express* Tx Output Specifications**

1. ±300 ppm. UI does not account for SSC dictated variations. No test load is necessarily associated

of each bit transmission or width.

1. Peak-Peak differential voltage. VDIFFp-p = 2 × VDMAx. Specified at the package pins into a 100 Ω test

(±0.5 dB) less as measured differentially peak to peak than the specified value.

1. 20–80% at Transmitter. Slower rise/fall times are better.
2. Peak common mode value. | V
3. 50 MHz to 1.6 GHz. The driver output impedance shall re sult in a differential return loss greater than

range of 50 MHz to 1.8 GHz. This output impedance r equirement applies to all valid output levels. for common mode (i.e., as measured by a Vector Network Analyzer with 100 Ω differential probes). 100 Ω . Applicable during active (L0) and Align states only.

1. DC Differential Mode Impedance 100 Ω ±10% tolerance. All devices shall employ on-chip adaptive
2. DC impedance matching between two lanes of a port.
3. Between any two lanes within a single Transmitter.
4. Clock source PPM mismatch is in addition to this value. Measured over 250 UI.
5. See Figure 20, “Transmitter Eye Diagram” on page 75.
6. Between any voltage from max supply to gnd with power on or off.
7. Squelch condition. Both signals brought to V

4.4.7 PCI Express* Differential Receiver (Rx) Input Specifications

**Table 35. PCI Express* Rx Input Specifications**

1. Peak-Peak differential voltage. VDIFFp-p = 2 × VRMAx. Measured at the package pins of the receiver.

See Figure 20, “Transmitter Eye Diagram” on page 75.

1. Max Jitter tolerated by Rx. This is the nominal value tolerated at the package pin of the receiver

device. A receiver must therefore tolerate any additional jitter generated by the package to the die.

1. Peak common mode value. | VD+ + VD-|/2 - VCM-DC(avg).
2. See Figure 21, “Receiver Eye Opening (Differential)” on page 75.
3. 50 MHz to 1.6 GHz. The driver output impedance shall re sult in a differential return loss greater than

range of 50 MHz to 1.8 GHz. This output impedance requirement applies to all valid output levels. for common mode (i.e., as measured by a Vector Network Analyzer with 100 Ω differential probes). 100 Ω . Applicable during active (L0) and Align states only.

1. DC Differential Mode Impedance 100 Ω ±10% tolerance.
2. DC impedance matching between two lanes of a port.
3. Peak to Peak value. Measured at the pin of the receiver. Differential signal below this level will

indicate a squelch condition.

1. All receivers shall be AC coupled to the media.
2. Lane skew at the Receiver that must be tolerated.

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4.4.8 Boundary Scan Test Signal Timings

Table 36. Boundary Scan Test Signal Timings TBSCH TCK High Time 15 ns Measured at 1.5 V ( 1). TBSCL TCK Low Time 15 ns Measured at 1.5 V ( 1). TBSOV1 TDO Valid Delay 5 15 ns Relative to falling edge of TCK (2, 3). TOF1 TDO Float Delay 5 15 ns Relative to falling edge of TCK (2, 5).

1. See Figure 7, “Output Timing Measurement Waveforms” on page 69.
2. See Figure 8, “Input Timing Measurement Waveforms” on page 70.
3. A float condition occurs when the output current becomes less than ILO. Float delay is not tested.

See Figure 7, “Output Timing Measurement Waveforms” on page 69.

4.5 AC Timing Waveforms

Figure 6. Clock Timing Measurement Waveforms Figure 7. Output Timing Measurement Waveforms

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Figure 8. Input Timing Measurement Waveforms Figure 9. I 2C/SMBus Interface Signal Timings Figure 10. UART Transmitter Receiver Timing

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Figure 13. Write PreAmble/PostAmble Durations

4.6 AC Test Conditions

Table 37. AC Measurement Conditions

1. Input signal slew rate is measured between V il and Vih.

Figure 14. AC Test Load for All Signals Except PCI and DDR SDRAM Figure 15. AC Test Load for DDR SDRAM Signals Figure 16. PCI/PCI-X T OV(max) Rising Edge AC Test Load

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Figure 17. PCI/PCI-X T OV(max) Falling Edge AC Test Load Figure 18. PCI/PCI-X T OV(min) AC Test Load Figure 19. Transmitter Test Load (100 Ω differential load)