2913

2913 INTEL | Alldatasheet

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Technical content

2913 AND 2914

integration, the performance of the 2913 and 2914 is superior to that of the separate devices. Figure 1. Pin Configurations

546 Order Number 210829 208

Figure 2. Block Diagram

Table 1. Pin Names Table 2. Pin Description Most negative supply; input voltage is - 5V +5%. loads directly in either a differential or single ended configuration. [ PWRO-_|_ inverting output of power amplifier. Functionally identical and complementary to PWRO +. adjusted over a 12 dB range depending on the voltage at GSp. CLKSEL | Input which must be pinstrapped to reflect the master clock frequency at CLKx, CLKp. +3 dBm0 digital signal output at Dx. state of the eighth bit of the PCM word in the most recent signaling frame. operates at TTL levels from 64 Kb to 2.048 Mb data rates.

Table 2. Pin Description (Continued) enters the standby state whenever FSp is TTL low for 300 milliseconds. [ GROD —_| Digital ground for all internal logic cirouits. Not internally tied to GRDA. independently but in an analogous manner to FSp. data clock which operates at TTL levels from 64 Kb to 2.048 Mb data rates. used as an input pin, ASEL should be strapped to either Voc or GRDD. [ GRDA __| Analog ground return for all internal voice circuits. Not internally connected to GRDD. Non-inverting analog input to uncommitted transmit operational amplifier. inverting analog input to uncommitted transmit operational amplifier. Most positive supply; input voltage is +5V +5%.

e dic I-to-analog conversions an ie transmit . " . termination of a PCM line or trunk. Figure 3. Typical Line Terminations

intel. 2913 and 2914 GENERAL OPERATION Power Down and Standby Modes To minimize power consumption, two power down System Reliability Features modes are provided in which most 2913/2914 func- tions are disabled. Only the power down, clock, and The combochip can be powered up by pulsing FSx —_frame sync buffers, which are required to power up and/or FSR while a TTL high voltage is applied to _the device, are enabled in these modes. As shown in PDN, provided that all clocks and supplies are con- —_—Table 3, the digital outputs on the appropriate chan- nected. The 2913 and 2914 have internal resets on —_nels are placed in a high impedance state until the power up (or when Vag or Voc are re-applied) in device retums to the active mode. order to ensure validity of the digital outputs and thereby maintain integrity of the PCM highway. The Power Down mode utilizes an external control signal to the PDN pin. In this mode, power consump- On the transmit channel, digital outputs Dx and TSx —_tion is reduced to the value shown in Table 3. The are held in a high impedance state for approximately device is active when the signal is high and inactive four frames (500 1s) after power por application of + whenit is low. In the absence of any signal, the PDN Vep or Voc. After this delay, Dx, TSx, and signaling _pin floats to TTL high allowing the device to remain will be functional and will occur in the proper time- active continuously. slot. The analog circuits on the transmit side require ‘approximately 60 milliseconds to reach their equilib- The Standby mode leaves the user an option of rium value due to the autozero circuit settling time. powering either channel down separately or power- Thus, valid digital information, such as for on/off —_ ing the entire device down by selectively removing hook detection, is available almost immediately, FSy and/or FS,. With both channels in the standby while analog information is available after some de- _ state, power consumption is reduced to the value lay. shown in Table 3. If transmit only operation is de- sired, FSx should be applied to the device while FSR On the receive channel, the digital output SIGR is _is held low. Similarly, if receive only operation is de- also held low for a maximum of four frames after sired, FSp should be applied while FSy is held low. power up or application of Vag or Vcc. SIGR will remain low thereafter until it is updated by a signal- ing frame. Fixed Data Rate Mode To further enhance system reliability, TSx and Dx Fixed data rate timing, which is 2910A and 2911A will be placed in a high impedance state approxi compatible, is selected by connecting DCLKR to mately 30 us after an interruption of CLKx. Similarly, Vag. It employs master clocks CLKx and CLKp, SIGp will be held low approximately 30 ps after an _frame synchronization clocks FSx and FSp, and out- interruption of CLKp. These interruptions could pos- _ put TSx. sibly occur with some kind of fault condition. Table 3, Power-Down Methods Typical Powerpown Power Digital Output Status Consumption Power Down PDN = TTLLow | 5mwW TS, and Dx are placed in a high impedance Mode state and SiGp is placed in a TTL low state within 10 ps. Standby Mode | FSxandFSpare | 12mW. TSx and Dx are placed in a high impedance TTL Low state and SiGp is placed in a TTL low state 300 milliseconds after FSy and FS, are removed. Only Transmit is | FSxisTTLLow. | 70mW TS, and Dx are placed in a high impedance on Standby state within 300 milliseconds. Only Receive ls | FSpis TTLLow SIGp is placed in a TTL low state within 300 ‘on Standby milliseconds. 5-51

erate the codec and filter sections and bit clocks to clocks for the receive and transmit PCM highways. clock wide designates a non-signaling frame, while a__ sitions of DCLKp. eight positive transitions of CLK following the rising _and is only available in the variable data rate mode. frequency of CLKx and CLK is selected by the means with which to specify a signaling frame. CLKSEL pin to be either 1.536, 1.544, or 2.048 MHz. the least significant bit of the encoded PCM word. inputs are still restricted to 1.536, 1.544, or 2.048 ships for signaling operation are shown in Figure 4. oun JQLAUALRLALLUTLL PLU LLL. Figure 4. Signaling Timing (Used Only with Fixed Data Rate Mode)

clocks in either the fixed or variable data rate 0 dBm0. operation of the two channels. bochip to provide the voltage reference function. lar manner and is completely independent of the dynamic range characteristics of the device. A distinctive feature of the 2914 is its analog loop- _ margin for error in other board components. LOOP is TTL high the analog output (PWRO +) is . . fies the LSB of the PCM output in signaling frames. Figure 5. Simplified Block Diagram of 2914 Combochip in the Analog Loopback Configuration

The input section provides gain adjustment in the ternal components. op amp can also be used in the inverting mode or next frame. differential amplifier mode (see Figure 6). er lines, 17 Hz European electric railroads, ringing __tTansferred to the receive fitter. D4 specification and CCITT recommendation G.714. {referenced to GRDA) to drive single ended loads. Figure 6. Transmit Filter Gain Adjustment $00 che atiorendais 300 ohms single ended or

Table 4. Zero Transmission Level Points OTLPIx Zero Transmission Level Point +276 dam Referenced to 6002. Transmit Channel (0 dBm0) p-Law +1.00 dam Referenced to 9000. Receive Channel (0 dBm0) p.-Law +4.00 dam Referenced to 9002. OTLP2R Zero Transmission Level Point +5.79 dBm Referenced to 6002. Receive Channel (0 dBm0) A-Law +4.03 dBm Referenced to 9002. and —12 dB as GSp is interpolated (with a potenti the center tap connected to the GSp input. tions, that is, when the digital input at Dp is the eight- the total loading. Figure 7. Gain Setting Configuration IFA = ¥%, (minimum output) then

intel . 2913 and 2914 ABSOLUTE MAXIMUM RATINGS NOTICE: This is a production data sheet. The specifi- ; cations are subject to change without notice, Voc and GRDD These are stress ratings only. Operation beyond the All Input and Output Voltages fended exposure beyond the “Operating Conditions” may attect device reliability. D.C. CHARACTERISTICS Ta = 0°C to 70°C, Voc = +5V 45%, Vag = —5V +5%, GRDA = OV, GRDD = OV, unless otherwise specified Typical values are for Ta = 25°C and nominal power supply values DIGITAL INTERFACE [symboi| Parameter | Min [Typ] Max [Unit] Test Conaitions li, | Low Level input Current [|__| _10 [ pa [GRDD < Vin < Vu) [tmy [High Level Input Curent [| | 0 ea [vs Vins Voo | Input Low Voltage, exceptcuxseL [| | [os |v] InputHigh Vottage, exceptcuxse| 20 | | |v [| Output Low Voltage [| [04 |v [ion = 82 mA at Dy, TSx and SiGR Vou | Output High Voltage V [low = 9.6 mA at Dx lou = 1.2 mA at SIGa Vito | Input Low Voltage, CLKSEL2) Ves Vas | V +05 cmerennsessy [= [9 = 05 -05 [cox [oer GurnCapactancot) | [s| [wr ————~d . 5-56

intel. 2913 and 2914 D.C. CHARACTERISTICS Ta = O°C to 70°C, Voc = +5V +5%, Vag = —5V 5%, GRDA = OV, GRDD = OV, unless otherwise specified Typical values are for Ta = 25°C and nominal power supply values (Continued) POWER DISSIPATION All measurements made at foci = 2.048 MHz, outputs unloaded [‘Symboi [Parameter | min | Typ | Max | unit| TestConditions | [tccr | VocOperatingcurents) || 14 | io [ma [tss1__| VapOperatingGurent || ~ta | -24 | maT | [cco | VocPower Down Current |_| 05 | 1.0 | mA | PON<Vusatter10us | [geo | VapPowerDownCurrent || -05 | -10 | mA | PON<Vuiater10ns | [ccs | VooStandby Curent || 4.2 | 24 | mA | FSyFSq < Vuiattor 300 me | [tees | VepStandby Current |_| -1.2 | ~24 | mA | FSx,FSa < Vusattor 300 ms | [Por | Operating Power Dissipation’ || 40 | 200 [mw] [Poo | PowerDownDissipation” [| 5 | 10 | mW | PON<Vuratter10ns | [Pst | Standby Power Dissipation” [| 12 [ 25 [mW | FSxFSasvu | NOTES: 4. Vin is the voltage on any digital pin. 2. SIGx and DCLKp are TTL level inputs between GROD and Vcc; they are also pin straps for mode selection when tied to Vp. Under these conditions Vio is the input low voltage requirement. 3. Timing parameters are guaranteed based on a 100 pF load capacitance. Up to eight digital outputs may be connected to a common PCM highway without buffering, assuming a board capacitance of 60 pF. 4. With nominal power supply values. 5. Vcc applied last or simultaneously with Vap. ANALOG INTERFACE, TRANSMIT CHANNEL INPUT STAGE [Symbot| Parameter | Min Typ | Max] Unit] TestConditions | [ex | Input Leakage Current, VExi+.VExi- | || 100 | na | ~217V< Vs 217 [Fx | inputReesistance, vFyi+.vex— | to | | [wat [Vosx [inputOtisetVotage, VFxit vex | | ast mv || [MAR | Common Mode Rejection, VFxi+.VFx— | 58 | [| dB | -2.17V Vi < 217v | [Avor_ | OCOpenLoopVotageGain,asx [sooo] | | | [fc | Opentoop Unity Gain Bandwiath. sx | | + | [wuz] | [Cn _[LoadCapactance,csx | S| | So oF | [Fun | MinimumLoadResistanceasx | 10 | | [kat ANALOG INTERFACE, RECEIVE CHANNEL DRIVER AMPLIFIER STAGE [Symbol] __—Parameter_—=—| Min | Typ | Max | Unit | Test Conditions | [Rona | OutputResistance,PwAO+,PwRO- | | a [| @ | | ee fEemenmom Pe ml ea PWRO-— [Guan | toadCapacitance, pwRo+.PwRo- | | | too | oe [| 5-57

intel. 2913 and 2914 A.C. CHARACTERISTICS—TRANSMISSION PARAMETERS Unless otherwise noted, the analog input is a 0 dBm0, 1020 Hz sine wave.(1) input amplifier is set for unity gain, noninverting. The digital input is a PCM bit stream generated by passing a 0 dBm0, 1020 Hz sine wave through an ideal encoder. Receive output is measured single ended, maximum gain configuration.(2) All output levels are (sin x)/x corrected. Specifications are for synchronous operation. Typical values are for Tq = 25°C and nominal power supply values. (Ta = 0°C to + 70°C; Voc = +5V +5%; Vea = —5V +5%; GRDA = OV; GRDD = OV; unless otherwise specified). GAIN AND DYNAMIC RANGE [Symbol] Parameter [in | Typ | Max | unit | Test Conditions Encoder Milliwatt Response] —0.18] +0.04| +0.18| d8m0| Signal input of 1.064 Vrms -law Tolerance Signal input of 1.068 Vrms A-law Ta = 25°C, Veg = —5V, Voc = +5V EmWrs | EmW Variation with ~0.07| +0.02| +0.07 +5% supplies, 0 to 70°C ‘Temperature and Supplies Relative to nominal conditions Digital Milliwatt Response £0.04] +0.18| dBm0| Measure relative to OTLPR. Signal Tolerance input per CCITT Recommendation G.711. Output signal of 1000 Hz, Ru = 2; Ta = 25°C; Vas = —5V, Voc = +5V. DmWrs | DmW Variation with -0.07| +0.02| +0.07 +£5% supplies, 0 to 70°C Temperature and Supplies NOTES: 1. 0 dBm0 is defined as the zero reference point of the channel under test (OTLP). This corresponds to an analog signal input of 1.064 Vrms or an output of 1.503 Vrms for p-law. See Table 4. 2. Unity gain input amplifier: GSx is connected to VFxI~, Signal input VFxI+; Maximum gain output amplifier; GSq is connected to PWRO—, output to PWRO+ GAIN TRACKING Reference Level = —10dBm0 GT1x__| Transmit Gain Tracking Error £02 +0.25| dB | +3to —40 dBm Sinusoidal Input; p-Law +03 +05 | dB | -40to ~50dBm0 £0.65 +12 | dB | -50to ~55d8m0 GT2x__| Transmit Gain Tracking Error £02 +0.25| dB | +3to —40dBmo ‘Sinusoidal Input; A-Law +03 +05 | dB | -40to ~50d8m0 +065 +1.2 | dB | -50to ~55dB8m0 GTip__ | Receive Gain Tracking Error £0.2 £0.25| dB | +3to ~40d8m0 Sinusoidal Input; p-Law +03 +05 | dB | -40to —50d8m0 £0.65 +12 | dB | -50to -55d8m0 Measured at PWRO+, Ry = 3002 GT2p__| Receive Gain Tracking Error +02 £0.25} dB | +3to —40 dBm0 Sinusoidal Input; A-Law +03 +05 | dB | —40to -50dBm0 £0.65 +12 | dB | ~-50to —55 d8m0 Measured at PWRO+, A = 3000. 5-58

intel. 2913 and 2014 A.C. CHARACTERISTICS—TRANSMISSION PARAMETERS (Continued) NOISE All receive channel measurements are single ended Prmto| raeme| am [Ty [int | testcenatom | | min | Typ | max [min] Typ [Max INxc1 {Transmit Noise, C-Message 13 dBmcO|VFxl+ = GRDA, VFxl— = Weighted GS INxc2 [Transmit Noise, C-Message dBrncO|VFyxI+ = GRDA, VFxI— = Weighted with GS; 6th Frame Signaling Eighth Bit Signaling INxP Transmit Noise, 7 —75|dBm0p|VFyxl+ = GRDA, VFxl— = iPsophometrically Weighted GS INRc1 |Receive Noise, C-Message \\dBrnco} Weighted: Quiet Code (Receive Noise, C-Message dBrncO|Input to Dp is zero code with] Weighted: Sign Bit Toggle sign bit toggle at 1 KHz rate Receive Noise, —79|dBm0p|Dr = lowest positive Psophometrically Weighted decode level Single Frequency Noise dBm0 |CCITT G.712.4.2, End to End Measurement measure at PWRO + Vcc Power Supply Rejection, Idle channel; 200 mV P-P |Transmit Channel ‘signal on supply; 10 to 50 KHz, measure at Dx Vag Power Supply Rejection, | Idle channel; 200 mV P-P [Transmit Channel ‘signal on supply; 5 10 to 50 KHz, measure at Dx Voc Power Supply Rejection, Idle channel; 200 mv P-P Receive Channel /signal on supply; measure Inarrow band at PWRO+ , 10 to 50 KHz IPSRR« |Vag Power Supply Rejection, Idle channel; 200 mv P-P Receive Channel [signal on supply; measure narrow band at PWRO +, 10 to 50 KHz Tra |Crosstalk, Transmit -71 VExI+ = OdBmo, ito Receive 1.02 KHz, Da = lowest positive decode level, measure at PWRO + Trt |Crosstalk, Receive “71 IDR = 0 dBm0, 1.02 KHz to Transmit \\VFxl+ = GRDA, measure at Dy 5-59

intel. 2913 and 2914 A.C. CHARACTERISTICS—TRANSMISSION PARAMETERS (Continued) DISTORTION [Symbol] _Parameter [Min] Typ] Max] Unit | Test Conditions $D1x | Transmit Signal to Distortion, p-Law dB 0 to —30 dBmo ‘Sinusoidal Input; dB | -—30 to —40dBm0 CCITT G.714-Method 2 dB | —40 to 45 dBm0 $D2x | Transmit Signal to Distortion, A-Law dB Oto -30 dBmo ‘Sinusoidal Input; dB | -30 to ~40 dBm0 CCITT G.714-Method 2 dB | —40 to —45 dBm0 Receive Signal to Distortion, »-Law dB 0 to —30 dBm0 ‘Sinusoidal Input; dB | —30 to —40 dBm0 CCITT G.714-Method 2 dB | —40 to —45dBm0 Receive Signal to Distortion, A-Law dB 0 to —30 dBm0 Sinusoidal Input; dB | -30 to —40 dBmo CCITT G.714-Method 2 dB | —40 to —45 dBm0 Transmit Single Frequency Distortion dBm0| AT&T Advisory #64 (3.8) Products. 0 dBmo0 Input Signal Receive Single Frequency Distortion dBm0| AT&T Advisory #64 (3.8) Products 0 dBmo Input Signal intermodulation Distortion, CCITT G.712 (7.1) End to End Measurement Intermodulation Distortion, dBm0| CCITT G.712 (7.2) End to End Measurement Spurious Out of Band Signals, dBm0| CCITT G.712 (6.1) End to End Measurement ‘Spurious in Band Signals, dBm0| CCITT G.712 (9) End to End Measurement Dax Transmit Absolute Delay #S | Fixed Data Rate. CLKx = 2.048 MHz! 0 dBm0, 1.02 KHz signal at VFy!-+ Measure at Dx. Transmit Differential Envelope Delay 170 bs |f = 500 — 600 Hz Relative to Dax 95 ps |f = 600 ~ 1000Hz 45 ps |f = 1000 - 2600 Hz

105 HS _|f = 2600 — 2800 Hz

Receive Absolute Delay 190 BS | Fixed Data Rate, CLK = 2.048 MHz; Digital input is DMW codes. Measure at PWRO+. Receive Differential Envelope Delay 45 ps |f = 500 — 600 Hz Relative to Dan 35 ps |f = 600 — 1000Hz 85 us |f = 1000 — 2600 Hz 110 us_|f = 2600 — 2800 Hz 5-60

Input amplifier is set for unity gain; noninverting; maximum gain output.

16.67 Hz | | [= fof

9900 He | -os5[ | +oosfeef

9400 He | -o7 | |-owfeef

4600 He and Above ee es

104 Ana

Figure 8. Transmit Channel

intel. 2913 and 2914 A.C. CHARACTERISTICS—TRANSMISSION PARAMETERS (Continued) RECEIVE CHANNEL TRANSFER CHARACTERISTICS [Symboi[ Parameter [| Min_[Typ| Max [Unit] TestConditions [Gar | GainRelativetoGainat1.02KHz| |__| _——=—=—«|_| 0 dBm0 Signal input atDp Below 200 Hz | | tors| asf [aoowe | 05 || totes] ap | 300 to 3000 Hz [-oras[ [rors] as | [ssoone os || toon pf [swoon | or | [or fof [aooone TT te Pow PO

4600 Hz and Above a ee

1.048 so1240 +0.12508 4012848 -00300 Saone” “Saane Sooona/ssaone como | cay gn 0.5048 sme 0.12548 -1040 Saoie ow ‘ 1048 4 ~t4s8 ~200 ~s008 ~s040 je ntoan 20a | -ow ‘ome 100K ‘ote tome 210628-12 Figure 9, Receive Channel 5-62

intel. 2913 and 2914 A.C. CHARACTERISTICS—TIMING PARAMETERS CLOCK SECTION ['Symboi [Parameter [min | typ | Max | unit | TestConaitions | [toy | Clock Period, CL. ike | 408 || [ns | toux = founn = 2.048 Mi | [toxx | Clock Pulse Width, CLkx. CuK | 220 [fons [| | tocux | DataciockPuise wictn | 220 ||| ns | 64 KHz < focix < 2.048 Miz | [toc | Clock Duty oyete, Cu cika | 45 | 50 [ss fe [| Lut [otockrisoandraitime | s | [ao fm | TRANSMIT SECTION, FIXED DATA RATE MODE(1) [_symbor [Parameter [min | typ | Max | Unit | TestConditions | | tozx | Dataénabledonts entry | o [| 14s [ns [0 < Coan < 100pF_| [ toox | Datadelayiromoukx | 0 [| 145 [ns | 0<Clonp < 100 pF | [tex | Datartoatontsext [60 [| 21s | ns | Ciom=0 | | tson | Timesiotxtoenabie [0 || 145 | ns | 0< Coan < 100pF_| | tsore | TimesiotxtoDisabio | 60 | | 215 [ns | Ciom=0 | | ts0 | Framesynedelay | 100 || tox [ons | [ss | Sina'sewptime | o [| fons [| [ts | SignaiHowtine To [| ns PO RECEIVE SECTION, FIXED DATA RATE MODE 5 | [_svmbot | Parameter [| min | Typ | Max | Unit | TestConcltions | | osm | Revenvedatasewp | io [| [ons [| | town | Receivedatatod | co | [| ons [| | ‘eso | Frame Sync Dela | too | | tax | me | | L_tsicn | signurdte Jo TT 2 fos TO Ong Parameters tpzx, tHzx. and tsorr are referenced to a high impedance state. 5-63

intel. 2913 and 2914 WAVEFORMS Fixed Data Rate Timing TRANSMIT TIMING ‘er rwwestor ene 7 3 7 7 7 7 7 . ne we . . rs WOM SINALING cot ve rx nana —rmesior an 7 7 > 7 . : 7 : 5 ore ‘oon tax or Kors XK wre wre Xr Xr Xt Xore > om —] | torr ts aah ten

05 DONT cane af Soir

NOTE: All timing parameters referenced to Vjj4 and V\\, except tpzx, tsorF and tyzx which reference a high impedance state. RECEIVE TIMING te eestor ae no e “ “ Fa now sinaine enanes Fo sionauna vaaanes tet cus Fy 7 2 7 . . 7 . : town ‘won om TK UK XR LK Ko" LK XK MK XD ny [| in — wae Cra 210620-14 NOTE: Al timing parameters referenced to Viy and Vi. 5-64

intel ° 2913 and 2914 WAVEFORMS (Continued) TRANSMIT SECTION, VARIABLE DATA RATE MODE(1) [_symbor | ___ Parameter | min | typ | Max | unit | TestConaitions _ | [sox | TimesiotDaay tom CO | wo | [i= | me | | [eso | Frame syneDoay | 100} | 100 | m= | ——*d [toox | oatabetaytomcikx | 0 | | 100 | ns | 0< Coun <100pF | { toon | Timesiottodxactve [| o | [50 | ns | 0 < Chonan < 1000 | [toorr | TimesotoOxinscive | 0 | | 00 | mm | 0<Cuogo< 1000" | [tox | oawGeckreios wee | | 15600 [m= [| [rsx | atdonytomrsx | 0 | | 0 [m=] ——*s RECEIVE SECTION, VARIABLE DATA RATE MODE [ symbor | ___ Parameter | min | typ | max | unit | Test Conaitions | [som | Tinestt Delay rom bcukN@ [140] [te | me | [eso | Frmesyne uy [100 | | tey= 100 | me | ——d [esa | OataSeuptine [0 | ||» | Ss | town | Datarowtime | go | | os PO [ton | ata Goex Paros | «es | | 1600 | ne |_| Lisen | TimestotendRecevetime | 60 | [| | ns [

64 KB OPERATION, VARIABLE DATA RATE MODE

[symoot| Parameter | win [ Typ | Wax unt | Tost Conditions Sel Ral Downtime frame Ss = l= Downtime frame [tock [Dataciockrusewiatn | | To fs | NOTES: 1. Timing parameters for toon and tooFr are referenced to a high impedance state. 2 tesix minimum requirements override trsox maximum spec for 64 KHz operation. * 3. tesLR minimum requirements override trsoR maximum spec for 64 KHz operation. 5-65

intel. 2913 and 2014 VARIABLE DATA RATE TIMING TRANSMIT TIMING Fx i bei, cis toon = [+ | |—toox | | toon SIT te m= ——{ ons Xors X ons Kove X ons X one X on YX one ) zr0820-18 RECEIVE TIMING rs, —L bets rae ne eae ae} | te cake 210828-18 NOTE: All timing parameters referenced to Vin and Vi except tpon and torr which reference a high impedance state. AC. TESTING INPUT, OUTPUT WAVEFORM i 20 20 os a a ay0626—17 ‘Ac Testing nts ae dvn at 24 ora Loge anda 450 (Getage': tour rtaturnrs ae made 120 ora Loge Row wre tape 8 5-66