2912A | DigiCamel IC Datasheet

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2912A INTEL | Alldatasheet

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Technical content

The primary application for the 2912A is in telephone systems for transmission, switching, or remote

gy results in a monolithic 2912A filter which is packaged in a standard 16-pin DIP. Figure 1. Block Diagram

Table 1. Pin Description before being sent to the Codec for encoding. transmit filter. Used for gain setting of the transmit fiter. is provided on pins PWRO+ and PWRO—. tied to Vag, the power amplifiers are powered down. capable of directly driving transformer hybrids. capable of directly driving transformer hybrids. compatible with the tel 2910A and Zora. Codecs. GRoD | 11 | Ground _| _ Digital ground return for internal clock generator. accordingly. High impedance input, TTL voltage levels. 2911A PDN outputs. TTL voltage levels. 1.544 MHz. If tied to Voc, CLK should be 2.048 MHz. circuits. Not connected to GRDD internally. is directly compatible with the Intel 2910A and 2911A Codecs.

The three clock frequencies are directly compatible with the Intel 2910A and 2911A Codecs. The following table should

be observed in selecting the clock frequency.

receive and transmit directions. function needed for an 8 KHz sampling system, and 2911A Codecs. Figure 3. Typical Line Termination be greater than 10K 9 in parallel with 25 pF. The .

intel. 29128 Receive Filter Output load resistance of 6002 to the amplifier in the tp bridged configuration. A typical connection of the The VFRO lead is capable of driving high impedance output driver amplifiers is shown in Figure 6. These electronic hybrids. The gain of the receive section amplifiers can also be used with loads connected to from VF pl to VFRO is: ground, cat When the power amplifier is not needed it should be 5000 deactivated to save power. This is accomplished by on (<2) tying the PWAI pin to Vgg before the device is pow- n( ered up. which when multiplied by the output response of the Intel 2910A and 2911A Codecs results in a0 dB gain / Power Down Mode in the pass band. The filter gain can be adjusted —_p, downward by a resistor voltage divider connected as hen ine endl on is ‘rand fe browghe igh the shown in Figure 5. The total resistive load Ri on ; H VFRO should not be less than 10K 0. 2012A goes into a standby, power down mode. Pow- Ri . er dissipation is reduced to 0.5 mW. in the stand-by mode, all outputs go into a high impedance state. This feature allows multiple 2912As to drive the ry same analog bus on a time-shared basis. vo | When power is restored, the settling time of the mn em oR 29122 is typically 15 ms. “ The PDN interface is directly compatible with the In- tel 2910A and 2911A PDN outputs. Only one com- mand from the common control is then necessary to . power down both the Codec and the Filters of the reo " line or trunk interface. a weno an = Figure 5, Receive Filter Output Gain Adjustment a Receive Filter Output Driver Amplifier Stage "= ‘A balanced power amplifier is provided in order to 7 | “4 drive low-impedance loads in a bridged configura. | = ————4 ran. <I tion. The receive filter output VFRO is connected L through gain setting resistors Ry and Re to the am- plifier input PWAI. The input voltage range on PWRI is +3.2 volts and the gain is 6 dB for a bridged out- ____! | ty put. With a 6002 load connected between PWRO+ and = PWRO-, the maximum voltage swing across the 270159-6 load is + 5.0 volts. The series combination of Rg and the hybrid transformer must present a minimum A.C. Figure 6. Typical Connection of Output Driver Amplifier 5-37

intel. 2912A ABSOLUTE MAXIMUM RATINGS* cations are subject to change without notice. Supply Voltage with Respect These are stress ratings only. Operation beyond the tOVBB +s eereeeeeeeeeeeess O.BV IO +14.0V ee eee nd the “Chante contions” Neopet OEE en -oavio +140y —Y Act dowco roi D.C. CHARACTERISTICS T, = 0°C to + 70°C; Voc = 5V +5%; Vag = —5V +5%; GRDA = OV; GRDD = OV; unless otherwise specified DIGITAL INTERFACE (CLK, CLKO, and PDN Pins) [Symbot[ Parameter [Min [ Tyet) | Max [unit] TestConaitions | [ttuc [tnputtoadcunentcuk | || t0_ | wa | Viv = GRD t0 Vor | [tuo [inputuoad Curent. cixo | || 10 | nA | Vin = Ves toVoo _| [up [inputuoadcurent pon || =100 | A | Vin = GRDD to Voc | [Vu | inputuowvottage (exceptcrk | || os | v | [Vw | inputtigh Vottageexceptcixoy| 20 [| | v | [Vuo | inputtowvowtage,cuko | Vea | [Vents] v | [Vio | inputintermediate Voltage, cLxo[@RpD-0s| | oa | v | [Vino [inputtighvortage,ctxo | voc“°S [| voc [vy] POWER DISSIPATION [“sympor_ [Parameter [min | typtt) | max | unit | Test Conditions | | tcco | VecStanaby Curent [| 50100 | wa | PON= Vin Min _| | taco | VapStanabyCurent [| 50 | 100 | wa | PON=VinMin | a DB al Amplifiers Inactive [| imeem |S fm | meee Amplifiers Inactive | tcce | VocOperatingcurent | | 8 | te | ma | [tae | VapOperatingGurent | | os | te | m | NOTES: 1. Typical values are for Ta = 25°C and nominal power supply values. 2. To place the power amplifiers in the inactive mode PWR! must be tied to Veg prior to power-up. 5-38

intel. 29128 D.C. CHARACTERISTICS T, = 0°C to +70°C; Voc = 5V +5%; Vag = —5V +5%; GRDA = OV; GRDD = OV; unless otherwise specified (Continued) ANALOG INTERFACE, TRANSMIT FILTER INPUT STAGE Bymbol_ Parameter [Min Typt‘maxunit| TeatConaitions | Jax [input Leakage Curent, veyi+vexi- | | [roo] nal-2av<Viw<22v | Fii__|inputResistance, vexi+vexi— | ao || [maf Mosx [input OrfsetVottage, VFxi+.vFxi— || [as {mv[ al el bd lO dBm0 = 1.1 Vaqs, Input at VFx!— JAvor_|OCOpen Loop voltage Gain, Gsx sooo] [| | fo [Open Loop unityGainBanawitn asx | [1 [| Moxi_ouputvotage Swing Gsx [zz] | [Vue toKn Fun floadcapacitance,asx || fastor[ Fux [Minimum LoadResistance,GSx | 10 || [ke ainimuma | ANALOG INTERFACE, TRANSMIT FILTER (See Figure 9) [Symbot| Parameter min [ Tye) [Max [unit] TeatConaitions | [Rox | OutputResistancevexo || 20 [asta ft foe faeesomery [| anna Input Op Amp at Unity Gain il =i al al

1 KHz, VFxO

i =i a [cix | toadCapacitance, vFxo | | | as | oe | [Rix | Minimum LoadResistance, FXO | 27 | | | ka | Minimum, [row _[omnroneowetiewe|ss2[ | |v [anatnormmae | or [Voxe [output vonage swing 1kHzvexo[ +25] [| v [rza7ka NOTES: 1. Typical values for Ta = 25°C and nominal power supply values. 2. PSRR;,2 include op amp in transmit section. 5-39

intel. 2912A D.C. CHARACTERISTICS T, = 0°C to + 70°C; Voc = 5V +5%; Vag = —5V +5%; GRDA = OV; GRODD = OV; unless otherwise specified (Continued) ANALOG INTERFACE, RECEIVE FILTER (See Figure 10) [Symbot[ Parameter [min | Typ(?)[ Max | unit | Test Conditions [tan | inputteakagecurent vent | | [3 | wa | -3.2v < Vm <a.2v | Fin | Input Resistance, VFal a [Ron | OupstResiance,vego |} [we | a} _] Output DC Ottset VERO [| |__| 100 | mv | VF! Connected to GRDA Power Supply Rejaction of Vcc at

1 KHz, VFRO

intel. 2912A A.C. CHARACTERISTICS T, = 0°C to +70°C; Voc = 5V +5%; Vag = —5V +5%; GRDA = OV; GRDD = OV; unless otherwise specified Glock Input Frequency: CLK = 1.536 MHz +0.1%; CLKO = Vizo (Tied to Vee) CLK = 2.048 MHz +0.1%; CLKO = Vizio (Tied to Veo) CLK = 1.544 MHz 0.1%; CLKO = Vii (Tied to GRDD) TRANSMIT FILTER TRANSFER CHARACTERISTICS (See Transmit Filter Transmit Characteristics, Figure 7) Symbol Parameter | in [typtt]| Max | unit | Test Conditions (Gain Relative to Gain at 1 KHz | {|__| d8mo input Signal

16.67 Hz |_| =s6] =50 | 48 [Gain setting op Amp

4600 Hz and Above [| | -se] ee |

pax | bsolute Passband Gain at 1 KHz, 34 RL = =® ‘axt [Gain Variation with Temperature at lo.0004 B/°C Jo dBimo Signal Level 5 1h KHz jax [Gain Variation with Supplies at 1 KHz 0.07 | dB/V [0 dBmo Signal Level, supplies + 5% ‘Rt {Cross Talk, Receive to Transmit, -75 Frl = 1.6 Vams, 1 KHz Measured at VFxO input, VFxl-+, VEx!— VExO onnected to GSy, GSx 20 log FEO onnected through 10 K2. to| RDA icx: [Total C Message Noise at Output, VFxO <dBrc0 |Gain Setting Op Amp at (Note 2)|Unity Gain icx2 _ [Total C Message Noise at Output, VFxO dBirnco |Gain Setting Op Amp at {Note 220 dB Gain Pox _ [Differential Envelope Delay, VFxO Hs 1 KHz to 2.6 KHz Pax _[Absoiste Delay attkrzvFxo || to | os | Px; [Single Frequency Distortion Products | |__| —48 | dB 0 dBm0 Input Signal at 1 KHa DPx2 [Single Frequency Distortion Products at =45 0.16 Vamg 1 KHz Input IMaximum Signal Level of +3 dBm0 at ISignal at VFxl+; Gain FXO [Setting Op Amp at 20 dB ain. The +3 dBm0 Signal at VFxO is 2.26 Vas 5-41

intel. 29124 A.C. CHARACTERISTICS T, = 0°C to + 70°C; Voc = 5V +5%; Vag = —5V +5%; GRDA = OV; GRDD = OV; unless otherwise specified (Continued) Clock Input Frequency: CLK = 1.836 MHz +0.1%; CLKO = Vito (Tied to Vag) CLK = 1.544 MHz £0.1%; CLKO = Vijo (Tied to GRDD) CLK = 2,048 MHz 0.1%; CLKO = Vino (Tied to Voc) RECEIVE FILTER TRANSFER CHARACTERISTICS (Seo Receive Filter Transfer Characteristics, Figure 8) Symbol Parameter [Min |Typt™)|Max] Unit | Test Conditions IGain Relative to Gain at 1 KHz with 0 dBmo Input Signal ISinx/x Correction of 2910A or 2911A | Below 200Hz || fot] 8 |o.demo Signal = 1.6 Vans * a [zor 08 | font a8 | sn (=) {sooreiwsoone —___|-oad) oad oe | ao [ssoorne} eas] Joan] ae Jronaivens (5) | saoonz or] fo] a

4600 Hz and Above || [a0] ae

(Gan __[Absolute PassbandGain at KHz, VFR] —0.1 | 0 [+o] a8 [= 904 | Pa een Variation with Temperature at | __fronedecog dB/°C [0 dBmo Signal Level } KHz [Gain Variation with Supplies at 1 KHz 0.07] dB/V |0.dBm0 Signal Level, [Supplies +5% Trp |Cross Talk, Transmit to Receive, -70 VFx! = 1.4 Vams, 1 KHz \\Measured at VF RO; |Output, VF RI Connected to 20 log (VFRO/VF xO) IGRDA HTotal C Message Noise at Output, VFaO <dBmc0|VFRO Output or PWRO+ and (Note 2) IPWRO — Connected with Unity Gain D Ditferential Envelope Delay, VFRO, ns 1 KHz to 2.6 KHz Pan _ [Absolute Dolay at t KHz, VERO a | Pa: [Single Frequency Distortion Products | | _—_—(|—48| dB [0 dBm0 Input Signal at 1 KHz D ingle Frequency Distortion Products at +3 dBmO Signal Level of [Maximum Signal Level of +3 dBm0 at 12.26 Vaws. 1 KHz Input at FRO VR! NOTES: 1. Typical Values are for Ta = 25°C and nominal power supply values. 2. A noise measurement of 12 dBrnc into a 6002 load at the 2912A device is equivalent to 6 dBrnc0. 3. For gain under load refer to output resistance specs and perform gain calculation. 4, Output is non-inverting. 5-42

Figure 7. Transmit Filter

Figure 8. Receive Filter

Typical Transter Function of the Receive Filter as a Separate Component.
Typical Transfer Function of the Receive Filter Driven by the Sample and Hold Output of the Intel 2910A and 2911A

CODECS. The Combined Filter/CODEC Response Meets the Stated Specifications.

Product Information

2912A specifications and overview.

Summary

PCM TRANSMIT/RECEIVE FILTER

Description

PCM TRANSMIT/RECEIVE FILTER

Source title 2912A Datasheet(PDF) - Intel Corporation

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