28F512 INTEL | Alldatasheet
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intel. 28F512 512K (64K x 8) CMOS FLASH MEMORY @ Flash Electrical Chip-Erase tm Command Register Architecture for — 1 Second Typical Chip-Erase Microprocessor/Microcontroller lm Quick-Pulse Programming Algorithm Compatible Write Interface — 10 ys Typical Byte-Program @ Noise Immunity Features — 1 Second Chip-Program — +10% Vcc Tolerance — Maximum Latch-Up Immunity 100,000 Erase/Progr: . 42.0V 45% V rogram Cycles through EP! Processing m 120V = PP = ETOX I Nonvolatile Flash Technology @ High-Performance Read —EPROM-Compatible Process Base — 120 ns Maximum Access Time —High-Volume Manufacturing @ CMOS Low Power Consumption Experience — 10 mA Typical Active Current = JEDEC-Standard Pinouts — 50 2A Typical Standby Current —32-Pin Plastic Dip — OW Data Retention Power —32-Lead PLCC @ Integrated Program/Erase Stop Timers (Boe Packering Spec, Onder #251300) m Extended Temperature Options Intel's 28F512 CMOS flash memory offers the most cost-effective and reliable alternative for read/write random access nonvolatile memory. The 28F512 adds electrical chip-erasure and reprogramming to familiar EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; on- board during subassembly test; in-system during final test; and in-system after-sale. The 28F512 increases memory flexibility, while contributing to time- and cost-savings. The 28F512 is a 512-kilobit nonvolatile memory organized as 65,536 bytes of 8 bits. Intel's 28F512 is offered in 32-pin plastic dip or 32-lead PLCC packages. Pin assignments conform to JEDEC standards for byte-wide EPROMs. Extended erase and program cycling capability is designed into Intel's ETOX II (EPROM Tunnel Oxide) pro- cess technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field com- bine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0V Vp supply, the 28F512 performs 100,000 erase and program cycles well within the time limits of the Quick-Pulse Programming and Quick-Erase algorithms. Intel's 28F512 employs advanced CMOS circuitry for systems requiring high-performance access speeds, low power consumption, and immunity to noise. Its 120 nanosecond access time provides no-WAIT-state perform- ance for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 wA trans- lates into power savings when the device is deselected. Finally, the highest degree of latch-up protection is achieved through Intel’s unique EP! processing. Prevention of latch-up is provided for stresses up to 100 mA on address and data pins, from —1V to Veg + 1V. With Intel's ETOX II process base, the 28F512 levers years of EPROM experience to yield the highest levels of quality, reliability, and cost-effectiveness. November 1904 |
660 M@™@ 4826175 O1bb108 Ob4 mm Order Number: 290204-008
Figure 1. 28F512 Block Diagram
0 Cs 20 F100, 0 O13 21100,
Figure 2. 28F512 Pin Configurations Table 1. Pin Description latched during a write cycle. are disabled. Data is internally latched during a write cycle. during a read cycle. OE # is active low. INPUT WRITE ENABLE: Controls writes to the control register and the array. and data is latched on the rising edge of the WE # pulse. Note: With Vpp < 6.5V, memory contents cannot be altered. register, erasing the entire array, or programming bytes in the array.
intel ° 28F512 APPLICATIONS circuit alterability; this eliminates unnecessary han- dling and less-reliable socketed connections, while The 28F512 flash memory provides nonvoiatility adding greater test, manufacture, and update flexi- along with the capability to perform over 100,000 bility. electrical chip-erasure/reprogram cycles. These fea- tures make the 28F512 an innovative altemative to Material and labor costs associated with code disk, EEPROM, and battery-backed static RAM. changes increases at higher levels of system inte- Where periodic updates of code and data-tables are gration — the most costly being code updates after required, the 28F512's reprogrammability and non- sale. Code “bugs”, or the desire to augment system volatility make it the obvious and ideal replacement functionality, prompt after-sale code updates. Field for EPROM. revisions to EPROM-based code requires the re- moval of EPROM components or entire boards. With Primary applications and operating systems stored _the 28F512, code updates are implemented locally in flash eliminate the slow disk-to-DRAM download via an edge-connector, or remotely over a commun- process. This results in dramatic enhancement of _cation link. Performance and substantial reduction of power consumption — a consideration particularly impor- For systems currently using a high-density static tant in portable equipment. Flash memory increases © RAM/battery configuration for data accumulation, flexibility with electrical chip erasure and in-system flash memory's inherent nonvolatility eliminates the update capability of operating systems and applica- need for battery backup. The concern for battery tion code. With updatable BIOS, system manufactur- _ failure no longer exists, an important consideration ers can easily accommodate last-minute changes as for portable equipment and medical instruments, revisions are made. both requiring continuous performance. In addition, flash memory offers a considerable cost advantage In diskless workstations and terminals, network traf- over static RAM. fic reduces to a minimum and systems are instant- ‘on. Reliability exceeds that of electromechanical © Flash memory's electrical chip erasure, byte pro- media. Often in these environments, power interrup- _ grammability and complete nonvolatility fit well with tions force extended re-boot periods for all net- data accumulation and recording needs. Electrical worked terminals. This mishap is no longer an issue chip-erasure gives the designer a “blank slate” in if boot code, operating systems, communication pro- which to log or record data. Data can be periodically tocols and primary applications are flash-resident in _off-loaded for analysis and the flash memory erased each terminal. Producing a new “blank slate”. For embedded systems that rely on dynamic RAM/ A high degree of on-chip feature integration simpli- disk for main system memory or nonvolatile backup _fies- memory-to-processor interfacing. Figure 3 de- storage, the 28F512 flash memory offers a solid picts two 28F512s tied to the 80C186 system bus. ‘state alternative in a minimal form factor. The The 28F512’s architecture minimizes interface cir- 28F512 provides higher performance, lower power culty needed for complete in-circuit updates of Consumption, instant-on capability, and allows an memory contents. “execute in place” memory hierarchy for code and data table reading. Additionally, the flash memory is With cost-effective in-system reprogramming, ex- more rugged and reliable in harsh environments tended cycling capability, and true nonvolatility, where extreme temperatures and shock can cause the 28F512 offers advantages to the alternatives: disk-based systems to fail. EPROMs, EEPROMs, battery backed static RAM, or disk. EPROM-compatible read specifications, The need for code updates pervades all phases of a straight-forward interfacing, and in-circuit alterability system's life — from prototyping to system manufac- _offers designers unlimited flexibility to meet the high ture to after-sale service. The electrical chip-erasure standards of today's designs. and reprogramming ability of the 28F512 allows in- | @™@ 4426175 O1bb111 655 a 6-63
Figure 3. 28F512 In a 80C 186 System Flash-memory augments EPROM functionality with put data for erase and program verification. for: 100% TTL-level control inputs; fixed power sup- . . plied to the Vpp pin. In addition, high voltage on Vpp _—receiving the appropriate verify or reset command. needed for programming or erase operations. With ™ode, the memory contents cannot be altered.
Table 2. 28F512 Bus Operations
- Refer to DC Characteristics. When Vpp = Vpp_ memory contents can be read but not written or erased.
- Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
- Vip Is the Intelligent identifier high voltage. Refer to DC Characteristics.
- Read operations with Vep = Vppy may access array data or the Intelligent Identifier codes.
- With Vpp at high voltage, the standby current equals Icc + Ipp (standby).
- Refer to Table 3 for valid Data-In during a write operation.
lockout voltage Vio. (See Power Up/Down Protec- _in a high-impedance state. state, independent of the Output-Enable signal. operation can only access the array data.
evel, raising A9 to high voltage Vip (see DC Charac- _—_data information needed to execute the command. the 28F512 is erased and reprogrammed in the tar- essor write timings are used. address 0001H outputs the device code (B8H). parameters. plied to the Vpp pin. The contents of the register _abling read-only operations. dressable memory location. The register is a latch commands. Table 3. Command Definitions
- Bus operations are defined in Table 2.
- IA = Identifier address: OOH for manufacturer code, 01H for device code.
EA = Address of memory location to be read during erase verity. PA = Address of memory location to be programmed. Addresses are latched on the falling edge of the Write-Enable pulse.
- ID = Data read from location 1A during device identification (Mfr = 89H, Device = BSH).
EVD = Data read from location EA during erase verity. PD = Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable. PVD = Data read from location PA during program verity. PA is latched on the Program command.
- Following the Read Intelligent ID command, two read operations access manufacturer and device codes.
- Figure 5 illustrates the Quick-Erase algorithm.
- Figure 4 illustrates the Quick-Pulse Programming algorithm.
- The second bus cycle must be followed by the desired command register write.
Read Command of this high voltage, memory contents are protected against erasure. Refer to AC Erase Characteristics While Vpp is high, for erasure and programming, and Waveforms for specific timing parameters. memory contents can be accessed via the read command. The read operation is initiated by writin, 00H into the command register. Macroprocaseee Erase-Verity Command read cycles retrieve array data. The device remains The erase command erases all bytes of the array in enabled for reads until the command register con- parallel, After each erase operation, all bytes must 7 be verified. The erase verify operation is initiated by The default contents of the register upon Vpp pow- NNN. ye bbe voted want te euoried aa ke er-up is OOH. This default value ensures that no Spu- latched on the falling edge of the Write-Enable rious alteration of memory contents occurs during Ise. The register write terminates the erase opera- the Vpp power transition. Where the Vpp SUppIY iS fon with the rising edge of lis Write-Enable pulse. hard-wired to the 28F512, the device powers-up and ng pulse. remains enabled for reads until the command-regis- ke 7 . ter contents are changed. Refer to the AC Read voltage io the adorecsed byte heeuine FH hon Scielanrohaatd ‘and Waveforms for specific timing the addressed byte indicates that all bits in the byte parameters. are erased. Intelligent Identifier Command The erase-verify command must be written to the command register prior to each byte verification to Flash-memories are intended for use in applications _latch its address. The process continues for each where the local CPU alters memory contents. As __ byte in the array until a byte does not return FFH such, manufacturer- and device-codes must be ac- data, or the last address is accessed. cessible while the device resides in the target sys- tem. PROM programmers typically access signature —_In the case where the data read is not FFH, another codes by raising AQ to a high voltage. However, mul- erase operation is performed. (Refer to Set-up tiplexing high voltage onto address lines is notade- __Erase/Erase). Verification then resumes from the sired system-design practice. address of the last-verified byte. Once alll bytes in the array have been verified, the erase step is com- ‘The 28F512 contains an Intelligent Identifier opera-___plete. The device can be programmed. At this point, tion to supplement traditional PROM-programming _the verify operation is terminated by writing a valid methodology, The operation is initiated by writing command (e.g. Program Set-up) to the command 90H into the command register. Following the com- _register. Figure 5, the Quick-Erase algorithm, illus- mand write, a read cycle from address 0000H re- _trates how commands and bus operations are com- trieves the manufacturer code of 89H. A read cycle _bined to perform electrical erasure of the 28F512. from address 0001H returns the device code of Refer to AC Erase Characteristics and Waveforms BBH. To terminate the operation, it is necessary to _for specific timing parameters. write another valid command into the register. ‘Set-up Program/Program Commands Set-up Erase/Erase Commands . Set-up program is a command-only operation that Set-up Erase is a command-only operation that stages the device for byte programming. Writing 40H stages the device for electrical erasure of all bytes in into the command register performs the set-up the array. The set-up erase operation is performed operation. by writing 20H to the command register. Once the program set-up operation is performed, To commence chip-erasure, the erase command the next Write-Enable pulse causes a transition to (20H) must again be written to the register. The _an active programming operation. Addresses are in- erase operation begins with the rising edge of the ternally latched on the falling edge of the Write-En- Write-Enable pulse and terminates with the rising able pulse. Data is internally latched on the rising ‘edge of the next Write-Enable pulse (.c., Erase-Veri- edge of the Write-Enable pulse. The rising edge of fy Command). Write-Enable aiso begins the programming opera- tion. The programming operation terminates with the This two-step sequence of set-up followed by execu- _next rising edge of Write-Enable, used to write the tion ensures that memory contents are not acciden- —_program-verify command. Refer to AC Programming tally erased. Also, chip-erasure can only occur when _— Characteristics and Waveforms for specific timing high voltage is applied to the Vpp pin. In the absence parameters. MH 4826175 O1bb115 2Ty 6-67
28F512 intel ° Program-Verify Command greatly reduces oxide stress and the probability of failure—increasing time to wearout by a factor of The 28F512 is programmed on a byte-by-byte basis. 100,000,000. Byte programming may occur sequentially or at ran- dom. Following each programming operation, the The 28F512 is capable of 100,000 program/erase byte just programmed must be verified. cycles. The device is programmed and erased using Intel's Quick-Pulse Programming and Quick-Erase The program-verify operation is initiated by writing algorithms. Intel’s algorithmic approach uses a se- COH into the command register. The register write __ries of operations (pulses), along with byte verifica- terminates the programming operation with the ris- _ tion, to completely and reliably erase and program ing edge of its Write-Enable pulse. The program-ver- _the device. ify operation stages the device for verification of the byte last programmed. No new address information For further information, see Reliability Report RR-60 is latched. (ETOX-Ii Reliability Data Summary). voltage to rosa’ Teron eecer read age QUICK-PULSE PROGRAMMING ALGORITHM outputs the data. A successful comparison between ick: ir the programmed byte and true data means that the Ptspone blatant rain ree byte is successfully programmed. Programming then fon 'ig followed by a byte verification to determine proceeds to the next desired byte location. Figure 4, When the addressed byte has been successtully pro- the 28F512 Quick-Pulse Programming algorithm, il- rammed. The algorithm allows for up to 25 pro- lustrates how commands are combined with bus op- rammec us , , gramming operations per byte, although most bytes erations to perform byte programming. Refer to AC Verity on the first or second operation. The entire Programming Characteristics and Waveforms for sequence of programming and byte verification is specific timing parameters. performed with Vpp at high voltage. Figure 4 illus- trates the Quick-Pulse Programming algorithm. Reset Command ‘A reset command is provided as a means to safely QUICK-ERASE ALGORITHM abort the erase- or program-command sequences. *s Quick: ann vi , Following either set-up command (erase or program) Uitel’s Quick Erase a so ielgs fast and ro} mee with two consecutive writes of FFH will safely abort Tih employs a closed-loop flow, similar to. the the operation. Memory contents will not be altered. Keke . A valid command must then be written to place the Guick-Pulse Programming algorithm, to simulta- device In tre deaked state neously remove charge from all bits in the array. Erasure begins with a read of memory contents. The EXTENDED ERASE/PROGRAM CYCLII 28F512 is erased when shipped from the factory. eH CYCLING Reading FFH data from the device would immedi- EEPROM cycling failures have always concerned _ately be followed by device programming. users. The high electrical field required by thin oxide EEPROMSs for tunneling can literally tear apart the For devices being erased and reprogrammed, uni- oxide at defect regions. To combat this, some sup- form and reliable erasure is ensured by first pro- pliers have implemented redundancy schemes, re- gramming all bits in the device to their charged state ducing cycling failures to insignificant levels. Howev- (Data = 00H). This is accomplished, using the er, redundancy requires that cell size.be doubled— Quick-Pulse Programming algorithm, in approxi- an expensive solution. mately one second. Intel has designed extended cycling capability into Erase execution then continues with an initial erase its ETOX II flash memory technology. Resulting im- operation. Erase verification (data = FFH) begins at provements in cycling reliability come without in- address 0000H and continues through the array to creasing memory cell size or complexity. First, an the last address, or until data other than FFH is en- advanced tunnel oxide increases the charge carry- countered. With each erase operation, an increasing ing ability ten-fold, Second, the oxide area per cell number of bytes verify to the erased state. Erase subjected to the tunneling electric field is one-tenth _ efficiency may be improved by storing the address of that of common EEPROM, minimizing the probabil the last byte verified in a register. Following the next ty of oxide defects in the region. Finally, the peak erase operation, verification starts at that stored ad- electric field during erasure is approximately 2MV/ —_—_ dress location. Erasure typically occurs in one sec- em lower than EEPROM. The lower electric field ond. Figure 5 illustrates the Quick-Erase algorithm.
668 MB 4826175 Olbbllb 130 a |
NOTES: 3, Reter to principles of operation.
- See DC Characteristics for value of Vper and VppL- . .
- Program Verity is only performed after byte program- 4. CAUTION: The algorithm MUST BE FOLLOWED
al) after the register is written with the Read command. vice. Figure 4. 28F512 Quick-Pulse Programming Algorithm
- See DC Characteristics for value of Vp and VepL. 8. Refer to principles of operation.
- Erase Verify is performed only after chip-erasure. A 4. CAUTION: The sigorithm MUST BE FOLLOWED
the register is written with the read command. vice. Figure 5. 28F512 Quick-Erase Algorithm
intel ° 28F512 DESIGN CONSIDERATIONS Power Up/Down Protection The 28F512 is designed to offer protection against Two-Line Output Contro! accidental erasure or programming during power transitions. Upon power-up, the 28F512 is indifferent Flash-memories are often used in larger memory ar- —_as to which power supply, Vpp or Vcc, powers up rays. Intel provides two read-control inputs to ac- first. Power supply sequencing is not required. Inter- commodate multiple memory connections. Two-line nal circuitry in the 28F512 ensures that the com- control provides for: mand register is reset to the read mode on power a. the lowest possible memory power dissipation up. and, A system designer must guard against active writes b. complete assurance that output bus contention for Vor voltages above Vixo when Vpp is active. : Since both WE # and CE# must be low for a com- , , mand write, driving either to Vix will inhibit writes. Mosrdacodor outpet’ shoud drive "chin an ae The control register architecture provides an added while the system's read signal controls all flash. __[¥6! of protection since alteration of memory con- t ° tents only occurs after successful completion of the memories and other parallel memories. This assures two, step command sequences that only enabled memory devices have active out- - puts, while deselected devices maintain the low Power standby condkion. 28F512 Power Dissipation When designing portable systems, designers must Power Supply Decoupling consider battery power consumption not only during Flash-memory power-switching characteristics re- Sevic® operation, but also for data retention. during quire careful device decoupling. System designers SYerorn. he WP vattery Mo ok your ayaten, a are interested in three Supply current (Ico) issues— Cayce the 28F512 does not consume any power to standby, active, and transient current peaks pro- s re duced by falling and rising edges of chip-enable. The "2tain code or data when the system is off. Table 4 see oe una Tacs Weck on tho doxice ouipurs lustvates the power dissipated when updating the determine the magnitudes of these peaks. 28F512. Two-line control and proper decoupling capacitor secant mee selection will suppress transient voltage peaks. yar Dissipation Each device should have a 0.1 F ceramic capacitor Power Dissipation connected between Voc and Vss, and between Vp (Watt-Seconds) ‘SS: Array Program/ 1 0.085 Place the high-frequency, low-inherent-inductance Program Verify capacitors as close as possible to the devices. Also, for every eight devices, a 4.7 .F electrolytic capaci- arey ase! 0.092 tor should be placed at the array’s power supply rase Verity connection, between Vcc and Vgg. The bulk capaci- | One Complete Cycle | 3 | 0.262 —*| tor will overcome voltage slumps caused by printed- circuit-board trace inductance, and will supply NOTES: charge to the smaller capacitors as needed. 1. Formula to calculate typical Program/Program Verity Power = [Vpp x # Bytes x Typical # Prog Pulses ae apt YP ipice Bg ules Cerny ircui loc_X tes x Typi og Pulses (twHwHt * Vpp Trace on Printed Circuit Boards toga Typical + twat * loos Typica). Programming flash-memories, while they reside in 7: rls eee reel Grase/Frase Mali aitiel the target system, requires that the printed circuit jar s<"# Bytesll + [Vectlace Typical > tenage TPL board designer pay attention to the Vpp power sup- _¢al'S"locg Typical X twa # Bytes)] ply trace. The Vpp pin supplies the memory cell cur- 3. One Complete Cycle Array Preprogram + Array rent for programming. Use similar trace widths and Erase + Program. layout considerations given the Voc power bus. Ad- 4. ““Typicals” are not guaranteed, but based on a limited equate Vpp supply traces and decoupling will de- number of samples from production lots. crease Vpp voltage spikes and overshoots. | mm 4426175 OF66119 957 6-71
ABSOLUTE MAXIMUM RATINGS* Vpp Supply Voltage with Respect to Ground - ¢ Maximum Ratings” may cause permanent damage. Voltage on Any Pin with “Operating Conditions” is not recommended and ex- Voltage on Pin Ag with may affect device reliability. NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Operating temperature is for extended temperature product defined by this specification. Maximum DC voltage on output pins is Voc + 0.5V, which may overshoot to Voc + 2.0V for periods less than 20 ns. 4, Maximum DC voltage on Ag oF Vp may overshoot to +14.0V for periods less than 20 ns. 5. Output shorted for no more than one second, No more than one output shorted at a time. OPERATING CONDITIONS. Ta Operating Temperatura(’) 70 | °C | ForRead-Only and Read/Write Operations for Commercial Products Ta Operating Temperature(2) +85 | °C | ForRead-Only and Read/Write Operations for Extended Temperature Products Veo supplyvotage | 450 | sso v [ DC CHARACTERISTICS—TTL/NMOS COMPATIBLE—Commercial Products [_bimits | Test Conditions lu Input Leakage Current 1 #1.0 | wA | Voc = Voc Max Vin = Voc oF Vss ho Output Leakage Current | 1 +10.0] wA | Voc = Voc Max Vout = Voc or Vss Voc Standby Current mA | Voc = Voc Max CE# = Vin Voc Active Read Current | 1 10 mA | Voc = Voc Max, CE# = Vip f = 6 MHz, lout = mA Voc Programming mA | Programming in Progress Current [cca [Voctrasecurent | 1.2 | | 50 | 15 | mA | ErasureinProgress | Voc Program Verify 1.2 mA | Vpp = VppH Current Program Verify in Progress 6-72 MH 4826175 0166120 bbl mo
DC CHARACTERISTICS—TTL/NMOS COMPATIBLE—Commercial Products (Continued) symbot | timite | Test Conditions [ win [tye | Mex _| Voc Erase Verity Current Vpp = VepH Erase Verify in Progress [ives |Vepteskage Curent | 1 | [| #100 | walVersvoo Vpp Read Current, Standby BA | Vpp > Voc Current, or 1D Current | | 100 | Vpp Programming Current 1.2 mA | Vpp = VepH Programming in Progress Vpp Erase Current 1.2 40 Vpp = VppH Erasure in Progress Vpp Program Verity Current 1,2 mA | Vpp = VepH Program Verity in Progress Vpp Erase Verity Current mA | Vpp = VppH Erase Verity in Progress Input Low Voltage | feos} Tos Pv Input High Votage [ao | |veceosf vf Vor _ | Output Low Voltage V | op = 5.8mA Voc = Voo Min Vor | Output High Voltage V_ | toy = -2.5mA Voc = Voo Min [vio _[Aaintetigntidentiiorvorage | [iso] | t300 |v [ [i [Aeimetigentidentiter Curent | 1.2 | [oo | 200 [ua |Ae=Vio | Vee. _ | Vpp during Read-Only V_ | NOTE: Erase/Program are Operations Inhibited when Vpp = Vppt VppH | Vpp during Read/Write 11.40 1260 | V Operations x [vino [Vvoctrserwrtetockvotese] [2s] | vf DC CHARACTERISTICS—CMOS COMPATIBLE—Commercial Products Test Condit jons | min | Type | max | lu Input Leakage Current 1 £1.0 | wA | Voc = Voc Max Vin = Voc or Vs Output Leakage Current 1 £10.0| pA | Voc = Voc Max Vout = Voc or Vss Voc Standby Current 1 pA | Voc = Voc Max CE# = Voc +0.2V Voc Active Read Current 1 mA | Voc = Voc Max, CE# = Vi. 1 = 6 MHz, loyy = OMA | MH 4826175 Olbbi2l STS 6-73
2BF512 intel ° DC CHARACTERISTICS—CMOS COMPATIBLE—Commercial Products (Continued) symbol [tite Voc Programming 1.0 Programming in Progress Current [tccs_[Voctresocurent | 2 | | 0 | 15 | ma | ErasuroinProgess | loca Voc Program Verity Vpp = VpPH Current Program Verity in Progross lees Voc Erase Verify Current Vep = VppH Erase Vorify in Progress lies | Vptooaecumere [1 |_| | 2108 [wa |Wrs¥oo | VppRead Current ID | 1 | 90 | 200 | wa Current, or Standby aan Pees | Vpp Programming mA | Vpp = VppH. Current Programming in Progress Vpp Erase Current Vpp = VppH Erasure in Progress Vpp Program Verify MA | Vpp = VepH. Current Program Verify in Progress Vpp Erase Verify Current mA | Vpp = VppH Erase Verity in Progress [va [rowiowvotwge | | os || |v] id [von —[rpueripn vous | | orvoo | [verosfv| ——S—~*d Vo. | Output Low Voltage V to. = 5.8mA Voc = Veo Min Vout | Output High Voltage 0.85 Voc lon = —2.5mA, v « Voc = Veo Min Vone Voc — 0.4 lon = —100 pA, Voc = Veo Min Vio _| Ag Intelligent Identifier 1300 | V | Ag = Vip Voltage ‘Ag Intelligent Identifier BA | Ag = Vin Current VepL | Vpp during Read-Only V_ | NOTE: Erase/Program Operations are Inhibited when Vep = VppL Ver — | Vep during Read/Write 1260 | Vv Operations ViKo. Voc Erase/Write Lock v Voltage 6-74 M@! 4826175 Olbb122 434 mw
DC CHARACTERISTICS—TTL/NMOS COMPATIBLE—Extended Temperature Products ome vent conaions Cocca lu Input Leakage Current || +10 Veo = Veo Max Vin = Voc or Vss lio | Output Leakage Current 10.0 | pA |Voc = Voc Max Vout = Vecor Vss locs Veo Standby Current 1.0 mA |Voc = Voc Max CE# = Vin Voc Active Read Current 1 mA |Voc = Voc Max, CE# = Vit f = 6 MHz, lout = OMA loce _|VeoProwamming Curent [1,2 | | 1.0 | 30 [mA Programming in Progress cca _|VooEreseGurent | 1.2 | | 50 | 30 |malraswoinProwess | cca | Voc Program Verify Current mA |Vpp = VepH Program Verify in Progress Voc Erase Verify Current Vpp = VepH Erase Verify in Progress linps_|Vep Leakage Current [+ [ [ [2100 [oa Wer svoo | op Read Current, Standby [90 | 200 | na arent of Curent [| S09 | Vp Programming Current mA |Vpp = VppH Programming in Progress Vpp Erase Current Vpp = VppH Erasure in Progress Vpp Program Verify Current | 1,2 mA |Vpp = VppH Program Verify in Progress Vpp Erase Verify Current mA | Vpp = VepH Erase Verify in Progress [vn [input Low Votage | [-es[ [oe [vf Input High Voltage | Teot Weerosfv | Vo. —_| Output Low Voltage 0.45 | V |lop = 5.8mA Voc = Voc Min Voxs | Output High Voltage V |lon = —2.5mA Voc = Veo Min Agineligentldentier Votage| —[v1so[ | 1300 Tv] lio _[Aalnteligent identifier Curent| 1.2 [ | 90 | 500 [pAlAe=vo | Vee. |Vpp during Read-Only V_|NOTE: Erase/Program are Operations Inhibited when Vpp = VepL VppH | Vpp during Read/Write v Operations VocErase/Witetockvetage| —[2s[ | [vf ee | MB 4826175 0166123 370 6-75
DC CHARACTERISTICS—CMOS COMPATIBLE—Extended Temperature Products symbol [__timits Test Conditions lu Input Leakage Current $1.0 BA | Voc = Voo Max Vin = Voc or Vss ho Output Leakage Current 1 £100 | MA | Voc = Voc Max Vout = Voc or Vss Voc Standby Current BA | Voc = Voc Max CE# = Voc +0.2V loca Voc Active Read Current Voc = Voc Max, CE# = Vi f = 6 MHz, lout = OMA ['oce__|VocProwanmingCurent| 1.2 [ [10 | 10 | ma | Prowammingin Prooross | liccs [Vootasecuren | 1.2] | so | 15 | ma |ensucinpregess | loca | Voc Program Verity mA | Vpp = VppH Current Program Verify in Progress Voc Erase Verify Current Vpp = VppH Erase Verify in Progress [iss | Venteatagouron | 1 | || #100 [pA Vmrs¥oo | Ver Read Curent, 1D | 20 | 200 | Current, or Standby Vpp = Vi Vpp Programming Current mA | Vpp = Vppy Programming in Progress Vpp Erase Current mA | Vpp = VepH Erasure in Progress Vpp Program Verify 1,2 Vep = VppH Current Program Verify in Progress Vpp Erase Verify Current mA | Vpp = VepH. Erase Verify in Progress [vx [wouttowvetwss | | os} |e |v] Vo. .| Output Low Voltage V | lo, = 5.8mA Voc = Voo Min 6-76 Mi 4626175 0166124 207 |
DC CHARACTERISTICS—CMOS COMPATIBLE—Extended Temperature Products (Continued) symbot | timits | sae | teat Conditions Voni | Output High Voltage 0.85 Veo lon = -2.5 mA, Voc = Voc Min Vou2 Veo — 0.4 lon = —100 pA, Voc = Voo Min [io [Astiatgonteniirvorae | | so | _[ra00[ v [ay=vo | lio [Astustgenintiercuren | xa |_| © | ow larln=vo | Vpp. _ | Vpp during Read-Only Operations V_ | NOTE: Erase/ Program are Inhibited when Vep = VepL Voctraserwrtotockvorage | | 28 | | [v] | CAPACITANCE Ta = 25°C, f = 1.0 MHz Aderess/GonrolCapactance [9 | [| 6 | oF | vw=% | Output Capacitance [os fe | | vor = ov . NOTES: currents are valid for all product versions (packages and speeds). 2. Not 100% tested: characterization data available. 3. Samplad, not 100% tested. 44, “Typicals” are not guaranteed, but based on a limited number of samples from production lots. | MH 4826175 Olbb12e5 143 a 677
AC TESTING INPUT/OUTPUT WAVEFORM AC TESTING LOAD CIRCUIT 24 13V Input 28 D> test pownrs cs 0.45 - t N94 output og D> TEST Points 33K TSS |) 290204-8 Tr = 100 pF AC Testing: Inputs are driven at 2.4V for a logic “1” and 0.45V for — 2 logic “0”. Testing measurements are made at 2.0V for a logic 200204-9 “1 and O.BV for a logic “0”. Riso/Fall imo < 10 ns, © = 100 pF C, includes Jig Capacitance AC TEST CONDITIONS AC CHARACTERISTICS—Read-Only Operations N28F512-120 TN28F512-120 | N26F512-150 Versions(®) P28F512-120 P2BF512-150 TP28F512-120 Road Cycle Time [fo [| i0 [Ts | Chip Enable Access Time | ff eo TY 150 Tn | Address Access Time | [| v0 350 | Output Enable Access Time a ChipEnableroOuputintowz | 23 | o | | o | Tas | [ter | chipDisabietoOupuinnignz [2 [ [ss [| 65 | ns | OuputEnabletoOuiputintowZ | 29 | o | | o [| rs | Output DisabletoOutputinHighZ | 2 | | so | [35 | ns | toH Output Hold from Address, CE #, or OE# Change Write Recovery TimebeforeRead | | 6 | | 6 | | us| NOTES: 1. Model number prefixes: N = PLCC, P = PDIP, T = Extended Temperature, 2. Sampled, not 100% tested. 3. Guaranteed by design. 4, Whichever occurs first. 6-78 MB 4826175 Olbb12b O8T mm
Figure 6. AC Waveforms for Read Operations
AC CHARACTERISTICS—Write/Erase/Program Operations(1, 4) Wie Cycle Time [fro [| 50 fs | Address Set-Up Time pf o Po TT | Address Hold Time | [eo [eo Ts | Data Setup Time a Data Hold Time | fo | fo PTs | WriteRecovey TimebeforeRead | | 6 | | 6 | | us| ReadRecovery Timebeforewrte | 2 | o | | o [| us| Chip Enable Hold Time [| fof fo [Tes | Write Pulse Width ee Write Pulse Width High re [twin | Ouration ot Programming Operation | 3 | 10 | | 10 | ‘| ns | Duration of Erase Operation | s [es [fies [| ms | Ver Set-UpTimetoChipEnabieLow | 2 [10 | [+0 | [us| NOTES: 1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Char- acteristics for Read-Only Operations. 2. Guaranteed by design. 3. The integrated stop timer terminates the programming/erase operations, thereby eliminating the need for a maximum ‘specification. 4, Erase/Program cycles on extended temperature products is 1,000 cycles. ERASE AND PROGRAMMING PERFORMANCE je | N/P28F512-120, 150 ‘TN/TP28F512-120(6) om | min | tye [Mex [win | tye [Max | Chip Erase 10 Time Chip Program 1,2,4 Time NOTES: 1. “Typicals” are not guaranteed, but based on a iimited number of samples from production lots. Data taken at 25°C, 12.0V Vpp at 0 cycles. 2. Minimum byte programming time excluding system overhead is 16 4s (10 us program + 6 ys write recovery), while maximum is 400 ps/byte (16 us x 25 loops allowed by algorithm). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case byte. 3. Excludes 00H Programming Prior to Erasure. 4, Excludes System-Level Overhead. 5, Refer to RR-60 “ETOX I! Flash Memory Reliability Data Summary” for typical cycling data and failure rate calculations. 6. Extended temperature products 6-80 ME 4826175 O1bb128 952 Me
Does not include Pre-Erase program. Figure 9. 28F512 Typical Erase Time at 12V
50 PPA or
Does not include Pre-Erase program. Figure 10. 28F512 Typical Erase Capability
52 ROS47 r
Figure 11. AC Waveforms for Programming Operations
ALTERNATIVE CE #-CONTROLLED WRITES tavav Write Cycle Time tAVEL Address Set- Up Time tELAK Address Hold Time Data Set-Up Time teHDx Data Hold Time tEHGL Write BS Recovery Time before Read toHEL Read us Recovery Time before Write tWLEL Write Enable ‘Set-Up Time before Chip Enable teHWH Write Enable Hold Time teLEH Write Pulse 1 70 70 Width tEHEL Write Pulse Width High tvPEL Vpp Set-Up HS Time to Chip Enable Low NOTE: 1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up, hold and inactive Write-Enable times should be measured relative to the Chip-Enable waveform. : 2. Guaranteed by design. 6-84 M™ 4826175 O1bb132 343 Ml | | ;
8 Kesg
25 BSS Zs
52 RSeg7 P
Figure 12. AC Waveforms for Erase Operations
25 BeSd AS
82 BeSd
Figure 13. Alternate AC Waveforms for Programming Operations
Ordering Information
GRBOGenBeHao| P= 32-PIN PLASTIC DIP 120n8 N= 32-LEAD PLce 150s ‘TEMPERATURE T= EXTENDED (-40°C TO +85°C) BLANK = COMMERCIAL (0°C TO +70°C) 200204—13 Valid Combinations: P28F512-120 N28F512-120 TP28F512-120 P28F512-150 N28F512-150 TN28F512-120 ADDITIONAL INFORMATION Order Number ER-20, “ETOX II Flash Memory Technology” 294005 ER-24, “Intel Flash Memory” 294008 AIR-60, “ETOX Il Flash Memory Reliability Data Summary” 293002 AP-316, “Using Flash Memory for In-System Reprogrammable 292046 Nonvolatile Storage” AP-325 "Guide to Flash Memory Reprogramming” 292059
REVISION HISTORY
Revised Erase Maximum Pulse Count for Figure 5 from 3000 to 1000 Clarified AC and DC test conditions
007 Corrected AC Waveforms
Added Extended Temperature devices; TP28F 512-120, TN28F512-120 [| oss Revised symbols; Le., CE, OE, etc. to CE#, OEF, ato. | ME 4626175 0166135 092 mm 687
intel. SMALL OUTLINE PACKAGE GUIDE OVERVIEW Intent This overview provides a quick reference for the Small Outline Package Guide, Intel literature order number 296514. Contents The table below details, in outline form, the type of information that can be found in the guide. How to Order Phone: (800) 548-4725 in US and Canada Outside US/Canada, contact local Intel or distributor sales office or write to: Intel Corporation Literature Sales P.O. Box 7641 Mt. Prospect, IL 60056-7641 Package * Small-Form-Factor/Fine-Pitch Introduction Description * TSOP, SSOP and PSOP Key Features * Device/Package Offerings SOP Layout * Space-Saving Features Features and * Device Pinouts Applications * SOP Applications SOP Physical * Package Drawings and Specifications Dimensions * PCB Land-Pad Layout Diagrams * Component Volume and Weight Characteristics ¢ Thermal Data SOP Manufacturing * Assembly Process Flow * Package Materials * Cross-Section Diagrams * Electrical and Solderability Test * Mechanical Inspection ‘SOP Reliability * Temperature Cycling via Convection Stresses ¢ Thermal Shock, Liquid-to-Liquid Stress * Steam, Accelerated Moisture Penetration Stress * 85°C/85% Relative Humidity, Alternate Pins Biased (+ 5V and GND) * High-Temperature Dynamic Life Test * Solder-Joint Reliability e * Surface Mount Process Considerations * Use Condition Considerations * Solder-Joint Life Predictions Curves SOP Handling © SOP Shipping Formats * Tray Diagrams and Dimensions © Tray Recycling * Tape and Reel Carrier Diagrams and Dimensions * Tube Diagrams and Dimensions * Moisture Considerations and Data — Moisture Sensitivity Classification Levels — Preconditioning Flow — Test Conditions Table — SOP Moisture Reliability Levels — Moisture Absorption and Desorption ‘October 1995
214 MH 4826175 0165295 550 mm (Order Number: 297542-002
SOP SMT Assembly © Storage and Handling Considerations Screen Printing — Solder Paste — Solder Volume — Solder Mask — Stencil — Vision System — Squeegee © Placement Equipment * Cleaning °IR Furnace PCB Design Considerations * Lead Placement Examples: — Good Placement —Misaligned —Lifting Information References and * Other Reference Material Additional Information Appendix A: SOP * SOP Vacuum Wand Suppliers ‘Support Tools ® SOP Programming Adapter Suppliers SOP Distribution Programming Support © SOP Independent Programming Houses * SOP Socket Suppliers — Prototyping Sockets — Production Sockets — Burn-In/Programming Sockets © SOP Programmer and Handler Vendors. * SOP Manufacturing Equipment Suppliers SOP Custom Board Manufacturing and Interposer Mounting ‘Appendix B: ‘SOP Reference Articles References Appendix C: SOP * EIA/JEDEC ‘Standards Bodies * ANSI *IPC * EIAJ | MB 4826175 Ob52%b 497 a 215