28F400B3 INTEL | Alldatasheet
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Technical content
Datasheet sections
- 1.0 INTRODUCTION
- 1.1 Smart 3 Advanced Boot Block Flash
- 1.2 Product Overview
- 2.0 PRODUCT DESCRIPTION
- 2.1 Package Pinouts
- 2.2 Block Organization
- 2.2.1 Parameter Blocks
- 2.2.2 Main Blocks
- 3.0 PRINCIPLES OF OPERATION
- 3.1 Bus Operation
- 3.1.1 Read
- 3.1.3 Standby
- 3.1.4 Deep Power-Down / Reset
- 3.1.5 Write
- 3.2 Modes of Operation
- 3.2.1 Read Array
- 3.2.2 Read Intelligent Identifier
- 3.2.3 Read Status Register
- 3.2.4 Program Mode
- 3.2.5 Erase Mode
- 3.3 Block Locking
- 3.3.2 WP# = VIL for Block Locking
- 3.3.3 WP# = VIH for Block Unlocking
- 3.4 VPP Program and Erase Voltages
- 3.5 Power Consumption
- 3.5.1 Active Power
- 3.5.2 Automatic Power Savings (APS)
- 3.5.3 Standby Power
- 3.5.4 Deep Power-Down Mode
- 3.6 Power-Up/Down Operation
- 3.6.1 RP# Connected to System Reset
- 3.7 Power Supply Decoupling
- 3.7.1 VPP Trace On Printed Circuit Boards
- 4.0 ABSOLUTE MAXIMUM RATINGS
- 5.0 OPERATING CONDITIONS (V
- 7.0 AC CHARACTERISTICS
- 7.1 Reset Operations
E PRELIMINARY Ma y 1997 Order Number: 290580-002 /c110 Flexible SmartVoltage Technology 2.7V–3.6V Program/Erase 2.7V–3.6V Read Operation 12V VPP Fast Production Programming /c110 2.7V or 1.8V I/O Option Reduces Overall System Power /c110 Optimized Block Sizes Eight 4-KW Blocks for Data, Top or Bottom Locations Up to Thirty-One 32-KW Blocks for Code /c110 High Performance 2.7V–3.6V: 120 ns Max Access Time /c110 Block Locking VCC -Level Control through WP# /c110 Low Power Consumption 20 mA Maximum Read Current /c110 Absolute Hardware-Protection VPP = GND Option VCC Lockout Voltage /c110 Extended Temperature Operation –40°C to +85°C /c110 Supports Code Plus Data Storage Optimized for FDI, Flash Data Integrator Software Fast Program Suspend Capability Fast Erase Suspend Capability /c110 Extended Cycling Capability 10,000 Block Erase Cycles /c110 Automated Word Program and Block Erase Command User Interface Status Registers /c110 SRAM-Compatible Write Interface /c110 Automatic Power Savings Feature /c110 Reset/Deep Power-Down 1 µA ICC Typical Spurious Write Lockout /c110 Standard Surface Mount Packaging 48-Ball µBGA* Package 48-Lead TSOP Package /c110 Footprint Upgradeable Upgradeable from 2-, 4- and 8-Mbit Boot Block /c110 ETOX™ V (0.4 µ) Flash Technology The new Smart 3 Advanced Boot Block, manufactured on Intel’s latest 0.4µ technology, represents a feature- rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability (2.7V read, program and erase) with high-speed, low-power operation. Several new features have been added, including the ability to drive the I/O at 1.8V, which significantly reduces system active power and interfaces to 1.8V controllers. A new blocking scheme enables code and data storage within a single device. Add to this the Intel-developed Flash Data Integrator (FDI) software and you have the most cost-effective, monolithic code plus data storage solution on the market today. Smart 3 Advanced Boot Block Word-Wide products will be available in 48-lead TSOP and 48-ball µBGA* packages. Additional information on this product family can be obtained by accessing Intel’s WWW page: http://www.intel.com/design/flcomp. SMART 3 ADVANCED BOOT BLOCK WORD-WIDE 4-MBIT (256K X 16), 8-MBIT (512K X 16), 16-MBIT (1024K X 16) FLASH MEMORY FAMILY 28F400B3, 28F800B3, 28F160B3
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F400B3, 28F800B3, 28F160B3 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 or visit Intel’s website at http:\\\\www.intel.com COPYRIGHT © INTEL CORPORATION 1996, 1997 CG-041493 *Third-party brands and names are the property of their respective owners
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REVISION HISTORY
-001 Original version -002 Section 3.4, VPP Program and Erase Voltages, added Updated Figure 9: Automated Block Erase Flowchart Updated Figure 10: Erase Suspend/Resume Flowchart (added program op. to table) Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes) I PPR maximum specification change from ±25 µA to ±50 µA Program and Erase Suspend Latency specification change Updated Appendix A: Ordering Information (included 8M and 4M information) Updated Figure, Appendix D: Architecture Block Diagram (Block info. in Words not bytes) Minor wording changes
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1.0 INTRODUCTION
This preliminary datasheet contains the specifications for the Advanced Boot Block flash memory family, which is optimized for low power, portable systems. This family of products features 1.8V–2.2V or 2.7V–3.6V I/Os and a low V CC /VPP operating range of 2.7V–3.6V for read and program/erase operations. In addition this family is capable of fast programming at 12V. Throughout this document, the term “2.7V” refers to the full voltage range 2.7V–3.6V (except where noted otherwise) and “V PP = 12V” refers to 12V ±5%. Section 1 and 2 provides an overview of the flash memory family including applications, pinouts and pin descriptions. Section 3 describes the memory organization and operation for these products. Finally, Sections 4, 5, 6 and 7 contain the operating specifications.
1.1 Smart 3 Advanced Boot Block
The new 4-Mbit, 8-Mbit, and 16-Mbit Smart 3 Advanced Boot Block flash memory provides a convenient upgrade from and/or compatibility to previous 4-Mbit and 8-Mbit Boot Block products. The Smart 3 product functions are similar to lower density products in both command sets and operation, providing similar pinouts to ease density upgrades. The Smart 3 Advanced Boot Block flash memory
features
- Enhanced blocking for easy segmentation of code and data or additional design flexibility
- Program Suspend command which permits program suspend to read
- WP# pin to lock and unlock the upper two (or lower two, depending on location) 4-Kword blocks
- V CCQ input for 1.8V–2.2V on all I/Os. See Figure 1-4 for pinout diagrams and VCCQ location
- Maximum program time specification for improved data storage.
Table 1. Smart 3 Advanced Boot Block Feature Summary
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1.2 Product Overview
Intel provides the most flexible voltage solution in the flash industry, providing three discrete voltage supply pins: V CC for read operation, VCCQ for output swing, and VPP for program and erase operation. Discrete supply pins allow system designers to use the optimal voltage levels for their design. All Smart
3 Advanced Boot Block flash memory products
provide program/erase capability at 2.7V or 12V and read with V CC at 2.7V. Since many designs read from the flash memory a large percentage of the time, 2.7V V CC operation can provide substantial power savings. The 12V VPP option maximizes program and erase performance during production programming. The Smart 3 Advanced Boot Block flash memory products are high-performance devices with low power operation. The available densities for word- wide devices (x16) are a. 4-Mbit (4,194,304-bit) flash memory organized as 256-Kwords of 16 bits each b. 8-Mbit (8,388,608-bit) flash memory organized as 512-Kwords of 16 bits each c. 16-Mbit (16,777,216-bit) flash memory organized as 1024-Kwords of 16 bits each. For byte-wide devices (x8) see the Smart 3 Advanced Boot Block Byte-Wide Flash Memory Family datasheet. The parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. The upper two (or lower two) parameter blocks can be locked to provide complete code security for system initialization code. Locking and unlocking is controlled by WP# (see Section 3.3 for details). The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verification, thereby unburdening the microprocessor or microcontroller. The status register indicates the status of the WSM by signifying block erase or word program completion and status. Program and erase automation allows program and erase operations to be executed using an industry- standard two-write command sequence to the CUI. Data writes are performed in word increments. Each word in the flash memory can be programmed independently of other memory locations; every erase operation erases all locations within a block simultaneously. Program suspend allows system software to suspend the program command in order to read from any other block. Erase suspend allows system software to suspend the block erase command in order to read from or program data to any other block. The Smart 3 Advanced Boot Block flash memory is also designed with an Automatic Power Savings (APS) feature which minimizes system current drain, allowing for very low power designs. This mode is entered immediately following the completion of a read cycle. When the CE# and RP# pins are at V CC , the ICC CMOS standby mode is enabled. A deep power- down mode is enabled when the RP# pin is at GND, minimizing power consumption and providing write protection. I CC current in deep power-down is 1 µA typical (2.7V VCC ). A minimum reset time of tPHQV is required from RP# switching high until outputs are valid to read attempts. With RP# at GND, the WSM is reset and Status Register is cleared. Section 3.5 contains additional information on using the deep power-down feature, along with other power consumption issues. The RP# pin provides additional protection against unwanted command writes that may occur during system reset and power-up/down sequences due to invalid system bus conditions (see Section 3.6). Refer to the DC Characteristics Table, Sections 5.1 and 6.1, for complete current and voltage specifications. Refer to the AC Characteristics Table, Section 7.0, for read, program and erase performance specifications.
2.0 PRODUCT DESCRIPTION
This section explains device pin description and package pinouts.
2.1 Package Pinouts
Figure 1. 48-Lead TSOP Package
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Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades. Routing is not recommended in this area. **Figure 2. 4-Mbit 48-Ball µBGA* Chip Size Package** Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades. Routing is not recommended in this area. **Figure 3. 8-Mbit 48-Ball µBGA* Chip Size Package**
Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades. Routing is not recommended in this area. **Figure 4. 16-Mbit 48-Ball µBGA* Chip Size Package**
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The pin descriptions table details the usage of each device pin. Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions latched during a program or erase cycle. WE# cycle during a Program command. Data is internally latched. when the chip is de-selected. current will increase due to current flow through the CE# and RP# inputs. buffers during an array or status register read. OE# is active low. edge of the second WE# pulse. control reset/deep power-down mode. Machine, and draws minimum current. When RP# is at logic high, the device is in standard operation. [program] or SR.5 [erase] will be set to indicate the operation failed. can be programmed or erased. See Section 3.3 for details on write protection.
Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions (Continued) This input may be tied directly to VCC (2.7V–3.6V). See the DC Characteristics for further details. are locked and protected against Program and Erase commands. cycles on the main blocks and 2500 cycles on the parameter blocks. NC NO CONNECT: Pin may be driven or left floating.
2.2 Block Organization
Figure 6 (bottom boot blocking).
2.2.1 PARAMETER BLOCKS
rewrite functionality of EEPROMs can be emulated. blocks of 4-Kwords (4,096-words) each.
2.2.2 MAIN BLOCKS
8-Mbit device contains fifteen 32-Kword blocks.
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Figure 5. 4-/8-/16-Mbit Advanced Boot Block Word-Wide Top Boot Memory Maps
Figure 6. 4-/8-/16-Mbit Advanced Boot Block Word-Wide Top Boot Memory Maps
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3.0 PRINCIPLES OF OPERATION
program and erase, are accessible via the CUI. as system status requests during WSM operation.
3.1 Bus Operation
Table 3. Bus Operations for Word-Wide Mode
- Refer to DC Characteristics.
IL, VIH for control pins and addresses, VPPLK , VPPH1 or VPPH2 for VPP .
- See DC Characteristics for VPPLK , VPPH1 , VPPH2 voltages.
- Manufacturer and device codes may also be accessed via a CUI write sequence, A1–A19 = X
- See Table 5 for device IDs.
- Refer to Table 6 for valid D
IN during a write operation.
- Command writes for block erase or word program are only executed when VPP = VPPH1 or VPPH2 .
- To program or erase the lockable blocks, hold WP# at VIH. See Section 3.3.
- RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.
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3.1.1 READ
The flash memory has three read modes available: read array, read identifier, and read status. These modes are accessible independent of the V PP voltage. The appropriate read mode command must be issued to the CUI to enter the corresponding mode. Upon initial device power-up or after exit from deep power-down mode, the device automatically defaults to read array mode. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control; when active it enables the flash memory device. OE# is the data output (DQ 0–DQ 15) control and it drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at V IH. Figure 15 illustrates a read cycle.
3.1.2 OUTPUT DISABLE
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0–DQ 15 are placed in a high-impedance state.
3.1.3 STANDBY
Deselecting the device by bringing CE# to a logic- high level (VIH) places the device in standby mode, which substantially reduces device power consumption. In standby, outputs DQ 0–DQ 15 are placed in a high-impedance state independent of OE#. If deselected during program or erase operation, the device continues to consume active power until the program or erase operation is complete.
3.1.4 DEEP POWER-DOWN / RESET
RP# at V IL initiates the deep power-down mode, sometimes referred to as reset mode. From read mode, RP# going low for time tPLPH accomplishes the following: 1. deselects the memory 2. places output drivers in a high-impedance state After return from power-down, a time t PHQV is required until the initial memory access outputs are valid. A delay (t PHWL or tPHEL ) is required after return from power-down before a write sequence can be initiated. After this wake-up interval, normal operation is restored. The CUI resets to read array mode, and the status register is set to 80H (ready). If RP# is taken low for time t PLPH during a program or erase operation, the operation will be aborted and the memory contents at the aborted location are no longer valid. After returning from an aborted operation, time t PHQV or tPHWL /tPHEL must be met before a read or write operation is initiated respectively.
3.1.5 WRITE
A write is any command that alters the contents of the memory array. There are two write commands: Program (40H) and Erase (20H). Writing either of these commands to the internal Command User Interface (CUI) initiates a sequence of internally- timed functions that culminate in the completion of the requested task (unless that operation is aborted by either RP# being driven to V IL for tPLRH or an appropriate suspend command). The Command User Interface does not occupy an addressable memory location. Instead, commands are written into the CUI using standard microprocessor write timings when WE# and CE# are low, OE# = V IH, and the proper address and data (command) are presented. The command is latched on the rising edge of the first WE# or CE# pulse, whichever occurs first. Figure 16 illustrates a write operation. Device operations are selected by writing specific commands into the CUI. Table 4 defines the available commands. Appendix B provides detailed information on moving between the different modes of operation.
3.2 Modes of Operation
The flash memory has three read modes and two write modes. The read modes are read array, read identifier, and read status. The write modes are program and block erase. Three additional modes
16 PRELIMINARY
Table 4. A comprehensive chart showing the state transitions is in Appendix B.
3.2.1 READ ARRAY
- WE# must be logic high (V IH)
- CE# must be logic low (VIL)
- OE# must be logic low (VIL)
- RP# must be logic high (VIH) In addition, the address of the desired location must be applied to the address pins. If the device is not in read array mode, as would be the case after a program or erase operation, the Read Array command (FFH) must be written to the CUI before array reads can take place.
Table 4. Command Codes and Descriptions
00 Invalid/
redefine these codes for future functions.
40 Program
after programming to read array data. See Section 3.2.4.
10 Alternate
20 Erase
and (c) wait for another command. See Section 3.2.5. command will resume that operation. data when CE# or OE# is toggled.
Table 4. Command Codes and Descriptions (Continued)
70 Read Status
program or erase operation has been initiated. See Section 3.2.3.
50 Clear Status
90 Intelligent
A0 = 1 for device, all other address inputs are ignored). See Section 3.2.2. See Appendix B for mode transition information.
3.2.2 READ INTELLIGENT IDENTIFIER
Table 5. Intelligent Identifier Table
3.2.3 READ STATUS REGISTER
the Read Array (FFH) command. Read Status Register command. completion of a program or erase operation.
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When the WSM is active, SR.7 will indicate the status of the WSM; the remaining bits in the status register indicate whether or not the WSM was successful in performing the desired operation (see Table 7).
3.2.3.1 Clearing the Status Register
The WSM sets status bits 1 through 7 to “1,” and clears bits 2, 6 and 7 to “0,” but cannot clear status bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4 and 5 indicate various error conditions, these bits can only be cleared by the controlling CPU through the use of the Clear Status Register (50H) command. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before reading the status register to determine if an error occurred during that series. Clear the Status Register before beginning another command or sequence. Note, again, that the Read Array command must be issued before data can be read from the memory array.
3.2.4 PROGRAM MODE
Programming is executed using a two-write sequence. The Program Setup command (40H) is written to the CUI followed by a second write which specifies the address and data to be programmed. The WSM will execute the following sequence of internally timed events: 1. Program the desired bits of the addressed memory. 2. Verify that the desired bits are sufficiently programmed. Programming of the memory results in specific bits within an address location being changed to a “0.” If the user attempts to program “1”s, there will be no change of the memory cell contents and no error occurs. The status register indicates programming status: while the program sequence is executing, bit 7 of the status register is a “0.” The status register can be polled by toggling either CE# or OE#. While programming, the only valid commands are Read Status Register, Program Suspend, and Program Resume. When programming is complete, the Program Status bits should be checked. If the programming operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If SR.3 is set then V PP was not within acceptable limits, and the WSM did not execute the program command. If SR.1 is set, a program operation was attempted to a locked block and the operation was aborted. The status register should be cleared before attempting the next operation. Any CUI instruction can follow after programming is completed; however, to prevent inadvertent status register reads, be sure to reset the CUI to read array mode.
3.2.4.1 Suspending and Resuming
The Program Suspend command allows program suspension in order to read data in other locations of memory. Once the programming process starts, writing the Program Suspend command to the CUI requests that the WSM suspend the program sequence (at predetermined points in the program algorithm). The device continues to output status register data after the Program Suspend command is written. Polling status register bits SR.7 and SR.2 will determine when the program operation has been suspended (both will be set to “1”). t WHRH1 /tEHRH1 specify the program suspend latency. A Read Array command can now be written to the CUI to read data from blocks other than that which is suspended. The only other valid commands, while program is suspended, are Read Status Register and Program Resume. After the Program Resume command is written to the flash memory, the WSM will continue with the program process and status register bits SR.2 and SR.7 will automatically be cleared. After the Program Resume command is written, the device automatically outputs status register data when read (see Figure 8, Program Suspend/Resume Flowchart). V PP must remain at the same VPP level used for program while in program suspend mode. RP# must also remain at V IH.
3.2.4.2 V PP Supply Voltage during
VPP supply voltage considerations are outlined in Section 3.4
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3.2.5 ERASE MODE
To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only one block can be erased at a time. The WSM will execute the following sequence of internally timed events to: 1. Program all bits within the block to “0.” 2. Verify that all bits within the block are sufficiently programmed to “0.” 3. Erase all bits within the block to “1.” 4. Verify that all bits within the block are sufficiently erased. While the erase sequence is executing, bit 7 of the status register is a “0.” When the status register indicates that erasure is complete, check the Erase Status bit to verify that the erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status register will be set to a “1,” indicating an erase failure. If V PP was not within acceptable limits after the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead, SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a “1” to identify that V PP supply voltage was not within acceptable limits. After an erase operation, clear the Status Register (50H) before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, to prevent inadvertent status register reads, it is advisable to reset the flash to read array after the erase is complete.
3.2.5.1 Suspending and Resuming Erase
Since an erase operation requires on the order of seconds to complete, an Erase Suspend command is provided to allow erase-sequence interruption in order to read data from or program data to another block in memory. Once the erase sequence is started, writing the Erase Suspend command to the CUI requests that the WSM pause the erase sequence at a predetermined point in the erase algorithm. The status register will indicate if/when the erase operation has been suspended. A Read Array/Program command can now be written to the CUI in order to read/write data from/to blocks other than that which is suspended. The Program command can subsequently be suspended to read yet another array location. The only valid commands while erase is suspended are Erase Resume, Program, Program Resume, Read Array, or Read Status Register. During erase suspend mode, the chip can be placed in a pseudo-standby mode by taking CE# to V IH. This reduces active current consumption. Erase Resume continues the erase sequence when CE# = V IL. As with the end of a standard erase operation, the status register must be read and cleared before the next instruction is issued. 3.2.5.2 V PP Supply Voltage during Erase VPP supply voltage considerations are outlined in Section 3.4.
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Table 6. Command Bus Definitions
- Bus operations are defined in Table 3.
0 = 0 for manufacturer code, A0 = 1 for device code.
- Following the Intelligent Identifier command, two read operations access manufacturer and device codes.
- Either 40H or 10H command is valid.
- When writing commands to the device, the upper data bus [DQ
Table 7. Status Register Bit Definition checking Program or Erase Status bits. still unable to verify successful block erasure. but failed to program a word. device is returned to read status mode. be masked out when polling the Status Register.
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Repeat for subsequent programming operations. Write FFH after the last program operation to reset device to read array mode. attempts are allowed by the Write State Machine. in cases where multiple bytes are programmed before full status is checked. Figure 7. Automated Word Programming Flowchart
Figure 8. Program Suspend/Resume Flowchart
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Repeat for subsequent block erasures. Write FFH after the last write operation to reset device to read array mode. attempts are allowed by the Write State Machine. where multiple bytes are erased before full status is checked. Figure 9. Automated Block Erase Flowchart
Figure 10. Erase Suspend/Resume Flowchart
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3.3 Block Locking
blocks are programmed or erased as necessary. corresponding Status Register bit (SR.3) to be set.
3.3.2 WP# = V
3.3.3 WP# = V IH FOR BLOCK UNLOCKING
WP# = VIH unlocks all lockable blocks. These blocks can now be programmed or erased.
3.4 V PP Program and Erase
connected to 12V for a total of 80 hours maximum. Table 8. Write Protection Truth Table for
3.5 Power Consumption
and therefore, overall system power consumption.
3.5.1 ACTIVE POWER
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3.5.2 AUTOMATIC POWER SAVINGS (APS)
Automatic Power Savings provides low-power operation during active mode. Power Reduction Control (PRC) circuitry allows the flash to put itself into a low current state when not being accessed. After data is read from the memory array, PRC logic controls the device’s power consumption by entering the APS mode where typical I CC current is comparable to ICCS . The flash stays in this static state with outputs valid until a new location is read. APS reduces active current to standby current levels for 2.7V–3.6V CMOS input levels.
3.5.3 STANDBY POWER
With CE# at a logic-high level (VIH) and the CUI in read mode, the flash memory is in standby mode, which disables much of the device’s circuitry and substantially reduces power consumption. Outputs (DQ 0–DQ 15) are placed in a high-impedance state independent of the status of the OE# signal. If CE# transitions to a logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed. System engineers should analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. This will provide a more accurate measure of application-specific power and energy requirements.
3.5.4 DEEP POWER-DOWN MODE
The deep power-down mode of the Smart 3 Advanced Boot Block products switches the device into a low power savings mode, which is especially important for battery-based devices. This mode is activated when RP# = V IL (GND ± 0.2V). During read modes, RP# going low de-selects the memory and places the output drivers in a high impedance state. Recovery from the deep power- down state, requires a minimum time equal to t PHQV (see AC Characteristics table). During program or erase modes, RP# transitioning low will abort the operation, but the memory contents of the address being programmed or the block being erased are no longer valid as the data integrity has been compromised by the abort. During deep power-down, all internal circuits are switched to a low power savings mode (RP# transitioning to V IL or turning off power to the device clears the status register).
3.6 Power-Up/Down Operation
The device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required, since the device is indifferent as to which power supply, V PP or VCC , powers-up first.
3.6.1 RP# CONNECTED TO SYSTEM
The use of RP# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Intel recommends connecting RP# to the system CPU RESET# signal to allow proper CPU/flash initialization following system reset. System designers must guard against spurious writes when V CC voltages are above VLKO and VPP is active. Since both WE# and CE# must be low for a command write, driving either signal to V IH will inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabled until RP# is brought to V IH, regardless of the state of its control inputs. By holding the device in reset (RP# connected to system PowerGood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 3.6.2 V CC , VPP AND RP# TRANSITIONS The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its default state upon power-up, after exit from deep power-down mode or after V CC transitions above VLKO (Lockout voltage), is read array mode.
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After any program or block erase operation is complete (even after VPP transitions down to VPPLK ), the CUI must be reset to read array mode via the Read Array command if access to the flash memory array is desired. Refer to AP-617 Additional Flash Data Protection Using V PP , RP#, and WP# for a circuit-level description of how to implement the protection schemes discussed in Section 3.5.
3.7 Power Supply Decoupling
Flash memory’s power switching characteristics require careful device decoupling. System designers should consider three supply current issues: 1. Standby current levels (I CCS ) 2. Active current levels (ICCR ) 3. Transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between each V CC and GND, and between its VPP and GND. These high- frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads. 3.7.1 V PP TRACE ON PRINTED CIRCUIT BOARDS Designing for in-system writes to the flash memory requires special consideration of the VPP power supply trace by the printed circuit board designer. The V PP pin supplies the flash memory cells current for programming and erasing. VPP trace widths and layout should be similar to that of VCC . Adequate VPP supply traces, and decoupling capacitors placed adjacent to the component, will decrease spikes and overshoots.
4.0 ABSOLUTE MAXIMUM
- Minimum DC voltage is –0.5V on input/output pins.
- Maximum DC voltage on VPP may overshoot to +14.0V
- Output shorted for no more than one second. No more
than one output shorted at a time.
- V PP Program voltage is normally 2.7V–3.6V.
be connected to 12V for a total of 80 hours maximum. See Section 3.4 for details. Table 9. Temperature and Voltage Operating Conditions4
- See DC Characteristics tables for voltage range-specific specifications.
- The voltage swing on the inputs, V
IN is required to match VCCQ .
- Applying VPP = 11.4V–12.6V during a program/erase can only be done for a maximum of 1000 cycles on the main blocks
- V CC , VCCQ and VPP1 must share the same supply when all three are between 2.7V and 3.6V.
- For operating temperatures of –25°C– +85°C the device is projected to have a minimum block erase cycling of 10,000 to
30 PRELIMINARY
Table 10. DC Characteristics
Table 10. DC Characteristics (Continued)
32 PRELIMINARY
- All currents are in RMS unless otherwise noted. Typical values at nominal VCC , TA = +25°C.
- ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is sum of
ICCES and ICCR . If the device is read while in program suspend, current draw is the sum of ICCWA and ICCR .
- Erase and Program are inhibited when VPP < VPPLK and not guaranteed outside the valid VPP ranges of VPPH1 and VPPH2 .
- Sampled, not 100% tested.
- Automatic Power Savings (APS) reduces I
CCR to approximately standby levels in static operation (CMOS inputs).
- Applying VPP = 11.4V–12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks
- Includes the sum of VCC and VCCQ current.
Table 11. Capacitance (TA = 25°C, f = 1 MHz)
- Sampled, not 100% tested.
34 PRELIMINARY
Table 12. Temperature and VCC Operating Conditions
- See DC Characteristics tables for voltage range-specific specifications.
- For operating temperatures of –25°C– +85°C the device is projected to have a minimum block erase cycling of 10,000 to
- The voltage swing on the inputs, VIN is required to match VCCQ .
- V CC1 and VCCQ and (VPP1 or VPP3 )
- V CC2 and VCCQ and (VPP2 or VPP3 )
Wherever the input voltage VIN is mentioned, it is required that VIN matches the chosen VCCQ .
Table 13. DC Characteristics: VCCQ = 1.8V–2.2V
36 PRELIMINARY
Table 13. DC Characteristics: VCCQ = 1.8V–2.2V (Continued)
- All currents are in RMS unless otherwise noted. Typical values at nominal VCC , TA = +25°C.
- ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is ICCR . If the
device is read while in program suspend , current draw is ICCR .
- Erases and Writes inhibited when VPP < VPPLK , and not guaranteed outside the valid VPP ranges of VPPH1 ,VPPH2 . or VPPH3.
- Sampled, not 100% tested.
- Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs).
- Applying VPP = 11.4V–12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks
7 Includes the sum of VCC and VCCQ current
Table 14. Capacitance (TA = 25°C, f = 1 MHz)
- Sampled, not 100% tested.
38 PRELIMINARY
AC test inputs are driven at VCCQ for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at VCCQ /2. Input rise and fall times (10%–90%) <10 ns. For worst case speed conditions VCCQ = 1.8V. Figure 13. 1.8V—2.2V Input Range and Measurement Points See table for component values. Figure 14. Test Configuration C L includes jig capacitance.
7.0 AC CHARACTERISTICS
AC Characteristics are applicable to both VCCQ ranges. Table 15. AC Characteristics: Read Operations (Extended Temperature)
- See AC Input/Output Reference Waveform for timing measurements.
- OE# may be delayed up to t
ELQV –tGLQV after the falling edge of CE# without impact on tELQV .
- Sampled, but not 100% tested.
40 PRELIMINARY
Figure 15. AC Waveform: Read Operations
Table 16. AC Characteristics: Write Operations (Extended Temperature)1
- Read timing characteristics during program suspend and erase suspend are the same as during read-only operations.
Refer to AC Characteristics during read mode.
- Refer to command definition table for valid AIN (Table 6).
- Refer to command definition table for valid DIN (Table 6).
- Sampled, but not 100% tested.
- See Test Configuration (Figures 12 and 14),
- Time tLOCK is required for successful locking and unlocking of all lockable blocks.
42 PRELIMINARY
- CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading Status Register
A. V CC Power-Up and Standby. B. Write Program or Erase Setup Command. C. Write Valid Address and Data (for Program) or Erase Confirm Command. D. Automated Program or Erase Delay. E. Read Status Register Data (SRD): reflects completed program/erase operation. F. Write Read Array Command. Figure 16. AC Waveform: Program and Erase Operations
7.1 Reset Operations
Figure 17. AC Waveform: Deep Power-Down/Reset Operation
- If tPLPH is < 100 ns the device may still RESET but this is not guaranteed.
- If RP# is asserted while a block erase or word program operation is not executing, the reset will complete within 100 ns.
- Sampled, but not 100% tested.
44 PRELIMINARY
Table 17. Erase and Program Timings
- Typical values measured at TA = +25°C and nominal voltages.
- Excludes external system-level overhead.
- Sampled, but not 100% tested.
E SMART 3 ADVANCED BOOT BLOCK –WORD-WIDE 45PRELIMINARY APPENDIX A
ORDERING INFORMATION
T E 2 8 F 1 6 0 B 3 T 1 2 0 Package TE = 48-Lead TSOP GT = 48-Ball µBGA* CSP Product line designator for all Intel Flash products Access Speed (ns) (120, 150) Product Family B3 = Smart 3 Advanced Boot Block VCC = 2.7V - 3.6V VPP = 2.7V - 3.6V or 11.4V - 12.6V Device Density 160 = x16 (16 Mbit) 800 = x16 (8 Mbit) 400 = x 16 (4 Mbit) T = Top Blocking B = Bottom Blocking VALID COMBINATIONS 48-Lead TSOP 48-Ball µBGA* CSP Extended 16M TE28F160B3T120 GT28F160B3T120 TE28F160B3B120 GT28F160B3B120 TE28F160B3T150 GT28F160B3T150 TE28F160B3B150 GT28F160B3B150 Extended 8M TE28F800B3T120 GT28F800B3T120 TE28F800B3B120 GT28F800B3B120 TE28F800B3T150 GT28F800B3T150 TE28F800B3B150 GT28F800B3B150 Extended 4M TE28F400B3T120 GT28F400B3T120 TE28F400B3B120 GT28F400B3B120 TE28F400B3T150 GT28F400B3T150 TE28F400B3B150 GT28F400B3B150
SMART 3 ADVANCED BOOT BLOCK –WORD-WIDE E
46 PRELIMINARY
WRITE STATE MACHINE CURRENT/NEXT STATES Command Input (and Next State) Current State SR.7 Data When Read Read Array (FFH) Program Setup (40/10H) Erase Setup (20H) Erase Confirm (D0H) Program / Erase Susp. (B0H) Program / Erase Resume (D0) Read Status (70H) Clear Status (50H) Read ID (90H) Read Array “1” Array Read Array Program Setup Erase Setup Read Array Read Status Read Array Read Identifier Program Setup “1” Status Pgm. Program (Command input = Data to be programmed) Program (Not Comp.) “0” Status Program Pgm Susp. to Status Program Program (Complete) “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Read Identifier Program Suspend to Status “1” Status Prog. Susp. to Array Program Suspend to Array Program Program Susp. to Array Program Prog. Susp. to Status Program Suspend to Array Program Suspend to Array “1” Array Prog. Susp. to Array Program Suspend to Array Program Program Susp. to Array Program Prog. Susp. to Status Prog. Susp. to Array Prog. Susp. to Array Erase Setup “1” Status Erase Command Error Erase Erase Cmd. Err. Erase Erase Command Error Erase Cmd. Error “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Read Identifier Erase (Not Comp) “0” Status Erase Ers. Susp. to Status Erase Erase (Complete) “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Read Identifier Erase Suspend to Status “1” Status Erase Susp. to Array Program Setup Erase Susp. to Array Erase Erase Susp. to Array Erase Erase Susp. to Status Erase Suspend to Array Erase. Susp. to Array “1” Array Erase Susp. to Array Program Setup Erase Susp. to Array Erase Erase Susp. to Array Erase Erase Susp. to Status Erase Suspend to Array Read Status “1” Status Read Array Program Setup Erase Setup Read Array Read Status Read Array Read Identifier Read Identifier “1” ID Read Array Program Setup Erase Setup Read Array Read Status Read Array Read Identifier 1. You cannot program “1”s to the flash. Writing FFH following the Program Setup will initiate the internal program algorithm of the WSM. Although the algorithm will execute, array data is not changed. The WSM returns to read status mode without reporting any error. Assuming V PP > VPPLK writing a second FFH while in read status mode will return the flash to read array mode.
E SMART 3 ADVANCED BOOT BLOCK –WORD-WIDE 47PRELIMINARY APPENDIX C ACCESS TIME VS. CAPACITIVE LOAD (tAVQV vs. CL) Access Time vs. Load Capacitance Derating Curve 115 116 117 118 119 120 121 122 123 124 30 50 70 100 Load Capacitance(pF) Access Time(ns) Smart 3 Advanced Boot Block NOTE: VCCQ = 2.7V This chart shows a derating curve for device access time with respect to capacitive load. The value in the DC characteristics section of the specification corresponds to CL = 50 pF. NOTE: Sampled, but not 100% tested
SMART 3 ADVANCED BOOT BLOCK –WORD-WIDE E
48 PRELIMINARY
ARCHITECTURE BLOCK DIAGRAM Output Multiplexer 4-KWord Parameter Block 32-KWord Main Block 32-KWord Main Block 4-KWord Parameter Block Y-Gating/Sensing Write State Machine Program/Erase Voltage Switch Data Comparator Status Register Identifier Register Data Register I/O Logic Address Latch Address Counter X-Decoder Y-Decoder Power Reduction Control Input Buffer Output Buffer GND VCC VPP CE# WE# OE# RP# Command User Interface Input Buffer A0-A19 DQ 0-DQ15 VCCQ WP# 0580-20
E SMART 3 ADVANCED BOOT BLOCK –WORD-WIDE 49PRELIMINARY APPENDIX E ADDITIONAL INFORMATION (1,2) Order Number Document/Tool 210830 1997 Flash Memory Databook
290605 Smart 3 Advanced Boot Block Byte-Wide 8-Mbit (1024K x8), 16-Mbit
(2056K x 8) Flash Memory Family Datasheet
292172 AP-617 Additional Flash Data Protection Using VPP , RP# and WP#
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