28F256L18

28F640L18 INTEL | Alldatasheet

Document overview

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• PDF pages: 106

Technical content

Datasheet sections

• 1.0 Introduction
• 1.1 Nomenclature
• 1.2 Acronyms
• 1.3 Conventions
• 2.0 Functional Overview
• 3.0 Package Information
• 3.1 VF BGA Packages
• 3.2 SCSP Packages
• 4.0 Ballout and Signal Descriptions
• 4.1 Signal Ballout
• 4.1.1 VF BGA Package Ballout
• 4.1.2 SCSP Package Ballout
• 4.2 Signal Descriptions
• 4.2.1 VF BGA Package Signal Descriptions
• 4.3 Memory Map
• 5.0 Maximum Ratings and Operating Conditions
• 5.1 Absolute Maximum Ratings
• 5.2 Operating Conditions
• 6.0 Electrical Specifications
• 7.0 AC Characteristics
• 7.1 AC Test Conditions
• 7.2 Capacitance
• 7.6 AC Write Specifications
• 7.7 Program and Erase Characteristics
• 8.0 Power and Reset Specifications
• 8.1 Power Up and Down
• 8.2 Reset
• 8.3 Power Supply Decoupling
• 9.0 Device Operations
• 9.1 Bus Operations
• 9.1.2 Writes
• 9.1.3 Output Disable

Order Number: 251902, Revision: 009 April 2005 Intel StrataFlash® Wireless Memory (L18) 28F640L18, 28F128L18, 28F256L18 Datasheet Product Features The Intel StrataFlash® wireless memory (L18) device is the latest generation of Intel StrataFlash® memory devices featuring flexible, multiple-partition, dual operation. It provides high performance synchronous-burst read mode and asynchronous read mode using 1.8 V low- voltage, multi-level cell (MLC) technology. The multiple-partition architecture enables background programming or erasing to occur in one partition while code execution or data reads take place in another partition. This dual-operation architecture also allows a system to interleave code operations while program and erase operations take place in the background. The 8-Mbit or 16-Mbit partitions allow system designers to choose the size of the code and data segments. The L18 wireless memory device is manufactured using Intel 0.13 µm ETOX™ VIII process technology. It is available in industry- standard chip scale packaging. ■ High performance Read-While-Write/Erase — 85 ns initial access — 54 MHz with zero wait state, 14 ns clock-to- data output synchronous-burst mode — 25 ns asynchronous-page mode — 4-, 8-, 16-, and continuous-word burst mode — Burst suspend — Programmable WAIT configuration — Buffered Enhanced Factory Programming (BEFP) at 5 µs/byte (Typ) — 1.8 V low-power buffered programming at 7 µs/byte (Typ) ■ Architecture — Asymmetrically-blocked architecture — Multiple 8-Mbit partitions: 64-Mbit and 128- Mbit devices — Multiple 16-Mbit partitions: 256-Mbit devices — Four 16-Kword parameter blocks: top or bottom configurations — 64-Kword main blocks — Dual-operation: Read-While-Write (RWW) or Read-While-Erase (RWE) — Status Register for partition and device status ■ Power —V CC (core) = 1.7 V - 2.0 V — Standby current: 30 µA (Typ) for 256-Mbit — 4-Word synchronous read current: 15 mA (Typ) at 54 MHz — Automatic Power Savings mode ■ Security — OTP space:  64 unique factory device identifier bits  64 user-programmable OTP bits  Additional 2048 user-programmable OTP bits — Absolute write protection: V PP = GND — Power-transition erase/program lockout — Individual zero-latency block locking — Individual block lock-down ■ Software — 20 µs (Typ) program suspend — 20 µs (Typ) erase suspend — Intel® Flash Data Integrator optimized — Basic Command Set (BCS) and Extended Command Set (ECS) compatible — Common Flash Interface (CFI) capable ■ Quality and Reliability — Expanded temperature: –25° C to +85° C — Minimum 100,000 erase cycles per block — ETOX™ VIII process technology (0.13 µm) ■ Density and Packaging — 64-, 128-, and 256-Mbit density in VF BGA packages — 128/0 and 256/0 density in SCSP — 16-bit wide data bus

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Intel StrataFlash® Wireless Memory (L18) Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005 Order Number: 251902, Revision: 009 5

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Revision History

Revision Date Revision Description 10/15/02 -001 Initial Release 01/20/03 -002 Revised 256-Mbit Partition Size Revised 256-Mbit Memory Map Change WAIT function to de-assert during Asynchronous Operations (Asynchronous Reads and all Writes) Change WAIT function to active during Synchronous Non-Array Read Updated all Waveforms to reflect new WAIT function Revised Section 8.2.2 Added Synchronous Read to Write transition Section Improved 1.8 Volt I/O Bin 2 speed to 95ns from 105ns Added new AC specs: R15, R16, R17, R111, R311, R312, W21, and W22 Various text edits 04/11/03 -003 Added SCSP for 128/0 and 256/0 Ball-out and Mechanical Drawing 08/04/03 -004 Changed I CCS and ICCR values Added 256-Mbit AC Speed Changed Program and Erase Spec Combined the Buffered Programming Flow Chart and Read While Buffered programming Flow Chart Revised Read While Buffered Programming Flow Chart Revised Appendix A Write State Machine Revised CFI Table 21 CFI Identification Various text edits. 01/20/04 -005 Various text clarifications, various text edits , block locking state diagram clarification, synchronous read to write timing clarification, write to synchronous read timing clarification 05/22/04 -006 Minor text edits Changed Capacitance values Changed Standby Current (typ), Power Down Current (typ), Erase Suspend Current (typ), and Automatic Power Savings Current (typ) Updated Transient Equialent Testing Load Circuit

Intel StrataFlash® Wireless Memory (L18) Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005 Order Number: 251902, Revision: 009 7 09/02/04 -007 Added Table 7 “Bus Operations Summary” on page 45 Modified Table 32 “L18 SCSP Package Ordering Information” on page 105 and added the following order items: * RD48F2000L0YTQ0, RD48F2000L0YBQ0 * RD48F4000L0YTQ0, RD48F4000L0YBQ0 * PF48F3000L0YTQ0, PF48F3000L0YBQ0 * PF48F4000L0YTQ0, PF48F4000L0YBQ0 * NZ48F4000L0YTQ0, NZ48F4000L0YBQ0 * JZ48F4000LOYTQ0, JZ48F4000LOYBQ0 09/29/04 -008 Removed two mechanical drawings for 9x7.7x1.0 mm and 9x11x1.0 mm Added mechanical drawing Figure 4 “256-Mbit, 88-ball (80-active ball) SCSP Drawing and Dimen- sions (8x11x1.0 mm)” on page 15 In Table 32 “L18 SCSP Package Ordering Information” on page 105, corrected 256L18 package size from 8x10x1.2 mm to 8x11x1.2 mm 04/22/05 -009 Removed Bin 2 LC and Frequency Support Tables Added back VF BGA mechanical drawings Renamed 256-Mbit UT-SCSP to be 256-Mbit SCSP Updated Ordering Info Minor text edits Converted datasheet to new template In Table 4 “Bottom Parameter Memory Map” on page 24, corrected 256-Mbit Blk 131 address range from 100000 - 10FFFF to 800000 - 80FFFF In Section 5.1, “Absolute Maximum Ratings” on page 25, corrected Voltage on any signal (except VCC, VPP) from -0.5 V to +3.8 V to -0.5 V to +2.5 V In Section E.2, “Ordering Information for SCSP” on page 105, corrected package designators for leaded and lead-free packages from RD/PF to NZ/JZ

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Intel StrataFlash® Wireless Memory (L18) Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005 Order Number: 251902, Revision: 009 9

1.0 Introduction

This document provides information about the Intel StrataFlash® wireless memory device (L18). This document describes the device features, operation, and specifications.

1.1 Nomenclature

1.8 V: range of 1.7 V – 2.0 V (except where noted) 1.8 V Extended Range: range of 1.35 V – 2.0 V VPP = 9.0 V: VPP voltage range of 8.5 V – 9.5 V Block: A group of bits, bytes or words within the flash memory array that erase simultaneously when the Erase command is issued to the device. The Intel StrataFlash® Wireless Memory (L18) has two block sizes: 16-Kword, and 64-Kword. Main block: An array block that is usually used to store code and/or data. Main blocks are larger than parameter blocks. Parameter block: An array block that is usually used to store frequently changing data or small system parameters that traditionally would be stored in EEPROM. Top parameter device: Previously referred to as a top-boot device, a device with its parameter partition located at the highest physical address of its memory map. Parameter blocks within a parameter partition are located at the highest physical address of the parameter partition. Bottom parameter device: Previously referred to as a bottom-boot device, a device with its parameter partition located at the lowest physical address of its memory map. Parameter blocks within a parameter partition are located at the lowest physical address of the parameter partition. Partition: A group of blocks that share common program/erase circuitry. Blocks within a partition also share a common status register. If any block within a partition is being programmed or erased, only status register data (rather than array data) is available when any address within that partition is read. Main partition: A partition containing only main blocks. Parameter partition: A partition containing parameter blocks and main blocks.

1.2 Acronyms

CUI: Command User Interface MLC: Multi-Level Cell OTP: One-Time Programmable PLR: Protection Lock Register PR: Protection Register

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RCR: Read Configuration Register RFU: Reserved for Future Use SR: Status Register WSM: Write State Machine

1.3 Conventions

VCC: signal or voltage connection VCC: signal or voltage level 0x: hexadecimal number prefix 0b: binary number prefix SR[4]: Denotes an individual register bit. A[15:0]: Denotes a group of similarly named signals, such as address or data bus. A5: Denotes one element of a signal group membership, such as an address. bit: binary unit byte: eight bits word: two bytes, or sixteen bits Kbit: 1024 bits KByte: 1024 bytes KWord: 1024 words Mbit: 1,048,576 bits MByte: 1,048,576 bytes MWord: 1,048,576 words

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2.0 Functional Overview

The Intel StrataFlash® Wireless Memory (L18) provides read-while-write and read-while-erase capability with density upgrades through 256-Mbit. This family of devices provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage. Each device density contains one parameter partition and several main partitions. The flash memory array is grouped into multiple 8-Mbit or 16-Mbit partitions. By dividing the flash memory into partitions, program or erase operations can take place at the same time as read operations. Although each partition has write, erase, and burst read capabilities, simultaneous operation is limited to write or erase in one partition while other partitions are in read mode. The Intel StrataFlash® Wireless Memory (L18) allows burst reads that cross partition boundaries. User application code is responsible for ensuring that burst reads do not cross into a partition that is programming or erasing. Upon initial power up or return from reset, the device defaults to asynchronous page-mode read. Configuring the Read Configuration Register enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization. In addition to the enhanced architecture and interface, the Intel StrataFlash® Wireless Memory (L18) incorporates technology that enables fast factory program and erase operations. Designed for low-voltage systems, the Intel StrataFlash® Wireless Memory (L18) supports read operations with V CC at 1.8 volt, and erase and program operations with VPP at 1.8 V or 9.0 V . Buffered Enhanced Factory Programming (Buffered EFP) provides the fastest flash array programming performance with VPP at 9.0 volt, which increases factory throughput. With VPP at 1.8 V , VCC and VPP can be tied together for a simple, ultra-low power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP is less than VPPLK. A Command User Interface (CUI) is the interface between the system processor and all internal operations of the Intel StrataFlash® Wireless Memory (L18). An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and program. A Status Register indicates erase or program completion and any errors that may have occurred. An industry-standard command sequence invokes program and erase automation. Each erase operation erases one block. The Erase Suspend feature allows system software to pause an erase cycle to read or program data in another block. Program Suspend allows system software to pause programming to read other locations. Data is programmed in word increments. The Intel StrataFlash® Wireless Memory (L18) offers power savings through Automatic Power Savings (APS) mode and standby mode. The device automatically enters APS following read-cycle completion. Standby is initiated when the system deselects the device by deasserting CE# or by asserting RST#. Combined, these features can significantly reduce power consumption. The Intel StrataFlash® Wireless Memory (L18)’s protection register allows unique flash device identification that can be used to increase system security. Also, the individual Block Lock feature provides zero-latency block locking and unlocking.

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3.0 Package Information

3.1 VF BGA Packages

Figure 1. 64- and 128-Mbit, 56-Ball VF BGA Package Drawing and Dimensions

Figure 2. 256-Mbit, 79-Ball VF BGA Package Drawing and Dimensions

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3.2 SCSP Packages

Figure 3. 128-Mbit, 88-ball (80-active ball) SCSP Drawing and Dimensions (8x10x1.2 mm)

Figure 4. 256-Mbit, 88-ball (80-active ball) SCSP Drawing and Dimensions (8x11x1.0 mm)

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4.0 Ballout and Signal Descriptions

4.1 Signal Ballout

4.1.1 VF BGA Package Ballout

Figure 5. 7x8 Active-Ball Matrix for 64-, and 128-Mbit Densities in VF BGA Packages

densities). All ball locations are populated. Figure 6. 7x9 Active-Ball Matrix for 256-Mbit Density in VF BGA Package

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4.1.2 SCSP Package Ballout

Information, refer to Section 3.0, “Package Information” on page 12. Figure 7. 88-Ball (80-Active Ball) SCSP Package Ballout

4.2 Signal Descriptions

4.2.1 VF BGA Package Signal Descriptions

Table 1. Signal Descriptions (Sheet 1 of 2) A[MAX:0] Input ADDRESS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit: A[23:0]. CE# or OE# are deasserted. Data is internally latched during writes. the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. in standby, with DQ[15:0] and WAIT in High-Z. on the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first. cycles. OE#-high places the data outputs in High-Z and WAIT in High-Z. the device in asynchronous read array mode. is VOL or VOH when CE# and OE# are asserted. WAIT is high-Z if CE# or OE# is V IH.  In asynchronous page mode, and all write modes, WAIT is deasserted. blocks to be erased or programmed using software commands. VPPLmin to perform in-system program or erase. VPP may be 0 V during read operations. VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles. 9 V may derate flash performance/behavior.

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VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted. VSS Power Ground: Ground reference for device logic voltages. Connect to system ground. VSSQ Power Ground: Ground reference for device output voltages. Connect to system ground. other balls, and must be left floating. RFU — Reserved for Future Use: Reserved by Intel for future device functionality and enhancement. Table 1. Signal Descriptions (Sheet 2 of 2)

Table 2 describes the active signals used on the 128/0 and 256/0 SCSP. Table 2. Device Signal Descriptions for SCSP (Sheet 1 of 2) ADDRESS INPUTS: Inputs for all die addresses during read and write operations. F1-CE# selects the flash die. RFU. They each can be tied high to VCCQ through a 10K-ohm resistor for future design flexibility. Treat this signal as NC (No Connect) for this device. is reduced to standby levels. Treat this signal as NC (No Connect) for this device. output buffers, and places the flash outputs in High-Z. F1-OE# controls the outputs of the flash die. pulled high to VCCQ through a 10K-ohm re sistor for future design flexibility. disables the RAM output buffers, and places the selected RAM outputs in High-Z. Treat this signal as NC (No Connect) for this device. are latched on the rising edge of WE#. R-WE# Input RAM WRITE ENABLE: Low-true; R-WE# controls writes to the selected RAM die. Treat this signal as NC (No Connect) for this device.  In asynchronous page mode, and all write modes, WAIT is deasserted.

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down blocks to be unlocked with software commands. high order bytes on DQ[15:8], and R-LB#-low enabl es the RAM low-order bytes on DQ[7:0]. Treat this signal as NC (No Connect) for this device. RST# Input FLASH RESET: Low-true; RST#-low initializes flash inte rnal circuitry and disables flash operations. RST#-high enables flash operation. Exit from reset places the flash in asynchronous read array mode. Treat this signal as NC (No Connect) for this device. VPPLmin to perform in-system flash modification. VPP may be 0 V during read operations. this pin at 9 V may reduce block cycling capability. VPEN (Erase/Program/Block Lock Enables) is not available for L18 products. invalid VCC voltages should not be attempted. S-VCC Power SRAM Power Supply: Supplies power for SRAM operations. Treat this signal as NC (No Connect) for this device. P-VCC Power PSRAM Power Supply: Supplies power for PSRAM operations. Treat this signal as NC (No Connect) for this device. VCCQ Power Flash I/O Power: Supply power for the input and output buffers. VSS Power Ground: Connect to system ground. Do not float any VSS connection. DU — Do Not Use: Do not connect to any other signal, or power supply; must be left floating. NC — No Connect: No internal connection; can be driven or floated. Table 2. Device Signal Descriptions for SCSP (Sheet 2 of 2)

4.3 Memory Map

Table 3. Top Parameter Memory Map

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Table 4. Bottom Parameter Memory Map

Intel StrataFlash® Wireless Memory (L18) Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005 Order Number: 251902, Revision: 009 25

5.0 Maximum Ratings and Operating Conditions

5.1 Absolute Maximum Ratings

Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only.

5.2 Operating Conditions

Warning: Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. Parameter Maximum Rating Notes Temperature under bias –25 °C to +85 °C Storage temperature –65 °C to +125 °C Voltage on any signal (except VCC, VPP) –0.5 V to +2.5 V 1 VPP voltage –0.2 V to +10 V 1,2,3 VCC voltage –0.2 V to +2.5 V 1 VCCQ voltage –0.2 V to +2.5 V 1 Output short circuit current 100 mA 4 Notes: 1. Voltages shown are spec ified with respect to V SS. Minimum DC voltage is –0.5 V on input/output signals and –0.2 V on VCC, VCCQ, and VPP. During transitions, this level may undershoot to –2.0 V for periods < 20 ns. Maximum DC voltage on VCC is VCC +0.5 V, which, during transitions, may overshoot to VCC +2.0 V for periods < 20 ns. Maximum DC voltage on input/output signals and V CCQ is VCCQ +0.5 V, which, during transitions, may overshoot to VCCQ +2.0 V for periods < 20 ns. 2. Maximum DC voltage on V PP may overshoot to +14.0 V for periods < 20 ns. any blocks for 1000 cycles maximum. 9.0 V program/erase voltage may reduce block cycling capability. 4. Output shorted for no more than one second. No more than one output shorted at a time. Symbol Parameter Min Max Units Notes T C Operating Temperature –25 +85 °C 1 VCC VCC Supply Voltage 1.7 2.0 VVCCQ I/O Supply Voltage 1.8 V Range 1.7 2.0 1.8 V Extended Range 1.35 2.0 VPPL VPP Voltage Supply (Logic Level) 0.9 2.0 VPPH Factory word programming VPP 8.5 9.5 tPPH Maximum VPP Hours V PP = VPPH - 80 Hours Block Erase Cycles Main and Parameter Blocks V PP = VCC 100,000 - CyclesMain Blocks V PP = VPPH - 1000 Parameter Blocks V PP = VPPH - 2500 Notes: 1. T C = Case temperature 2. In typical operation, the VPP program voltage is V PPL. VPP can be connected to 8.5 V – 9.5 V for 1000 cycles on main blocks and 2500 cycles on parameter blocks.

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6.0 Electrical Specifications

6.1 DC Current Characteristics

1.7 V – 2.0 V 1.35 V - 2.0 V Unit Test Conditions Notes Typ Max ILI Input Load Current - ±1 µA VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or VSS 1 ILO Output Leakage Current DQ[15:0], WAIT - ±1 µA V CC = VCCMax VCCQ = VCCQMax VIN = VCCQ or VSS ICCS ICCD VCC Standby, Power Down 64-Mbit 15 30 µA VCC = VCCMax VCCQ = VCCQMax CE# = VCCQ RST# = VCCQ (for ICCS) RST# = GND (for ICCD) WP# = VIH 1,2 128-Mbit 20 70 256-Mbit 25 110 ICCAPS APS 64-Mbit 15 30 µA VCC = VCCMax VCCQ = VCCQMax CE# = VSSQ RST# = VCCQ All inputs are at rail to rail (VCCQ or VSSQ). 128-Mbit 20 70 256-Mbit 25 110 ICCR Average VCC Read Current Asynchronous Single-Word f = 5MHz (1 CLK) 13 15 mA VCC = VCCMax CE# = VIL OE# = VIH Inputs: VIL or VIH Page-Mode Read f = 13 MHz (5 CLK) 8 9 mA 4-Word Read Synchronous Burst Read f = 40MHz, LC = 3 12 16 mA Burst length = 4 14 18 mA Burst length = 8 16 20 mA Burst length = 16 20 25 mA Burst length = Continuous Synchronous Burst Read f = 54MHz, LC = 4 15 18 mA Burst length = 4 18 22 mA Burst length = 8 21 25 mA Burst length = 16 22 27 mA Burst Length = Continuous I CCW, ICCE VCC Program Current, VCC Erase Current 35 50 mA VPP = VPPL, program/erase in progress 1,3,4, 25 32 mA VPP = VPPH, program/erase in progress 1,3,5, ICCWS, ICCES VCC Program Suspend Current, VCC Erase Suspend Current 64-Mbit 15 30 µA CE# = V CCQ; suspend in progress 1,6,3128-Mbit 20 70 256-Mbit 25 110 IPPS, IPPWS, IPPES VPP Standby Current, VPP Program Suspend Current, VPP Erase Suspend Current 0.2 5 µA V PP = VPPL, suspend in progress 1,3

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6.2 DC Voltage Characteristics

IPPR VPP Read 2 15 µA V PP ≤ VCC 1,3IPPW VPP Program Current 0.05 0.10 mA VPP = VPPL, program in progress 82 2 V PP = VPPH, program in progress IPPE VPP Erase Current 0.05 0.10 mA VPP = VPPL, erase in progress 82 2 V PP = VPPH, erase in progress Notes: 1. All currents are RMS unless noted. Typical values at typical V CC, TC = +25°C. 2. I CCS is the average current measured over any 5 ms time interval 5 µs after CE# is deasserted. 3. Sampled, not 100% tested. 4. V CC read + program current is the sum of V CC read and VCC program currents. 5. V CC read + erase current is the sum of V CC read and VCC erase currents. 6. I CCES is specified with the device deselected. If dev ice is read while in erase suspend, current is I CCES plus ICCR 7. I CCW, ICCE measured over typical or max times specified in Section 7.7, “Program and Erase Characteristics” on page 41 Sym Parameter VCCQ 1.35 V – 2.0 V 1.7 V – 2.0 V Unit Test Condition Notes Min Max Min Max VIL Input Low Voltage 0 0.2 0 0.4 V 1 VIH Input High Voltage V CCQ – 0.2 V CCQ VCCQ – 0.4 V CCQ V1 VOL Output Low Voltage - 0.1 - 0.1 V VCC = VCCMin VCCQ = VCCQMin IOL = 100 µA VOH Output High Voltage V CCQ – 0.1 - V CCQ – 0.1 - V VCC = VCCMin VCCQ = VCCQMin IOH = –100 µA VPPLK VPP Lock-Out Voltage - 0.4 - 0.4 V 2 VLKO VCC Lock Voltage 1.0 - 1.0 - V VLKOQ VCCQ Lock Voltage 0.9 - 0.9 - V NOTES: 1. V IL can undershoot to –0.4 V and V IH can overshoot to VCCQ + 0.4 V for durations of 20 ns or less. 2. V PP ≤ VPPLK inhibits erase and program operations. Do not use VPPL and VPPH outside their valid ranges. Sym Parameter VCCQ 1.7 V – 2.0 V 1.35 V - 2.0 V Unit Test Conditions Notes Typ Max

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7.0 AC Characteristics

7.1 AC Test Conditions

at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed occurs at V CC = VCCMin.

1. See the following table for component values.
2. Test configuration component value for worst case speed conditions.

Figure 8. AC Input/Output Reference Waveform Figure 9. Transient Equivalent Testing Load Circuit Table 5. Test configuration component value for worst case speed conditions

1.35 V Standard Test 30

1.7 V Standard Test 30

7.2 Capacitance

Figure 10. Clock Input AC Waveform Table 6. Capacitance

1. Sampled, not 100% tested.
2. Silicon die capacitance only, add 1 pF for discrete packages.

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7.3 AC Read Specifications (V CCQ = 1.35 V – 2.0 V) Num Symbol Parameter All DensitiesSpeed –90 Units Notes Min Max Asynchronous Specifications R1 t AVAV Read cycle time 90 - ns 6R2 tAVQV Address to output valid - 90 ns R3 tELQV CE# low to output valid - 90 ns R4 tGLQV OE# low to output valid - 25 ns 1,2 R5 t PHQV RST# high to output valid - 150 ns 1 R6 t ELQX CE# low to output in low-Z 0 - ns 1,3 R7 t GLQX OE# low to output in low-Z 0 - ns 1,2,3 R8 t EHQZ CE# high to output in high-Z - 20 ns 1,3R9 t GHQZ OE# high to output in high-Z - 20 ns R10 t OH Output hold from first occurring address, CE#, or OE# change 0 - ns R11 t EHEL CE# pulse width high 17 - ns 1 R12 t ELTV CE# low to WAIT valid - 17 ns 1 R13 t EHTZ CE# high to WAIT high Z - 17 ns 1,3 R15 t GLTV OE# low to WAIT valid - 17 ns 1 R16 tGLTX OE# low to WAIT in low-Z 0 - ns 1,3 R17 tGHTZ OE# high to WAIT in high-Z - 20 ns 1,3 Latching Specifications R101 t AVVH Address setup to ADV# high 7 - ns R102 t ELVH CE# low to ADV# high 10 - ns R103 t VLQV ADV# low to output valid - 90 ns R104 t VLVH ADV# pulse width low 7 - ns R105 t VHVL ADV# pulse width high 7 - ns R106 t VHAX Address hold from ADV# high 7 - ns 1,4 R108 t APA Page address access - 30 ns 1 R111 tphvh RST# high to ADV# high 30 - ns 1 Clock Specifications R200 f CLK CLK frequency - 47 MHz 1,3R201 t CLK CLK period 21.3 - ns R202 t CH/CL CLK high/low time 4.5 - ns R203 t FCLK/RCLK CLK fall/rise time - 3 ns Synchronous Specifications R301 t AVCH/L Address setup to CLK 7 - ns 1R302 t VLCH/L ADV# low setup to CLK 7 - ns R303 t ELCH/L CE# low setup to CLK 7 - ns R304 t CHQV / tCLQV CLK to output valid - 17 ns R305 t CHQX Output hold from CLK 3 - ns 1,5 R306 t CHAX Address hold from CLK 7 - ns 1,4,5 R307 t CHTV CLK to WAIT valid - 17 ns 1,5 R311 t CHVL CLK Valid to ADV# Setup 0 - ns 1 R312 t CHTX WAIT Hold from CLK 3 - ns 1,5 NOTES: 1. See Figure 8, “AC Input/Output Reference Waveform” on page 28 for timing measurements and max allowable input slew rate. 2. OE# may be delayed by up to t ELQV – tGLQV after CE#’s falling edge without impact to tELQV. 3. Sampled, not 100% tested. 4. Address hold in synchronous burst mode is t CHAX or tVHAX, whichever timing specification is satisfied first. 5. Applies only to subsequent synchronous reads. 6. The specifications in this table will only be used by customers (1) who desire a 1.35 to 2.0 V CCQ operating range OR (2) who desire to transition their host controller from a 1.7 V to 2.0 V V CCQ voltage now to a lower range in the future.

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7.4 AC Read Specifications for 64-Mbit and 128-Mbit Densities

(VCCQ = 1.7 V – 2.0 V) Num Symbol Parameter Speed –85 Units Notes Min Max Asynchronous Specifications R1 t AVAV Read cycle time 85 - ns 6R2 tAVQV Address to output valid - 85 ns R3 tELQV CE# low to output valid - 85 ns R4 tGLQV OE# low to output valid - 20 ns 1,2 R5 t PHQV RST# high to output valid - 150 ns 1 R6 t ELQX CE# low to output in low-Z 0 - ns 1,3 R7 t GLQX OE# low to output in low-Z 0 - ns 1,2,3 R8 t EHQZ CE# high to output in high-Z - 17 ns 1,3R9 t GHQZ OE# high to output in high-Z - 17 ns R10 t OH Output hold from first occurring address, CE#, or OE# change 0 - ns R11 t EHEL CE# pulse width high 14 - ns 1 R12 t ELTV CE# low to WAIT valid - 14 ns 1 R13 t EHTZ CE# high to WAIT high Z - 14 ns 1,3 R15 t GLTV OE# low to WAIT valid - 14 ns 1 R16 tGLTX OE# low to WAIT in low-Z 0 - ns 1,3 R17 tGHTZ OE# high to WAIT in high-Z - 17 ns 1,3 Latching Specifications R101 t AVVH Address setup to ADV# high 7 - ns 1R102 t ELVH CE# low to ADV# high 10 - ns R103 t VLQV ADV# low to output valid - 85 ns 1,6 R104 t VLVH ADV# pulse width low 7 - ns 1R105 t VHVL ADV# pulse width high 7 - ns R106 t VHAX Address hold from ADV# high 7 - ns 1,4 R108 t APA Page address access - 25 ns 1 R111 t phvh RST# high to ADV# high 30 - ns 1 Clock Specifications R200 f CLK CLK frequency - 54 MHz 1,3R201 t CLK CLK period 18.5 - ns R202 t CH/CL CLK high/low time 3.5 - ns R203 t FCLK/RCLK CLK fall/rise time - 3 ns Synchronous Specifications R301 t AVCH/L Address setup to CLK 7 - ns 1R302 t VLCH/L ADV# low setup to CLK 7 - ns R303 t ELCH/L CE# low setup to CLK 7 - ns R304 t CHQV / tCLQV CLK to output valid - 14 ns R305 t CHQX Output hold from CLK 3 - ns 1,5 R306 t CHAX Address hold from CLK 7 - ns 1,4,5 R307 t CHTV CLK to WAIT valid - 14 ns 1,5 R311 t CHVL CLK Valid to ADV# Setup 0 - ns 1 R312 t CHTX WAIT Hold from CLK 3 - ns 1,5 NOTES: 1. See Figure 8, “AC Input/Output Reference Waveform” on page 28 for timing measurements and maximum allowable input slew rate. 2. OE# may be delayed by up to t ELQV – tGLQV after CE#’s falling edge without impact to tELQV. 3. Sampled, not 100% tested. 4. Address hold in sync hronous burst mode is t CHAX or tVHAX, whichever timing specification is satisfied first. 5. Applies only to subsequent synchronous reads. 6. The specifications in Section 7.3 will only be used by customers (1) who desire a 1.35 to 2.0 V CCQ operating range OR (2) who desire to transition their host controller from a 1.7 V to 2.0 V V CCQ voltage now to a lower range in the future.

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7.5 AC Read Specifications for 256-Mbit Density (V CCQ = 1.7 V – 2.0 V) Num Symbol Parameter Speed –85 Units Notes Min Max Asynchronous Specifications R1 t AVAV Read cycle time VCC = VCCQ = 1.8 V – 2.0 V 85 - ns VCC = VCCQ = 1.7 V – 2.0 V 88 - R2 tAVQV Address to output valid VCC = VCCQ = 1.8 V – 2.0 V -8 5 ns VCC = VCCQ = 1.7 V – 2.0 V -8 8 R3 tELQV CE# low to output valid VCC = VCCQ = 1.8 V – 2.0 V -8 5 ns VCC = VCCQ = 1.7 V – 2.0 V -8 8 R4 tGLQV OE# low to output valid - 20 ns 1,2 R5 t PHQV RST# high to output valid - 150 ns 1 R6 t ELQX CE# low to output in low-Z 0 - ns 1,3 R7 t GLQX OE# low to output in low-Z 0 - ns 1,2,3 R8 t EHQZ CE# high to output in high-Z - 17 ns 1,3R9 t GHQZ OE# high to output in high-Z - 17 ns R10 t OH Output hold from first occurring address, CE#, or OE# change 0 - ns R11 t EHEL CE# pulse width high 14 - ns 1 R12 t ELTV CE# low to WAIT valid - 14 ns 1 R13 t EHTZ CE# high to WAIT high Z - 14 ns 1,3 R15 t GLTV OE# low to WAIT valid - 14 ns 1 R16 tGLTX OE# low to WAIT in low-Z 0 - ns 1,3 R17 tGHTZ OE# high to WAIT in high-Z - 17 ns 1,3 Latching Specifications R101 t AVVH Address setup to ADV# high 7 - ns 1R102 t ELVH CE# low to ADV# high 10 - ns R103 t VLQV ADV# low to output valid VCC = VCCQ = 1.8 V – 2.0 -8 5 ns 1,6 VCC = VCCQ = 1.7 V – 2.0 -8 8 R104 t VLVH ADV# pulse width low 7 - ns 1R105 t VHVL ADV# pulse width high 7 - ns R106 t VHAX Address hold from ADV# high 7 - ns 1,4 R108 t APA Page address access - 25 ns 1 R111 t phvh RST# high to ADV# high 30 - ns 1 Clock Specifications R200 f CLK CLK frequency - 54 MHz 1,3R201 t CLK CLK period 18.5 - ns R202 t CH/CL CLK high/low time 3.5 - ns R203 t FCLK/RCLK CLK fall/rise time - 3 ns Synchronous Specifications R301 t AVCH/L Address setup to CLK 7 - ns 1R302 t VLCH/L ADV# low setup to CLK 7 - ns R303 t ELCH/L CE# low setup to CLK 7 - ns R304 t CHQV / tCLQV CLK to output valid - 14 ns R305 t CHQX Output hold from CLK 3 - ns 1,5 R306 t CHAX Address hold from CLK 7 - ns 1,4,5 R307 t CHTV CLK to WAIT valid - 14 ns 1,5

Note: WAIT shown deasserted during asynchronous r ead mode (RCR[10]=0 Wait asserted low).

1. See Figure 8, “AC Input/Output Reference Waveform” on page 28 for timing measurements and max allowable input slew
2. OE# may be delayed by up to t ELQV – tGLQV after CE#’s falling edge without impact to tELQV.
3. Sampled, not 100% tested.
4. Address hold in sync hronous burst mode is t

CHAX or tVHAX, whichever timing specification is satisfied first.

1. Applies only to subsequent synchronous reads.
2. The specifications in Section 7.3 will only be used by customers (1) who desire a 1.35 to 2.0 V

(2) who desire to transition their host controller from a 1.7 V to 2.0 V V CCQ voltage now to a lower range in the future. Figure 11. Asynchronous Single-Word Read with ADV# Low

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Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0 Wait asserted low). Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0 Wait asserted low). Figure 12. Asynchronous Single-Word Read with ADV# Latch Figure 13. Asynchronous Page-Mode Read Timing

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initial latency and deasserted during valid data (RCR[10] = 0 Wait asserted low).

1. CLK can be stopped in either high or low state.
2. WAIT is driven per OE# assertion during synchr onous array or non-array read. WAIT asserted during

initial latency and deasserted during valid data (RCR[10] = 0 Wait asserted low). Figure 16. Synchronous Burst-Mode Four-Word Read Timing Figure 17. Burst Suspend Timing

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7.6 AC Write Specifications

Nbr. Symbol Parameter (1, 2) Min Max Units Notes W1 t PHWL RST# high recovery to WE# low 150 - ns 1,2,3 W2 t ELWL CE# setup to WE# low 0 - ns 1,2,3 W3 t WLWH WE# write pulse width low 50 - ns 1,2,4 W4 t DVWH Data setup to WE# high 50 - ns 1,2 W5 t AVWH Address setup to WE# high 50 - ns W6 t WHEH CE# hold from WE# high 0 - ns W7 t WHDX Data hold from WE# high 0 - ns W8 t WHAX Address hold from WE# high 0 - ns W9 t WHWL WE# pulse width high 20 - ns 1,2,5 W10 t VPWH V PP setup to WE# high 200 - ns 1,2,3,7 W11 t QVVL VPP hold from Status read 0 - ns W12 t QVBL WP# hold from Status read 0 - ns 1,2,3,7 W13 t BHWH WP# setup to WE# high 200 - ns W14 t WHGL WE# high to OE# low 0 - ns 1,2,9 W16 t WHQV WE# high to read valid t AVQV + 35 - ns 1,2,3,6,10 Write to Asynchronous Read Specifications W18 t WHAV WE# high to Address valid 0 - ns 1,2,3,6 Write to Synchronous Read Specifications W19 t WHCH/L WE# high to Clock valid 19 - ns 1,2,3,6,10 W20 t WHVH WE# high to ADV# high 19 - ns Write Specifications with Clock Active W21 t VHWL ADV# high to WE# low - 20 ns 1,2,3,11 W22 t CHWL Clock high to WE# low - 20 ns Notes: 1. Write timing characteristics during erase su spend are the same as write-only operations. 2. A write operation can be terminated with either CE# or WE#. 3. Sampled, not 100% tested. 4. Write pulse width low (t WLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high (whichever occurs first). Hence, t WLWH = tELEH = tWLEH = tELWH. 5. Write pulse width high (t WHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low (whichever occurs last). Hence, t WHWL = tEHEL = tWHEL = tEHWL). 6. t WHVH or tWHCH/L must be met when transitioning from a write cycle to a synchronous burst read. 7. V PP and WP# should be at a valid level until eras e or program success is determined. 8. This specification is only applicable when transiti oning from a write cycle to an asynchronous read. See spec W19 and W20 for synchronous read. 9. When doing a Read Status operation following any command that alters the Status Register, W14 is 20 ns. 10. Add 10ns if the write operations results in a RCR or block lock status change, for the subsequent read operation to reflect this change. 11. These specs are required only when the device is in a synchronous mode and clock is active during address setup phase.

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Figure 18. Write to Write Timing Figure 19. Asynchronous Read to Write Timing

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Figure 22. Write to Synchronous Read Timing

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7.7 Program and Erase Characteristics

Nbr. Symbol Parameter VPPL VPPH Units Notes Min Typ Max Min Typ Max Conventional Word Programming W200 t PROG/W Program Time Single word - 90 180 - 85 170 µs 1Single cell - 30 60 - 30 60 Buffered Programming W200 t PROG/W Program Time Single word - 90 180 - 85 170 µs 1W201 t PROG/PB One Buffer (32 words) - 440 880 - 340 680 Buffered Enhanced Factory Programming W451 t BEFP/W Program Single word n/a n/a n/a - 10 - µs 1,2 W452 tBEFP/ Setup Buffered EFP Setup n/a n/a n/a 5 - - 1 Erasing and Suspending W500 t ERS/PB Erase Time 16-Kword Parameter - 0.4 2.5 - 0.4 2.5 s 1W501 t ERS/MB 64-Kword Main - 1.2 4 - 1.0 4 W600 t SUSP/P Suspend Latency Program suspend - 20 25 - 20 25 µsW601 t SUSP/E Erase suspend - 20 25 - 20 25 Notes: 1. Typical values measured at T C = +25 °C and nominal voltages. Performance numbers are valid for all speed versions. Excludes system overhead. Sampled, but not 100% tested. 2. Averaged over entire device.

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8.0 Power and Reset Specifications

8.1 Power Up and Down

Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; If VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCMIN before applying VCCQ and VPP. Device inputs should not be driven before supply voltage equals VCCMIN. Power supply transitions should only occur when RST# is low. This protects the device from accidental programming or erasure during power transitions.

8.2 Reset

Asserting RST# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected. Connect RST# to the same active-low reset signal used for CPU initialization. Also, because the device is disabled when RST# is asserted, it ignores its control inputs during power-up/down. Invalid bus conditions are masked, providing a level of memory protection. System designers should guard against spurious writes when V CC voltages are above VLKO. Because both WE# and CE# must be asserted for a write operation, deasserting either signal inhibits writes to the device. The Command User Interface (CUI) architecture provides additional protection because alteration of memory contents can only occur after successful completion of a two-step command sequence (see Section 9.2, “Device Commands” on page 47). Nbr. Symbol Parameter Min Max Unit Notes P1 t PLPH RST# pulse width low 100 - ns 1,2,3,4 P2 t PLRH RST# low to device reset during erase - 25 µs 1,3,4,7 RST# low to device reset during program - 25 1,3,4,7 P3 t VCCPH VCC Power valid to RST# deassertion (high) 60 - 1,4,5,6 Notes: 1. These specifications are valid for al l device versions (packages and speeds). 2. The device may reset if t PLPH is < tPLPHmin, but this is not guaranteed. 3. Not applicable if RST# is tied to Vcc. 4. Sampled, but not 100% tested. 5. If RST# is tied to the V CC supply, device will not be ready until tVCCPH after VCC ≥ VCC min. 6. If RST# is tied to any supply/signal with V CCQ voltage levels, the RST# input voltage must not exceed VCC until VCC ≥ VCC(min). 7. Reset completes within t PLPH if RST# is asserted while no erase or program operation is executing.

8.3 Power Supply Decoupling

produced when CE# and OE# are asserted and deasserted. placed as close as possible to package leads. voltage droop caused by PCB trace inductance. Figure 23. Reset Operation Waveforms

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8.4 Automatic Power Saving

Automatic Power Saving (APS) provides low power operation during a read’s active state. ICCAPS is the average current measured over any 5 ms time interval, 5 µs after CE# is deasserted. During APS, average current is measured over the same time interval 5 µs after the following events happen: (1) there is no internal read, program or erase operations cease; (2) CE# is asserted; (3) the address lines are quiescent and at VSSQ or VCCQ. OE# may also be driven during APS.

9.0 Device Operations

Machine (WSM) manages all block-erase and word-program algorithms. through which the flash device is controlled.

9.1 Bus Operations

address inputs to determine the accessed partition. ADV#-low opens the internal address latches. OE#-low activates the outputs and gates selected data onto the I/O bus. Table 7. Bus Operations Summary

1. Refer to the Table 8, “Command Bus Cycles” on page 47 for valid DQ[15:0] during a write operation.

SS ± 0.2 V to meet the maximum specified power-down current.

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9.1.1 Reads

To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted. CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus. See Section 10.0, “Read Operations” on page 50 for details on the available read modes, and see Section 15.0, “Special Read States” on page 75 for details regarding the available read states. The Automatic Power Savings (APS) feature provides low power operation following reads during active mode. After data is read from the memory array and the address lines are quiescent, APS automatically places the device into standby. In APS, device current is reduced to ICCAPS (see Section 6.1, “DC Current Characteristics” on page 26).

9.1.2 Writes

To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted. During a write operation, address and data are latched on the rising edge of WE# or CE#, whichever occurs first. Table 8, “Command Bus Cycles” on page 47 shows the bus cycle sequence for each of the supported device commands, while Table 9, “Command Codes and Definitions” on page 48 describes each command. See Section 7.0, “AC Characteristics” on page 28 for signal- timing details. Note: Write operations with invalid VCC and/or VPP voltages can produce spurious results and should not be attempted.

9.1.3 Output Disable

When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-impedance (High-Z) state, WAIT is also placed in High-Z.

9.1.4 Standby

When CE# is deasserted the device is deselected and placed in standby, substantially reducing power consumption. In standby, the data outputs are placed in High-Z, independent of the level placed on OE#. Standby current, ICCS, is the average current measured over any 5 ms time interval, 5 µs after CE# is deasserted. During standby, average current is measured over the same time interval 5 µs after CE# is deasserted. When the device is deselected (while CE# is deasserted) during a program or erase operation, it continues to consume active power until the program or erase operation is completed.

9.1.5 Reset

As with any automated device, it is important to assert RST# when the system is reset. When the system comes out of reset, the system processor attempts to read from the flash memory if it is the system boot device. If a CPU reset occurs with no flash memory reset, improper CPU initialization may occur because the flash memory may be providing status information rather than array data. Flash memory devices from Intel allow proper CPU initialization following a system reset through the use of the RST# input. RST# should be controlled by the same low-true reset signal that resets the system CPU.

device is reset to asynchronous Read Array state. because the data may have been only partially written or erased. Characteristics” on page 28 for details about signal-timing.

9.2 Device Commands

Interface (CUI). See Table 8, “Command Bus Cycles” on page 47. either asserting RST# or by issuing an appropriate suspend command. Table 8. Command Bus Cycles (Sheet 1 of 2)

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9.3 Command Definitions

Valid device command codes and descriptions are shown in Table 9.

1. First command cycle address should be the same as the operation’s target address.

PnA = Address within the partition. PBA = Partition base address. IA = Identification code address offset. QA = CFI Query address offset. BA = Address within the block. WA = Word address of memory location to be written. PRA = Protection Register address. LRA = Lock Register address. X = Any valid address within the device. QD = Query data on DQ[15:0]. N = Word count of data to be loaded into the write buffer. PD = Protection Register data. PD = Protection Register data. RCD = Read Configuration Register data on A[15:0]. A[MAX:16] can select any partition .

1. The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This
2. The confirm command (0xD0) is followed by the buffer data.

Table 8. Command Bus Cycles (Sheet 2 of 2) Table 9. Command Codes and Definitions (Sheet 1 of 2) 0xFF Read Array Places the addressed partition in Read Array mode. Array data is output on DQ[15:0]. data, Block Lock status, or Protection Register data on DQ[15:0]. addresses output Common Flash Interface information on DQ[7:0]. used to clear the SR error bits.

First cycle of a 2-cycle programming command; prepares the CUI for a write operation. Equivalent to the Word Program Setup command, 0x40. The confirm command is Issued after the data streaming for writing into the buffer is done. the buffer to the flash memory array. and data, and prepares the device for Buffered EFP mode. toggled to update the Status Register Data for synchronous Non-array read. mode regardless of control signal states (except for RST# asserted). First cycle of a 2-cycle command; prepares the CUI for block lock configuration changes. 0x01 Lock Block If the previous command was Block Lock Setup (0x60), the addressed block is locked. 0xD0 Unlock Block If the previous command was Block Lock Set up (0x60), the addressed block is unlocked. If the addressed block is in a lock-down state, the operation has no effect. starts the programming algorithm. Status Register bits SR[4] and SR[5], indicating a command sequence error. Read Configuration Register command, subsequent read operations access array data. Table 9. Command Codes and Definitions (Sheet 2 of 2)

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10.0 Read Operations

The device supports two read modes: asynchronous page mode and synchronous burst mode. Asynchronous page mode is the default read mode after device power-up or a reset. The Read Configuration Register must be configured to enable synchronous burst reads of the flash memory array (see Section 10.3, “Read Configuration Register (RCR)” on page 51). Each partition of the device can be in any of four read states: Read Array, Read Identifier, Read Status or Read Query. Upon power-up, or after a reset, all partitions of the device default to Read Array. To change a partition’s read state, the appropriate read command must be written to the device (see Section 9.2, “Device Commands” on page 47). See Section 15.0, “Special Read States” on page 75 for details regarding Read Status, Read ID, and CFI Query modes. The following sections describe read-mode operations in detail.

10.1 Asynchronous Page-Mode Read

Following a device power-up or reset, asynchronous page mode is the default read mode and all partitions are set to Read Array. However, to perform array reads after any other device operation (e.g. write operation), the Read Array command must be issued in order to read from the flash memory array. Note: Asynchronous page-mode reads can only be performed when Read Configuration Register bit RCR[15] is set (see Section 10.3, “Read Configuration Register (RCR)” on page 51). To perform an asynchronous page-mode read, an address is driven onto A[MAX:0], and CE# and ADV# are asserted. WE# and RST# must already have been deasserted. WAIT is deasserted during asynchronous page mode. ADV# can be driven high to latch the address, or it must be held low throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored. If only asynchronous reads are to be performed, CLK should be tied to a valid V IH level, WAIT signal can be floated and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial access time tA VQV delay. (see Section 7.0, “AC Characteristics” on page 28). In asynchronous page mode, four data words are “sensed” simultaneously from the flash memory array and loaded into an internal page buffer. The buffer word corresponding to the initial address on A[MAX:0] is driven onto DQ[15:0] after the initial access delay. Address bits A[MAX:2] select the 4-word page. Address bits A[1:0] determine which word of the 4-word page is output from the data buffer at any given time.

10.2 Synchronous Burst-Mode Read

Section 10.3, “Read Configuration Register (RCR)” on page 51continuous-wordsTo perform a synchronous burst- read, an initial address is driven onto A[MAX:0], and CE# and ADV# are asserted. WE# and RST# must already have been deasserted. ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can remain asserted throughout the burst access, in which case the address is latched on the next valid CLK edge while ADV# is asserted.

Count” on page 52). Subsequent data is output on valid CLK edges following a minimum delay. clock edges until the burst length requirements are satisfied.

10.2.1 Burst Suspend

later. Burst suspend provides maximum benefit in non-cache systems. without limit as long as device operation conditions are met. IH or VIL. WAIT is in High-Z during OE# deassertion. Figure 17, “Burst Suspend Timing” on page 36.

10.3 Read Configuration Register (RCR)

Configuration Register command (see Section 9.2, “Device Commands” on page 47). <partition base address> + 0x05 (see Section 15.2, “Read Device Identifier” on page 76). The RCR is shown in Table 10. The following sections describe each RCR bit. Table 10. Read Configuration Register Description (Sheet 1 of 2)

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10.3.1 Read Mode

cleared, synchronous burst mode is selected.

10.3.2 Latency Count

word is to be driven onto DQ[15:0]. The input clock frequency is used to determine this value. Figure 24 shows the data output latency for the different settings of LC[2:0]. Refer to Table 11 and Table 12 for Latency Code Settings.

15 Read Mode (RM) 0 = Synchronous burst-mode read

14 Reserved (R) Reserved bits should be cleared (0)

10 Wait Polarity (WP) 0 =WAIT signal is active low

9 Data Hold (DH) 0 =Data held for a 1-clock data cycle

8 Wait Delay (WD) 0 =WAIT deasserted with valid data

7 Burst Sequence (BS) 0 =Reserved

6 Clock Edge (CE) 0 = Falling edge

3 Burst Wrap (BW) 0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]

0). WD = 1 is not supported. Table 10. Read Configuration Register Description (Sheet 2 of 2)

See Figure 25, “Example Latency Count Setting” on page 54. Figure 24. First-Access Latency Count Table 11. LC and Frequency Support (t AVQV/tCHQV = 85 ns / 14 ns) Table 12. LC and Frequency Support (t AVQV/tCHQV = 90 ns / 17 ns)

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10.3.3 WAIT Polarity

The WAIT Polarity bit (WP), RCR[10] determines the asserted level (VOH or VOL) of WAIT. When WP is set, WAIT is asserted-high (default). When WP is cleared, WAIT is asserted-low.

10.3.3.1 WAIT Signal Function

(RCR[15]=0). The WAIT signal is only “deasserted” when data is valid on the bus. read query the WAIT signal is also “deasserted” when data is valid on the bus. “Asynchronous Page-Mode Read Timing” on page 34. Figure 25. Example Latency Count Setting

10.3.4 Data Hold

Table 13. WAIT Functionality Table

1. Active: WAIT is asserted until data becomes valid, then
2. When OE# = V IH during writes, WAIT = High-Z

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10.3.5 WAIT Delay

WD is cleared, WAIT is asserted during invalid data.

10.3.6 Burst Sequence

effect of the Burst Wrap (BW) setting. Figure 26. Data Hold Timing

1 CLK

Table 14. Burst Sequence Word Ordering (Sheet 1 of 2)

10.3.7 Clock Edge

edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert WAIT.

10.3.8 Burst Wrap

set, burst wrapping does not occur (default). When BW is cleared, burst wrapping occurs. boundary, the worst case output delay is one clock cycle less than the first access Latency Count. device-row boundary. WAIT informs the system of this delay when it occurs.

10.3.9 Burst Length

flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word. outputs synchronous burst data until it reaches the end of the “burstable” address space. Table 14. Burst Sequence Word Ordering (Sheet 2 of 2)

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11.0 Programming Operations

The device supports three programming methods: Word Programming (40h/10h), Buffered Programming (E8h, D0h), and Buffered Enhanced Factory Programming (Buffered EFP) (80h, D0h). See Section 9.0, “Device Operations” on page 45 for details on the various programming commands issued to the device. Successful programming requires the addressed block to be unlocked. If the block is locked down, WP# must be deasserted and the block must be unlocked before attempting to program the block. Attempting to program a locked block causes a program error (SR[4] and SR[1] set) and termination of the operation. See Section 13.0, “Security Modes” on page 66 for details on locking and unlocking blocks. The following sections describe device programming in detail.

11.1 Word Programming

Word programming operations are initiated by writing the Word Program Setup command to the device (see Section 9.0, “Device Operations” on page 45). This is followed by a second write to the device with the address and data to be programmed. The partition accessed during both write cycles outputs Status Register data when read. The partition accessed during the second cycle (the data cycle) of the program command sequence is the location where the data is written. See Figure 39, “Word Program Flowchart” on page 85. Programming can occur in only one partition at a time; all other partitions must be in a read state or in erase suspend. VPP must be above VPPLK, and within the specified VPPL min/max values (nominally 1.8 V). During programming, the Write State Machine (WSM) executes a sequence of internally-timed events that program the desired data bits at the addressed location, and verifies that the bits are sufficiently programmed. Programming the flash memory array changes “ones” to “zeros.” Memory array bits that are zeros can be changed to ones only by erasing the block (see Section 12.0, “Erase Operations” on page 64). The Status Register can be examined for programming progress and errors by reading any address within the partition that is being programmed. The partition remains in the Read Status Register state until another command is written to that partition. Issuing the Read Status Register command to another partition address sets that partition to the Read Status Register state, allowing programming progress to be monitored at that partition’s address. Status Register bit SR[7] indicates the programming status while the sequence executes. Commands that can be issued to the programming partition during programming are Program Suspend, Read Status Register, Read Device Identifier, CFI Query, and Read Array (this returns unknown data). When programming has finished, Status Register bit SR[4] (when set) indicates a programming failure. If SR[3] is set, the WSM could not perform the word programming operation because V PP was outside of its acceptable limits. If SR[1] is set, the word programming operation attempted to program a locked block, causing the operation to abort.

Intel StrataFlash® Wireless Memory (L18) Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005 Order Number: 251902, Revision: 009 59 Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow, when word programming has completed.

11.1.1 Factory Word Programming

Factory word programming is similar to word programming in that it uses the same commands and programming algorithms. However, factory word programming enhances the programming performance with VPP = VPPH. This can enable faster programming times during OEM manufacturing processes. Factory word programming is not intended for extended use. See Section 5.2, “Operating Conditions” on page 25 for limitations when VPP = VPPH. Note: When VPP = VPPL, the device draws programming current from the VCC supply. If VPP is driven by a logic signal, VPPL must remain above VPPL MIN to program the device. When VPP = VPPH, the device draws programming current from the VPP supply. Figure 27, “Example VPP Supply Connections” on page 63 shows examples of device power supply configurations.

11.2 Buffered Programming

The device features a 32-word buffer to enable optimum programming performance. For Buffered Programming, data is first written to an on-chip write buffer. Then the buffer data is programmed into the flash memory array in buffer-size increments. This can improve system programming performance significantly over non-buffered programming. When the Buffered Programming Setup command is issued (see Section 9.2, “Device Commands” on page 47), Status Register information is updated and reflects the availability of the write buffer. SR[7] indicates buffer availability: if set, the buffer is available; if cleared, the write buffer is not available. To retry, issue the Buffered Programming Setup command again, and re-check SR[7]. When SR[7] is set, the buffer is ready for loading. (see Figure 41, “Buffer Program Flowchart” on page 87). On the next write, a word count is written to the device at the buffer address. This tells the device how many data words will be written to the buffer, up to the maximum size of the buffer. On the next write, a device start address is given along with the first data to be written to the flash memory array. Subsequent writes provide additional device addresses and data. All data addresses must lie within the start address plus the word count. Optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 32-word boundary (A[4:0] = 0x00). Crossing a 32-word boundary during programming will double the total programming time. After the last data is written to the buffer, the Buffered Programming Confirm command must be issued to the original block address. The WSM begins to program buffer contents to the flash memory array. If a command other than the Buffered Programming Confirm command is written to the device, a command sequence error occurs and Status Register bits SR[7,5,4] are set. If an error occurs while writing to the array, the device stops programming, and Status Register bits SR[7,4] are set, indicating a programming failure. Reading from another partition is allowed while data is being programmed into the array from the write buffer (see Section 14.0, “Dual-Operation Considerations” on page 71).

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When Buffered Programming has completed, additional buffer writes can be initiated by issuing another Buffered Programming Setup command and repeating the buffered program sequence. Buffered programming may be performed with VPP = VPPL or VPPH (see Section 5.2, “Operating Conditions” on page 25 for limitations when operating the device with VPP = VPPH). If an attempt is made to program past an erase-block boundary using the Buffered Program command, the device aborts the operation. This generates a command sequence error, and Status Register bits SR[5,4] are set. If Buffered programming is attempted while VPP is below VPPLK, Status Register bits SR[4,3] are set. If any errors are detected that have set Status Register bits, the Status Register should be cleared using the Clear Status Register command.

11.3 Buffered Enhanced Factory Programming

Buffered Enhanced Factory Programing (Buffered EFP) speeds up Multi-Level Cell (MLC) flash programming for today's beat-rate-sensitive manufacturing environments. The enhanced programming algorithm used in Buffered EFP eliminates traditional programming elements that drive up overhead in device programmer systems. Buffered EFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 42, “Buffered EFP Flowchart” on page 88). It uses a write buffer to spread MLC program performance across 32 data words. Verification occurs in the same phase as programming to accurately program the flash memory cell to the correct bit state. A single two-cycle command sequence programs the entire block of data. This enhancement eliminates three write cycles per buffer: two commands and the word count for each set of 32 data words. Host programmer bus cycles fill the device’s write buffer followed by a status check. SR[0] indicates when data from the buffer has been programmed into sequential flash memory array locations. Following the buffer-to-flash array programming sequence, the Write State Machine (WSM) increments internal addressing to automatically select the next 32-word array boundary. This aspect of Buffered EFP saves host programming equipment the address-bus setup overhead. With adequate continuity testing, programming equipment can rely on the WSM’s internal verification to ensure that the device has programmed properly. This eliminates the external post- program verification and its associated overhead.

11.3.1 Buffered EFP Require ments and Considerations

Buffered EFP requirements:  Ambient temperature: TA = 25°C, ±5°C  VCC within specified operating range.  VPP driven to VPPH.  Target block unlocked before issuing the Buffered EFP Setup and Confirm commands.  The first-word address (WA0) for the block to be programmed must be held constant from the setup phase through all data streaming into the target block, until transition to the exit phase is desired.

Intel StrataFlash® Wireless Memory (L18) Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005 Order Number: 251902, Revision: 009 61  WA0 must align with the start of an array buffer boundary1. Buffered EFP considerations:  For optimum performance, cycling must be limited below 100 erase cycles per block2.  Buffered EFP programs one block at a time; all buffer data must fall within a single block3.  Buffered EFP cannot be suspended.  Programming to the flash memory array can occur only when the buffer is full4.  Read operation while performing Buffered EFP is not supported. NOTES: 1. Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] = 0x00. 2. Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work properly. 3. If the internal address counter increments beyond the block's maximum address, addressing wraps around to the beginning of the block. 4. If the number of words is less than 32, remaining locations must be filled with 0xFFFF.

11.3.2 Buffered EFP Setup Phase

After receiving the Buffered EFP Setup and Confirm command sequence, Status Register bit SR[7] (Ready) is cleared, indicating that the WSM is busy with Buffered EFP algorithm startup. A delay before checking SR[7] is required to allow the WSM enough time to perform all of its setups and checks (Block-Lock status, VPP level, etc.). If an error is detected, SR[4] is set and Buffered EFP operation terminates. If the block was found to be locked, SR[1] is also set. SR[3] is set if the error occurred due to an incorrect V PP level. Note: Reading from the device after the Buffered EFP Setup and Confirm command sequence outputs Status Register data. Do not issue the Read Status Register command; it will be interpreted as data to be loaded into the buffer.

11.3.3 Buffered EFP Program/Verify Phase

After the Buffered EFP Setup Phase has completed, the host programming system must check SR[7,0] to determine the availability of the write buffer for data streaming. SR[7] cleared indicates the device is busy and the Buffered EFP program/verify phase is activated. SR[0] indicates the write buffer is available. Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data programming to the array. For Buffered EFP, the count value for buffer loading is always the maximum buffer size of 32 words. During the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF. Caution: The buffer must be completely filled for programming to occur. Supplying an address outside of the current block's range during a buffer-fill sequence causes the algorithm to exit immediately. Any data previously loaded into the buffer during the fill cycle is not programmed into the array. The starting address for data entry must be buffer size aligned, if not the Buffered EFP algorithm will be aborted and the program fail (SR[4]) flag will be set.

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Data words from the write buffer are directed to sequential memory locations in the flash memory array; programming continues from where the previous buffer sequence ended. The host programming system must poll SR[0] to determine when the buffer program sequence completes. SR[0] cleared indicates that all buffer data has been transferred to the flash array; SR[0] set indicates that the buffer is not available yet for the next fill cycle. The host system may check full status for errors at any time, but it is only necessary on a block basis after Buffered EFP exit. After the buffer fill cycle, no write cycles should be issued to the device until SR[0] = 0 and the device is ready for the next buffer fill. Note: Any spurious writes are ignored after a buffer fill operation and when internal program is proceeding. The host programming system continues the Buffered EFP algorithm by providing the next group of data words to be written to the buffer. Alternatively, it can terminate this phase by changing the block address to one outside of the current block’s range. The Program/Verify phase concludes when the programmer writes to a different block address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the device enters the Buffered EFP Exit phase.

11.3.4 Buffered EFP Exit Phase

When SR[7] is set, the device has returned to normal operating conditions. A full status check should be performed on the partition being programmed at this time to ensure the entire block programmed successfully. When exiting the Buffered EFP algorithm with a block address change, the read mode of both the programmed and the addressed partition will not change. After Buffered EFP exit, any valid command can be issued to the device.

11.4 Program Suspend

Issuing the Program Suspend command while programming suspends the programming operation. This allows data to be accessed from memory locations other than the one being programmed. The Program Suspend command can be issued to any device address; the corresponding partition is not affected. A program operation can be suspended to perform reads only. Additionally, a program operation that is running during an erase suspend can be suspended to perform a read operation (see Figure 40, “Program Suspend/Resume Flowchart” on page 86). When a programming operation is executing, issuing the Program Suspend command requests the WSM to suspend the programming algorithm at predetermined points. The partition that is suspended continues to output Status Register data after the Program Suspend command is issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend latency is specified in Section 7.7, “Program and Erase Characteristics” on page 41. To read data from blocks within the suspended partition, the Read Array command must be issued to that partition. Read Array, Read Status Register, Read Device Identifier, CFI Query, and Program Resume are valid commands during a program suspend. A program operation does not need to be suspended in order to read data from a block in another partition that is not programming. If the other partition is already in a Read Array, Read Device Identifier, or CFI Query state, issuing a valid address returns corresponding read data. If the other partition is not in a read mode, one of the read commands must be issued to the partition before data can be read.

During a program suspend, deasserting CE# places the device in standby, reducing active current. suspend. If RST# is asserted, the device is reset.

11.5 Program Resume

must remain deasserted (see Figure 40, “Program Suspend/Resume Flowchart” on page 86).

11.6 Program Protection

even if VPP is less than VPPLK. Figure 27. Example VPP Supply Connections

• Factory Programming with VPP = VPPH
• Complete write/Erase Protection when VPP ≤ VPPLK VCC VPP VCC VPP
• Low Voltage and Factory Programming
• Low-voltage Programming only
• Logic Control of Device Protection VCC VPP
• Low Voltage Programming Only
• Full Device Protection Unavailable VCC VPP ≤ 10K Ω VPP VCC VCC PROT # VCC VPP=VPPH VCC

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12.0 Erase Operations

Flash erasing is performed on a block basis. An entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. When a block is erased, all bits within that block read as logical ones. The following sections describe block erase operations in detail.

12.1 Block Erase

Block erase operations are initiated by writing the Block Erase Setup command to the address of the block to be erased (see Section 9.2, “Device Commands” on page 47). Next, the Block Erase Confirm command is written to the address of the block to be erased. Erasing can occur in only one partition at a time; all other partitions must be in a read state. If the device is placed in standby (CE# deasserted) during an erase operation, the device completes the erase operation before entering standby.VPP must be above VPPLK and the block must be unlocked (see Figure 43, “Block Erase Flowchart” on page 89). During a block erase, the Write State Machine (WSM) executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array changes “zeros” to “ones.” Memory array bits that are ones can be changed to zeros only by programming the block (see Section 11.0, “Programming Operations” on page 58). The Status Register can be examined for block erase progress and errors by reading any address within the partition that is being erased. The partition remains in the Read Status Register state until another command is written to that partition. Issuing the Read Status Register command to another partition address sets that partition to the Read Status Register state, allowing erase progress to be monitored at that partition’s address. SR[0] indicates whether the addressed partition or another partition is erasing. The partition’s Status Register bit SR[7] is set upon erase completion. Status Register bit SR[7] indicates block erase status while the sequence executes. When the erase operation has finished, Status Register bit SR[5] indicates an erase failure if set. SR[3] set would indicate that the WSM could not perform the erase operation because V PP was outside of its acceptable limits. SR[1] set indicates that the erase operation attempted to erase a locked block, causing the operation to abort. Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow once the block erase operation has completed.

12.2 Erase Suspend

Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows data to be accessed from memory locations other than the one being erased. The Erase Suspend command can be issued to any device address; the corresponding partition is not affected. A block erase operation can be suspended to perform a word or buffer program operation, or a read operation within any block except the block that is erase suspended (see Figure 40, “Program Suspend/Resume Flowchart” on page 86).

Intel StrataFlash® Wireless Memory (L18) Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005 Order Number: 251902, Revision: 009 65 When a block erase operation is executing, issuing the Erase Suspend command requests the WSM to suspend the erase algorithm at predetermined points. The partition that is suspended continues to output Status Register data after the Erase Suspend command is issued. Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is specified in Section 7.7, “Program and Erase Characteristics” on page 41. To read data from blocks within the suspended partition (other than an erase-suspended block), the Read Array command must be issued to that partition first. During Erase Suspend, a Program command can be issued to any block other than the erase-suspended block. Block erase cannot resume until program operations initiated during erase suspend complete. Read Array, Read Status Register, Read Device Identifier, CFI Query, and Erase Resume are valid commands during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase Suspend. To read data from a block in a partition that is not erasing, the erase operation does not need to be suspended. If the other partition is already in Read Array, Read Device Identifier, or CFI Query, issuing a valid address returns corresponding data. If the other partition is not in a read state, one of the read commands must be issued to the partition before data can be read. During an erase suspend, deasserting CE# places the device in standby, reducing active current. VPP must remain at a valid level, and WP# must remain unchanged while in erase suspend. If RST# is asserted, the device is reset.

12.3 Erase Resume

The Erase Resume command instructs the device to continue erasing, and automatically clears status register bits SR[7,6]. This command can be written to any partition. When read at the partition that’s erasing, the device outputs data corresponding to the partition’s last state. If status register error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted (see Figure 40, “Program Suspend/Resume Flowchart” on page 86).

12.4 Erase Protection

When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If VPP is below VPPLK, erase operations halt and SR[3] is set indicating a VPP-level error.

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13.0 Security Modes

The device features security modes used to protect the information stored in the flash memory array. The following sections describe each security mode in detail.

13.1 Block Locking

Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power up in a locked state to protect array data from being altered during power transitions. Any block can be locked or unlocked with no latency. Locked blocks cannot be programmed or erased; they can only be read. Software-controlled security is implemented using the Block Lock and Block Unlock commands. Hardware-controlled security can be implemented using the Block Lock-Down command along with asserting WP#. Also, V PP data security can be used to inhibit program and erase operations (see Section 11.6, “Program Protection” on page 63 and Section 12.4, “Erase Protection” on page 65).

13.1.1 Lock Block

To lock a block, issue the Lock Block Setup command. The next command must be the Lock Block command issued to the desired block’s address (see Section 9.2, “Device Commands” on page 47 and Figure 45, “Block Lock Operations Flowchart” on page 91). If the Set Read Configuration Register command is issued after the Block Lock Setup command, the device configures the RCR instead. Block lock and unlock operations are not affected by the voltage level on VPP. The block lock bits may be modified and/or read even if VPP is below VPPLK.

13.1.2 Unlock Block

The Unlock Block command is used to unlock blocks (see Section 9.2, “Device Commands” on page 47). Unlocked blocks can be read, programmed, and erased. Unlocked blocks return to a locked state when the device is reset or powered down. If a block is in a lock-down state, WP# must be deasserted before it can be unlocked (see Figure 28, “Block Locking State Diagram” on page 67).

13.1.3 Lock-Down Block

A locked or unlocked block can be locked-down by writing the Lock-Down Block command sequence (see Section 9.2, “Device Commands” on page 47). Blocks in a lock-down state cannot be programmed or erased; they can only be read. However, unlike locked blocks, their locked state cannot be changed by software commands alone. A locked-down block can only be unlocked by issuing the Unlock Block command with WP# deasserted. To return an unlocked block to locked- down state, a Lock-Down command must be issued prior to changing WP# to V IL. Locked-down blocks revert to the locked state upon reset or power up the device (see Figure 28, “Block Locking State Diagram” on page 67).

13.1.4 Block Lock Status

DQ0 is the addressed block’s lock bit, while DQ1 is the addressed block’s lock-down bit.

13.1.5 Block Locking During Suspend

masked by the command sequence error. Figure 28. Block Locking State Diagram Notes: 1. [a,b,c] represents [WP#, DQ1, DQ0]. X = Don’t Care.

1. DQ1 indicates Block Lock-Down status. DQ1 = ‘0’, Lock-Down has not been issued

to this block. DQ1 = ‘1’, Lock-Down has been issued to this block.

1. DQ0 indicates block lock status. DQ0 = ‘0’, block is unlocked. DQ0 = ‘1’, block is
2. Locked-down = Hardware + Software locked.
3. [011] states should be tracked by system software to determine difference between

Hardware Locked and Locked-Down states.

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If a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. However, the erase operation completes when it is resumed. Block lock operations cannot occur during a program suspend. See Appendix A, “Write State Machine (WSM)” on page 78, which shows valid commands during an erase suspend.

13.2 Protection Registers

The device contains 17 Protection Registers (PRs) that can be used to implement system security measures and/or device identification. Each Protection Register can be individually locked. The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The lower 64- bit segment is pre-programmed at the factory with a unique 64-bit number. The other 64-bit segment, as well as the other sixteen 128-bit Protection Registers, are blank. Users can program these registers as needed. When programmed, users can then lock the Protection Register(s) to prevent additional bit programming (see Figure 29, “Protection Register Map” on page 69). The user-programmable Protection Registers contain one-time programmable (OTP) bits; when programmed, register bits cannot be erased. Each Protection Register can be accessed multiple times to program individual bits, as long as the register remains unlocked. Each Protection Register has an associated Lock Register bit. When a Lock Register bit is programmed, the associated Protection Register can only be read; it can no longer be programmed. Additionally, because the Lock Register bits themselves are OTP, when programmed, Lock Register bits cannot be erased. Therefore, when a Protection Register is locked, it cannot be unlocked

13.2.1 Reading the Protection Registers

Figure 29. Protection Register Map

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13.2.2 Programming the Protection Registers

To program any of the Protection Registers, first issue the Program Protection Register command at the parameter partition’s base address plus the offset to the desired Protection Register (see Section 9.2, “Device Commands” on page 47). Next, write the desired Protection Register data to the same Protection Register address (see Figure 29, “Protection Register Map” on page 69). The device programs the 64-bit and 128-bit user-programmable Protection Register data 16 bits at a time (see Figure 46, “Protection Register Programming Flowchart” on page 92). Issuing the Program Protection Register command outside of the Protection Register’s address space causes a program error (SR[4] set). Attempting to program a locked Protection Register causes a program error (SR[4] set) and a lock error (SR[1] set). Note: If a program or erase operation occurs when programming a Protection Register, certain restrictions may apply. See Table 15, “Simultaneous Operation Restrictions” on page 74 for details.

13.2.3 Locking the Pr otection Registers

Each Protection Register can be locked by programming its respective lock bit in the Lock Register. To lock a Protection Register, program the corresponding bit in the Lock Register by issuing the Program Lock Register command, followed by the desired Lock Register data (see Section 9.2, “Device Commands” on page 47). The physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These addresses are used when programming the lock registers (see Table 17, “Device Identifier Information” on page 77). Bit 0 of Lock Register 0 is already programmed at the factory, locking the lower, pre-programmed 64-bit region of the first 128-bit Protection Register containing the unique identification number of the device. Bit 1 of Lock Register 0 can be programmed by the user to lock the user-programmable, 64-bit region of the first 128-bit Protection Register. The other bits in Lock Register 0 are not used. Lock Register 1 controls the locking of the upper sixteen 128-bit Protection Registers. Each of the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit Protection Registers. Programming a bit in Lock Register 1 locks the corresponding 128-bit Protection Register. Caution: After being locked, the Protection Registers cannot be unlocked.

14.0 Dual-Operation Considerations

occur in one partition while data reads (or code execution) take place in another partition.

14.1 Memory Partitioning

a time can be in program or erase mode.

14.2 Read-While-Write Command Sequences

returned, regardless of the read mode of the partition prior to issuing the Setup command. Figure 30. Operating Mode with Correct Command Sequence Example

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14.2.1 Simultaneous Operation Details

will be detailed in the following sections.

14.2.2 Synchronous and Asynchrono us RWW Characteristics and

read, and write operation with clock active.

14.2.2.1 Write operation to asynchronous read transition

write cycle (WE# going high) to perform an asynchronous read (only address valid is required). Figure 31. Operating Mode with Correct Command Sequence Example Figure 32. Operating Mode with Illegal Command Sequence Example

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14.2.2.2 Write to synchronous read operation transition

W19 and W20 - tWHCV and tWHVH The AC parameters W19 or W20 (tWHCV-WE# High to Clock Valid, and tWHVH - WE# High to ADV# High) is required when transitioning from a write cycle (WE# going high) to perform a synchronous burst read. A delay from WE# going high to a valid clock edge or ADV# going high to latch a new address must be met.

14.2.2.3 Write Operation with Clock Active

The AC parameters W21 (tVHWL- ADV# High to WE# Low) and W22 (tCHWL -Clock high to WE# low) are required during write operations when the device is in a synchronous mode and the clock is active. A write bus cycle consists of two parts:  the host provides an address to the flash device; and  the host then provides data to the flash device. The flash device in turn binds the received data with the received address. When operating synchronously (RCR[15] = 0), the address of a write cycle may be provided to the flash by the first active clock edge with ADV# low, or rising edge of ADV# as long as the applicable cycle separation conditions are met between each cycle. If neither a clock edge nor a rising ADV# edge is used to provide a new address at the beginning of a write cycle (the clock is stopped and ADV# is low), the address may also be provided to the flash device by holding the address bus stable for the required amount of time (W5, tAV W H) before the rising WE# edge. Alternatively, the host may choose not to provide an address to the flash device during subsequent write cycles (if ADV# is high and only CE# or WE# is toggled to separate the prior cycle from the current write cycle). In this case, the flash device will use the most recently provided address from the host. Refer to Figure 20, “Write to Asynchronous Read Timing” on page 39, Figure 21, “Synchronous Read to Write Timing” on page 39, and Figure 22, “Write to Synchronous Read Timing” on page 40, for representation of these timings.

14.2.3 Read Operation During Buffered Programming

The multi-partition architecture of the device allows background programming (or erasing) to occur in one partition while data reads (or code execution) take place in another partition. To perform a read while buffered programming operation, first issue a Buffered Program set up command in a partition. When a read operation occurs in the same partition after issuing a setup command, Status Register data will be returned, regardless of the read mode of the partition prior to issuing the setup command.

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on page 87 for more details. Note: Simultaneous read-while-Buffered EFP is not supported.

14.3 Simultaneous Operation Restrictions

Table 15. Simultaneous Operation Restrictions data may be read from any other partition. or Query data is being read from addresses within the parameter partition. is not allowed when reading array data from the parameter partition. partition is in Read Status. Reads in partitions other than the parameter partition are supported.

15.0 Special Read States

until the burst length requirements are satisfied. Single-Word Array or Non-array Read Timing” on page 35 for details.

15.1 Read Status Register

The Status Register is read using single asynchronous-mode or synchronous burst mode reads. state of the other partitions. PP, and block-locked operations. Table 16. Status Register Description (Sheet 1 of 2)

7 Device Write Status

0 = Device is busy; program or erase cycle in progress; SR[0] valid. 1 = Device is ready; SR[6:1] are valid.

6 Erase Suspend Status

0 = Erase suspend not in effect. 1 = Erase suspend in effect.

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operation cannot be detected via the Status Register because it contains the previous error status.

15.1.1 Clear Status Register

15.2 Read Device Identifier

5 Erase Status (ES) 0 = Erase successful. 1 = Erase fail or program sequence error when set with SR[4,7]. 4 Program Status (PS) 0 = Program successful. 3V PP Status (VPPS) 0 = VPP within acceptable limits during program or erase operation. 1 = VPP < VPPLK during program or erase operation.

2 Program Suspend Status

0 = Program suspend not in effect. 1 = Program suspend in effect.

1 Block-Locked Status

0 = Block not locked during program or erase. 1 = Block locked during program or erase; operation aborted.

0 Partition Write Status

0 0 = Program or erase operation in addressed partition. 0 1 = Program or erase operation in other partition. 1 0 = No active program or erase operations. Table 16. Status Register Description (Sheet 2 of 2)

15.3 CFI Query

information and address offsets within the CFI database. outputs in the CFI Query state, while the partition continues to program or erase in the background. availability, as described in Table 15. Table 17. Device Identifier Information

• Block Is Unlocked DQ 0 = 0b0
• Block Is Locked DQ 0 = 0b1
• Block Is not Locked-Down DQ 1 = 0b0
• Block Is Locked-Down DQ 1 = 0b1 Configuration Register PBA + 0x 05 Configuration Register Data Lock Register 0 PBA + 0x80 PR-LK0 64-bit Factory-Programmed Protection Register PBA + 0x81–0x84 Factory Protection Register Data 64-bit User-Programmable Protection Register PBA + 0x85–0x88 User Protection Register Data Lock Register 1 PBA + 0x89 Protection Register Data 16x128-bit User-Programmable Protection Registers PBA + 0x8A–0x109 PR-LK1 Notes: 1. PBA = Partition Base Address. 2. BBA = Block Base Address.

Table 18. Device ID codes

64 Mbit 880B 880E

128 Mbit 880C 880F

256 Mbit 880D 8810

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Figure 33. Write State Machine—Next State Table (Sheet 1 of 6)

Figure 34. Write State Machine—Next State Table (Sheet 2 of 6)

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Figure 35. Write State Machine—Next State Table (Sheet 3 of 6)

Figure 36. Write State Machine—Next State Table (Sheet 4 of 6)

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Figure 37. Write State Machine—Next State Table (Sheet 5 of 6)

1. "Illegal commands" include commands outside of the allowed command set (allowed commands: 40H
2. If a "Read Array" is attempted from a busy partition, the result will be invalid data. The ID and Query

data are located at different locations in the address map.

1. 1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or

unexpected results will occur.

1. To protect memory contents against erroneous comm and sequences, there are specific instances in a

Figure 38. Write State Machine—Next State Table (Sheet 6 of 6)

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resume command (0xD0), the second command will be ignored because it is unclear whether the user intends to erase the block or resume the program operation. 5. The Clear Status command onl y clears the error bits in the status register if the device is not in the following modes: WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes). 6. BEFP writes are only allowed when the status r egister bit #0 = 0, or else the data is ignored. 7. The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array, ID/CFI or Status) it was last pointed to on the last instruction to the "chip", but the next state of the chip does not depend on where the partition's output mux is presently pointing to. 8. Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register) perform the operation and then move to the Ready State. 9. WA0 refers to the block address latched during the first write cycle of the current operation.

Figure 39. Word Program Flowchart Repeat for subsequent Word Program operations. after a sequence of program operations.

1 VPP Range

command clears the Status Register error bits.

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Figure 40. Program Suspend/Resume Flowchart

Figure 41. Buffer Program Flowchart

1. Word count value on D[7:0] is loaded into the word count

register. Count ranges for this device are N = 0x00 to 0x1F.

1. The device outputs the Status Register when read.
2. Write Buffer contents will be programmed at the issued word
3. Align the start address on a Write Buffer boundary for
4. The Buffered Programming Confirm command must be

loop that loaded the buffer data.

1. The Status Register indicates an improper command

Clear Status Register command to clear error bits.

1. The Status Register can be read from any addresses within

place the partition in the Read Array state.

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Figure 42. Buffered EFP Flowchart

1. First-word address to be programmed within the target block must be aligned on a write-buffer boundary.
2. Write-buffer contents are programmed sequentially to the flash array starting at the first word address;WSM internally increments addressing.

Write 0xFF to enter Read Array state.

Figure 43. Block Erase Flowchart Repeat for subsequent block erasures. or after a sequence of block erasures. Write 0xFF after the last operation to enter read array mode. Only the Clear Status Register command clears SR[1, 3, 4, 5]. attempting an erase retry or other error recovery.

0 Yes

Read None Status Register data.

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Figure 44. Erase Suspend/Resume Flowchart Read None Status Register data.

Figure 45. Block Lock Operations Flowchart Confirm locking change on D[1,0].

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Figure 46. Protection Register Programming Flowchart outside this space will return an error. Repeat for subsequent programming operations. after a sequence of program operations. Write 0xFF after the last operation to set Read Array state. Only the Clear Staus Register command clears SR[1, 3, 4]. attempting a program retry or other error recovery. Read None Status Register Data.

block erases, reads and otherwise control the flash device. The Query database allows system software to obtain information for controlling the flash device. This section describes the device’s CFI-compliant interface that allows access to Query data. devices, the Query table device starting address is a 10h, which is a word address for x16 devices. 7-0) and 00h in the high byte (DQ15-8). presented at the lower address, and the most significant data byte is presented at the higher address. shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode. Table 20. Example of Query Structure Output of x16- Devices Table 19. Summary of Query Structure Output as a Function of Device and Mode

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Table 21. Query Structure

1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as

a function of device bus width and mode.

1. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size
2. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.

Table 22. CFI Identification

Table 23. System Interface Information Table 24. Device Geometry Definition Offset Length Description Add. Offset Length Description Add.

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Offset Length Description Code 27h 1 “n” such that device size = 2n in number of bytes 27: See table below 76543210 2 8 h 2 ———— x 6 4 x 3 2 x 1 6 x 8 2 8 : - - 0 1 x 1 6 15 14 13 12 11 10 9 8 2Ah 2 “n” such that maximum number of bytes in write buffer = 2n 2A: --06 64 2B: --00 2Ch 1 2C: 2Dh 4 Erase Block Region 1 Information 2D: bits 0–15 = y, y+1 = number of identical-size erase blocks 2E: bits 16–31 = z, region erase block(s) size are z x 256 bytes 2F: 30: 31h 4 Erase Block Region 2 Information 31: bits 0–15 = y, y+1 = number of identical-size erase blocks 32: bits 16–31 = z, region erase block(s) size are z x 256 bytes 33: 34: 35h 4 Reserved for future erase block region information 35: 36: 37: 38: See table below See table below See table below See table below Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table: Number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. Symmetrically blocked partitions have one blocking region Address 64 Mbit

128 Mbit 256 Mbit

Table 25. Primary Vendor-Specific Extended Query

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Table 26. Protection Register Information Table 27. Burst Read Information pre-programmed and user-programmable. Following bytes are factory or user-programmable. Number of Protection register fields in JEDEC ID space. follow. 00h indicates no burst capability. word width to determine the burst data output width.

Table 28. Partition and Erase-block Region Information (P+23)h (P+23)h 1 12D: 12D:Number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). one or more contiguous erase block regions.

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Table 29. Partition Region 1 Information mode capabilities defined in Table 10. Types of erase block regions in this Partition Region.

Table 30. Partition Region 2 Information mode capabilities as defined in Table 10. mode capabilities as defined in Table 10. Types of erase block regions in this Partition Region.

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Table 31. Partition and Erase Block Region Information

Intel StrataFlash® Wireless Memory (L18) Datasheet Intel StrataFlash® Wireless Memory (L18) April 2005 Order Number: 251902, Revision: 009 103 Appendix D Additional Information Order/Document Number Document/Tool

251903 Intel StrataFlash ® Wireless Memory (L30) Datasheet

290701 Intel ® Wireless Flash Memory (W18) Datasheet

290702 Intel ® Wireless Flash Memory (W30) Datasheet

290737 Intel StrataFlash ® Synchronous Memory (K3/K18) Datasheet

251908 Migration Guide for 1.8 Volt Intel® Wireless Flash Memory (W18/W30) to 1.8 Volt Intel StrataFlash® Wireless Memory (L18/L30), Application Note 753 251909 Migration Guide for 3 Volt Synchronous Intel StrataFlash® Memory (K3/K18) to 1.8 Volt Intel StrataFlash® Wireless Memory (L18/L30), Application Note 754

298161 Intel ® Flash Memory Chip Scale Package User’s Guide

297833 Intel ® Flash Data Integrator (FDI) User’s Guide

298136 Intel ® Persistent Storage Manager User Guide

Notes: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http:/ /www.intel.com for technical documentation and tools. 3. For the most current information on Intel StrataFlash ® memory, visit our website at http:// developer.intel.com/design/flash/isf.

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Figure 47. Ordering Information for L18 in VF BGA

Intel StrataFlash® Wireless Memory (L18) April 2005 Intel StrataFlash® Wireless Memory (L18) Datasheet

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