PXA250 INTEL | Alldatasheet

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Intel® PXA250 and PXA210 Applications Processors Electrical, Mechanical, and Thermal Specification Datasheet Product Features High Performance Processor —Intel® XScale™ Microarchitecture —32KB Instruction Cache —32KB Data Cache —2KB “mini” Data Cache —Extensive Data Buffering Intel® Media Processing Technology —Enhanced 16-bit Multiply —40-bit Accumulator Flexible Clocking —CPU clock from 66 to 300MHz —Flexible memory clock ratios —Frequency change modes Rich Serial Peripheral Set —AC97 Audio Port —I2S Audio Port —USB Client Controller —High Speed UART —Second UART with flow control —FIR and SIR infrared comm ports Low Power —Less than 500mW Typical Internal Dissipation —Supply Voltage may be Reduced to 0.85V —Low Power/Sleep Modes High Performance Memory Controller —Four Banks of SDRAM - up to 100MHz —Five Static Chip Selects —Support for PCMCIA or Compact Flash —Companion Chip interface Additional Peripherals for system connectivity —Multimedia Card Controller (MMC) —SSP Controller —I2C Controller —Two Pulse Width Modulators (PWMs) —All peripheral pins double as GPIOs. Hardware debug features Hardware Performance Monitoring features Order Number: 278524-001 February, 2002

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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® PXA250 and PXA210 Applications Processors may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com . Copyright © Intel Corporation, 2002 *Other names and brands may be claimed as the property of others.

PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification

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Revision History

7/6/010.5First Release 2/8/02-001First public release of the EMTS

PXA250 and PXA210 — Electrical, Mechanical, and Thermal Specification

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by Intel’s XScaleTM Microarchitecture. flexibility in color mapping. “Applications Processor Block Diagram” on page8 . Table 1. Related Documentation

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  • The PXA250 applications processor, 256-pin mBGA (refer to Figure 2, “PXA250 Applications Processor” on page16)
  • The PXA210 applications processor, 225-pin TPBGA package (refer to Figure 3, “PXA210 Applications Processor” on page26)

Figure 1. Applications Processor Block Diagram

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Lead 17x17mm mBGA Pinout — Ballpad Number Order” on page17. Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 1 of 7) MD[15:0]ICOCZMemory data bus. D[15:0] are used for 16-bit data mode. processor, 16-bit package option. memory devices to control their data bus drivers. mask enables (DQM) for SDRAM. pins for all banks of SDRAM. SDRAM and/or Synchronous Static Memory clock enable. SDRAM and/or Synchronous Static Memory clock enable. during sleep. SDCKE[1] is always deasserted upon reset.

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memory bank 0 is configured for SMROM or SDRAM-timing Synchronous Flash. SDCLK[2:1] control register assertion bits are always deasserted upon reset. GPIO[80] ICOCZStatic chip select 4. GPIO[79] ICOCZStatic chip select 3. GPIO[78] ICOCZStatic chip select 2. GPIO[15] ICOCZStatic chip select 1. from memory and attribute space. one enables the high byte lane and bit zero enables the low byte lane. Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 2 of 7)

card that the current address is a valid 16 bit wide I/O address. extend the length of the transfers to/from applications processor. socket one is selected. This signal has the same timing as an address. Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 3 of 7)

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USB_PIAOAUSB Client port positive Pin of differential pair. USB_NIAOAUSB Client port negative Pin of differential pair. This pin is a dedicated output. Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 4 of 7)

GPIO[46] ICOCZ IrDA Receive signal (input). IrDA Transmit signal (output). This pin is the transmit pin for both the SIR and FIR functions. I2C Data signal (bidirectional). requires a pull up resistor. As an input, it expects standard CMOS levels. (nRESET) as wakeup sources for both rising and falling edge detects. main external sleep wakeup stimulus. Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 5 of 7)

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000 Asynchronous 32-bit ROM

Power Enable. Active high output. Battery Fault. Active low input. recognize a wakeup event while this signal is asserted. VDD Fault. Active low input. timer completes (approximately 10 ms). Hard reset. Active low input. LOW the processor performs idle cycles. Reset Out. Active low output. If JTAG is not used, then tie nTRST to either nRESET or low. TDIICJTAG test interface data input. Note this pin has an internal pullup resistor. TMSICJTAG test interface mode select. Note this pin has an internal pullup resistor. on the JTAG test interface. Note this pin has an internal pulldown resistor. TESTICTest Mode. You must ground this pin. This pin is for manufacturing purposes only. Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 6 of 7)

to the low voltage (.85 - 1.3v) supply on the PCB. the common ground plane on the PCB. this pin to the common low voltage supply. PLL_VSSSUPGround signal for PLLs. these pins to the common 3.3volt supply on the PCB. these pins to the common ground plane on the PCB. common 3.3volt supply on the PCB. common ground plane on the PCB.

  1. GPIO Reset Operation: Configured as GPIO inputs by default after any reset. The input buffers for these

pins are disabled to prevent current drain. Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 7 of 7)

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Figure 2. PXA250 Applications Processor

Table 3. PXA250 256-Lead 17x17mm mBGA Pinout — Ballpad Number Order (Sheet 1 of 3)

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Table 3. PXA250 256-Lead 17x17mm mBGA Pinout — Ballpad Number Order (Sheet 2 of 3)

Table 3. PXA250 256-Lead 17x17mm mBGA Pinout — Ballpad Number Order (Sheet 3 of 3) Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 1 of 7) MD[15:0]ICOCZ Memory data bus. (input/output) Lower 16 bits of the data bus. devices to control data bus drivers. nWEOCZ Memory write enable. (output) Connect to the write enables of memory devices. controller provides control register bits for deassertion.

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  1. At reset, all clock pins are free running at the divide by 2 clock speed and may

deasserted on reset. SDCLK[1] can be Hi-Z, SDCLK[0] cannot. and Flash. Individually programmable in the memory configuration registers. nCS[5:3] can be used with variable latency I/O devices. external bus device is ready to transfer data. device to request the system bus from the Memory Controller. device to request the system bus from the Memory Controller. Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 2 of 7)

MMC chip select 0. (output) Chip select 0 for the MMC Controller. MMC chip select 1. (output) Chip select 1 for the MMC Controller. MMC clock. (output) Clock for the MMC Controller. RTC clock. (output) Real time clock 1 Hz tick. 3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator. 32 kHz clock. (output) Output from the 32 kHz oscillator. GPIO[76] ICOCZ LCD pixel clock. (output) Clocks valid pixel data into the LCD ’s line shift buffer. LCD panel. For TFT panels, this signal indicates valid pixel data. MMC chip select 0. (output) Chip select 0 for the MMC Controller. MMC chip select 1. (output) Chip select 1 for the MMC Controller. Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 3 of 7)

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GPIO[46] ICOCZ IrDA receive signal. (input) Receive pin for the FIR function. GPIO[53]ICOCZ MMC clock. (output) Clock signal for the MMC Controller. MMC chip select 0. (output) Chip select 0 for the MMC Controller. MMC chip select 1. (output) Chip select 1 for the MMC Controller. MMC clock. (output) Clock for the MMC Controller. MMC chip select 0. (output) Chip select 0 for the MMC Controller. MMC chip select 1. (output) Chip select 1 for the MMC Controller. Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 4 of 7)

into the PXA210 applications processor and Codec 1. GPIO[29] ICOCZ AC97 Audio Port data in. (input) Input line for Codec 0. I2S data in. (input) Input line for the I 2S Controller. GPIO[32] ICOCZ AC97 Audio Port data in. (input) Input line for Codec 1. I2S system clock. (output) System clock from I 2S Controller. GPIO[30] ICOCZ AC97 Audio Port data out. (output) Output from the PXA210 to Codecs 0 and 1. I2S data out. (output) Output line for the I 2S Controller. I2Ssync. (output) Frame sync signal for the I 2S Controller. SDAICOCZ I2C data. (bidirectional). PXTALIA 3.6864 Mhz crystal input. PEXTALOA 3.6864 Mhz crystal output. TXTALIA 32.768 khz crystal input. TEXTALOA 32.768 khz crystal output. RTC clock. (output) Real time clock 1 Hz tick. 3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator. 32 kHz clock. (output) Output from the 32 kHz oscillator. Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 5 of 7)

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[2:0] IC Boot select pins. (input)Indicates type of boot device. supply to remove power because the system is entering Sleep Mode. processor will not recognize a wakeup event while this signal is asserted. VDD Fault. (input) Signals that the main power source is going out of regulation. internal 3.6864 MHz oscillator has stabilized. asserted for “soft” reset events: sleep, watchdog reset, or GPIO reset. Processor Design Guide ” for details. using this pin. This pin has an internal pull-up resistor. returned to the JTAG controller using this pin. controller. This pin has an internal pull-up resistor. TCKIC JTAG test clock. (input) Clock for all transfers on the JTAG test interface. TESTIC Test Mode. (input) Reserved. Must be grounded. TESTCLKIC Test Clock. (input) Reserved. Must be grounded. supply plane on the PCB but may be connected to the common low voltage supply. PLL_VSSSUP Ground signal for PLLs. common 3.3V supply on the PCB. Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 6 of 7)

common ground plane on the PCB. the common ground plane on the PCB. Table 4. Pin and Signal Descriptions for the PXA210 Applications Processor (Sheet 7 of 7)

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Figure 3. PXA210 Applications Processor

Table 5. PXA210 225-Lead 13x13mm TPBGA Pinout — Ballpad Number Order (Sheet 1 of 3)

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Table 5. PXA210 225-Lead 13x13mm TPBGA Pinout — Ballpad Number Order (Sheet 2 of 3)

Maximum Ratings is not guaranteed. Table 5. PXA210 225-Lead 13x13mm TPBGA Pinout — Ballpad Number Order (Sheet 3 of 3) Table 7. Absolute Maximum Ratings (Sheet 1 of 2)

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range is dependent on the operation voltage. Note: The parameters in Table 8 are preliminary and subject to change. Table 7. Absolute Maximum Ratings (Sheet 2 of 2) Table 8. Voltage, Temperature, and Frequency Electrical Specifications (Sheet 1 of 2)

The DC Characteristics for each pin include input sense levels and output drive levels and currents. Table 8. Voltage, Temperature, and Frequency Electrical Specifications (Sheet 2 of 2) Table 9. Standard Input, Output, and I/O Pin DC Operating Conditions

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  • nCS[5:1] (GP 33, 80, 79, 78, 15 respectively), nCS[0]
  • DQM[3:0]
  • nOE, nWE, nSDRAS, nSDCAS, nSDCS[3:0]
  • SDCLK[2:0], SDCKE[1:0]
  • RDnWR, RDY (GP[18])
  • nPWE, nPOE pins (GP[49:48])
  • MMCLK (GP[53]), MMCMD, MMDAT
  • TDO
  • nACRESET 2.Low Strength Input, Output, and I/O pins - all remaining non-supply pins A pin’s AC Characteristics include input and output capacitance. These determine loading for external drivers or other load analysis. The AC Characteristics also include a de-rating factor, which indicates how much faster or slower the AC timings get with different loads. The AC Operating Conditions for the high- and low-strength input, output, and I/O pins are shown in Table10, “Standard Input, Output, and I/O Pin AC Operating Conditions”. All AC specification values are valid for entire temperature range of the device.

Table 10. Standard Input, Output, and I/O Pin AC Operating Conditions

  • Drive the TEXTAL pin with a digital signal that has a low level near 0volts and a high level near VCC. Do not exceed VCC or go below VSS by more than 100mV. The minimum slew rate is 1volt per 1 µs. The maximum current sourced by the external clock source when the clock is at its maximum positive voltage should be approximately 1mA.
  • Float the TXTAL pin or drive it complementary to the TEXTAL pin, with the same voltage level, slew rate, and input current restrictions.

Table 11. 32.768kHz Oscillator Specifications

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  • Drive the PEXTAL pin with a digital signal with a low level near 0volts and a high level near VCC. Do not exceed VCC or go below VSS by more than 100mV. The minimum slew rate is 1volt / 100ns. The maximum current sourced by the external clock source when the clock is at its maximum positive voltage should be approximately 1mA.
  • Float the PXTAL pin or drive it complementary to the PXTAL pin, with the same voltage level, slew rate, and input current restrictions. If floated, some degree of noise susceptibility will be introduced in the system, and it is therefore not recommended.

Table 12. 3.6864MHz Oscillator Specifications

4.6Reset and Power AC Timing Specifications The applications processor asserts the nRESET_OUT pin in one of several different modes:

  • Power On
  • Hardware Reset
  • Watchdog Reset
  • GPIO Reset
  • Sleep Mode The following sections give the timing and specifications for the entry and exit of these modes. 4.6.1Power On Timing The External Voltage Regulator and other power-on devices must provide the applications processor with a specific sequence of power and resets to ensure proper operation. This sequence is shown in Figure 4, “Power-On Reset Timing” on page36, and detailed in Table13, “Power-On Timing Specifications” on page36. On the applications processor, it is important that the power supplies be powered-up in a certain order to avoid high current situations. The required order is: 1.BATT_VCC 2.VCCQ 3.VCCN 4.VCC and PLL_VCC The supply in step 3 may be powered at the same time as those in step 2, however, VCCN should not be powered before VCCQ.

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times and nRESET timing requirements indicated in Table 13. indicated in Section 4.6.1, “Power On Timing” on page35. Figure 4. Power-On Reset Timing Table 13. Power-On Timing Specifications deasserted or the PXA250 applications processor enters Sleep Mode.

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Mode Timing Specifications” on page39 is the required timing parameters for Sleep Mode. Table 15. GPIO Reset Timing Specifications the state of GP[1] before configuring as a Reset to ensure no spurious reset is generated. 2.Time is 512*N Processor Clock Cycles plus up to 4 cycles of the 3.6864MHz input clock. assertion of GPIO Reset. The Lock Detector has a maximum time of 350 µs plus synchronization. Figure 7. Sleep Mode Timing

  • SRAM / ROM / Flash / Synchronous Fast Flash Asynchronous writes (Table17, “SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications” on page39)
  • Variable Latency I/O (Table18, “Variable Latency I/O Interface AC Specifications” on page40)
  • Card Interface (PCMCIA or Compact Flash) (Table19, “Card Interface (PCMCIA or Compact Flash) AC Specifications” on page41)
  • Synchronous Memories (Table20, “Synchronous Memory Interface AC Specifications1” on page42)

Table 16. Sleep Mode Timing Specifications Table 17. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (Sheet 1 of 2)

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Table 18. Variable Latency I/O Interface AC Specifications Table 17. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (Sheet 2 of 2)

Table 19. Card Interface (PCMCIA or Compact Flash) AC Specifications

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  • LCD
  • SSP

Table 20. Synchronous Memory Interface AC Specifications 1 1.These numbers are for a maximum 99.5MHz MEMCLK and 99.5MHz output SDCLK. the 99.5MHz MEMCLK. It can be 99.5MHz at the fastest. 3.This number represents 1/2 SDCLK period. the 132.7MHz MEMCLK at its fastest.

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Boundary scan test signal timing is shown in Table23, “Boundary Scan Test Signal Timing”. Figure 9. SSP AC Timing Definitions Table 22. SSP AC Timing Specifications Table 23. Boundary Scan Test Signal Timing (Sheet 1 of 2)

50pF load indicated in Figure 10. Table 23. Boundary Scan Test Signal Timing (Sheet 2 of 2) Figure 10. AC Test Load