273159-006 INTEL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 86
Technical content
Datasheet sections
- 1.0 Introduction
- 2.2 Burst Bus
- 2.3 Timer Unit
- 2.4 Priority Interrupt Controller
- 2.5 Instruction Set Summary
- 2.6 Faults and Debugging
- 2.7 Low Power Operation
- 2.8 Test Features
- 2.9 Memory-Mapped Control Registers
- 2.10 Data Types and Memory Addressing Modes
- 3.0 Packaging Information
- 3.1 Available Processors and Packages
- 3.2 Pin Descriptions
- 3.2.1 Functional Pin Definitions
- 4.0 Electrical Specifications
- 4.1 Absolute Maximum Ratings
- 4.2 Operating Conditions
- 4.3 Connection Recommendations
- 4.4 VCC5 Pin Requirements (VDIFF)
- 4.5 VCCPLL Pin Requirements
- 5.0 Device Identification
- 6.0 Thermal Specifications
- 6.1 Thermal Management Accessories
- 6.1.1 Heatsinks
- 7.0 Bus Functional Waveforms
- 7.1 Basic Bus States
- 7.2 Boundary-Scan Register
Datasheet sections
- 4 Datasheet
- 9 VCCPLL Lowpass Filter
- 25 CLKIN Waveform
- 26 T OV1 Output Delay Waveform
- 27 T OF Output Float Waveform
- 28 T IS1 and TIH1 Input Setup and Hold Waveform
- 29 T IS2 and TIH2 Input Setup and Hold Waveform
- 30 T IS3 and TIH3 Input Setup and Hold Waveform
- 31 T IS4 and TIH4 Input Setup and Hold Waveform
- 32 T LX, TLXL and TLXA Relative Timings Waveform
- 33 DT/R# and DEN# Timings Waveform
- 34 TCK Waveform
- 36 T BSOV1 and TBSOF1 Output Delay and Output Float Waveform
- 37 T BSOV2 and TBSOF2 Output Delay and Output Float Waveform
- 38 T BSIS2 and TBSIH2 Input Setup and Hold Waveform
- 42 Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus
- 43 Burst Read and Write Transactions Without Wait States, 32-Bit Bus
- 44 Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus
- 45 Burst Read and Write Transactions Without Wait States, 8-Bit Bus
- 46 Burst Read and Write Transactions With 1, 0 Wait States
- 47 Double Word Read Bus Request, Misaligned One Byte From
Datasheet sections
- 48 HOLD/HOLDA Waveform For Bus Arbitration
- 49 Cold Reset Waveform
- 50 Warm Reset Waveform
- 51 Entering the ONCE State
- 52 Bus States with Arbitration
- 53 Summary of Aligned and Unaligned Accesses (32-Bit Bus)
- 54 Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued)
- 7 Pin Description Nomenclature
- 8 Pin Description— External Bus Signals
- 9 Pin Description— Processor Control Signals, Test Signals, and Power
- 10 Pin Description— Interrupt Unit Signals
- 17 Absolute Maximum Ratings
- 19 VDIFF Parameters
- 23 Note Definitions for Table 22, 80960Jx AC Characteristics
- 31 Thermal Resistance for q
- 32 Maximum Ambient Temperature Reference Table
- 37 Maximum T
- 38 Maximum T A at Various Airflows in °C (80960JC)
- 39 Maximum T A at Various Airflows in °C (80960JD)
- 40 Maximum T A at Various Airflows in °C (80960JS)
- 41 Maximum T A at Various Airflows in °C (80960JA/JF)
Datasheet sections
- 6 Datasheet
- 42 Boundary-Scan Register—Bit Order
- 43 Natural Boundaries for Load and Store Accesses
- 44 Summary of Byte Load and Store Accesses
- 45 Summary of Short Word Load and Store Accesses
- 46 Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor Datasheet Product Features I Code Compatible with all 80960Jx Processors I High-Performance Embedded Architecture —One Instruction/Clock Execution —Core Clock Rate is: 1x the Bus Clock for 80960JA/JF/JS 2x the Bus Clock for 80960JD/JC 3x the Bus Clock for 80960JT —Load/Store Programming Model —Sixteen 32-Bit Global Registers —Sixteen 32-Bit Local Registers (8 sets) —Nine Addressing Modes —User/Supervisor Protection Model I Two-Way Set Associative Instruction Cache —80960JA - 2 Kbyte —80960JF/JD - 4 Kbyte —80960JS/JC/JT - 16 Kbyte —Programmable Cache-Locking Mechanism I Direct Mapped Data Cache —80960JA - 1 Kbyte —80960JF/JD - 2 Kbyte —80960JS/JC/JT - 4 Kbyte —Write Through Operation I On-Chip Stack Frame Cache —Seven Register Sets May Be Saved —Automatic Allocation on Call/Return —0-7 Frames Reserved for High-Priority Interrupts I On-Chip Data RAM —1 Kbyte Critical Variable Storage —Single-Cycle Access I 3.3 V Supply V oltage —5 V Tolerant Inputs —TTL Compatible Outputs I High Bandwidth Burst Bus —32-Bit Multiplexed Address/Data —Programmable Memory Configuration —Selectable 8-, 16-, 32-Bit Bus Widths —Supports Unaligned Accesses —Big or Little Endian Byte Ordering I High-Speed Interrupt Controller —31 Programmable Priorities —Eight Maskable Pins plus NMI# —Up to 240 Vectors in Expanded Mode I Two On-Chip Timers —Independent 32-Bit Counting —Clock Prescaling by 1, 2, 4 or 8 —Internal Interrupt Sources I Halt Mode for Low Power I IEEE 1149.1 (JTAG) Boundary Scan Compatibility I Packages —132-Lead Pin Grid Array (PGA) —132-Lead Plastic Quad Flat Pack (PQFP) —196-Ball Mini Plastic Ball Grid Array (MPBGA) Order Number: 273159-006 August 2004
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL ® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY , RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY , OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com. AlertVIEW, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Create & Share, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel Play, Intel Play logo, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel Xeon, Intel XScale, IPLink, Itanium, LANDesk, LanRover, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, RemoteExpress, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside., The Journey Inside, TokenExpress, Trillium, VoiceBrick, Vtune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © Intel Corporation, 2002, 2004
1.0 Introduction
(272483) and may be viewed online at http://developer.intel.com/design/i960/Techinfo/80960JX/. Figure 1. 80960Jx Microprocessor Package Options Table 1. 80960Jx 3.3-V Microprocessor Family variables in this document are now indicated with an "x".
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
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80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor Datasheet 9 2.0 80960Jx Overview The 80960Jx processor offers high performance to cost-sensitive 32-bit embedded applications. The 80960Jx is object code compatible with the 80960 core architecture and is capable of sustained execution at the rate of one instruction per clock. This processor’s features include generous instruction cache, data cache, and data RAM. It also boasts a fast interrupt mechanism and dual-programmable timer units. The 80960Jx processor’s clock multiplication operates the processor core at two or three times the bus clock rate to improve execution performance without increasing the complexity of board designs. Memory subsystems for cost-sensitive embedded applications often impose substantial wait state penalties. The 80960Jx integrates considerable storage resources on-chip to decouple CPU execution from the external bus. The 80960Jx rapidly allocates and de-allocates local register sets during context switches. The processor must flush a register set to the stack only when it saves more than seven sets to its local register cache. A 32-bit multiplexed burst bus provides a high-speed interface to system memory and I/O. A full complement of control signals simplifies the connection of the 80960Jx to external components. The user programs physical and logical memory attributes through memory-mapped control registers (MMRs), an extension not found on the i960 ® Kx, Sx or Cx processors. Physical and logical configuration registers enable the processor to operate with all combinations of bus width and data object alignment. The processor supports a homogeneous byte ordering model. This processor integrates two important peripherals: a timer unit and an interrupt controller. These and other hardware resources are programmed through memory-mapped control registers, an extension to the familiar i960 processor architecture. The timer unit (TU) offers two independent 32-bit timers for use as real-time system clocks and general-purpose system timing. These operate in either single-shot or auto-reload mode and may generate interrupts. The interrupt controller unit (ICU) provides a flexible, low-latency means for requesting interrupts. The ICU provides full programmability of up to 240 interrupt sources into 31 priority levels. The ICU takes advantage of a cached priority table and optional routine caching to minimize interrupt latency. Clock doubling on the 80960JD/JC processors reduces interrupt latency by 40% compared to the 80960JA/JF, and clock tripling on the 80960JT reduces interrupt latency by 20% compared to the 80960JD/JC. Local registers may be dedicated to high-priority interrupts to further reduce latency. Acting independently from the core, the ICU compares the priorities of posted interrupts with the current process priority, off-loading this task from the core. The ICU also supports the integrated timer interrupts. The 80960Jx features a Halt mode designed to support applications where low power consumption is critical. The halt instruction shuts down instruction execution, resulting in a power savings of up to 90 percent. The 80960Jx’s testability features, including ONCE (On-Circuit Emulation) mode and Boundary Scan (JTAG), provide a powerful environment for design debug and fault diagnosis.
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your local Intel representative. Figure 2. 80960Jx Block Diagram
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor Datasheet 11
2.2 Burst Bus
A 32-bit high-performance Bus Controller Unit (BCU) interfaces the 80960Jx to external memory and peripherals. The BCU fetches instructions and transfers data at the rate of up to four 32-bit words per six clock cycles. The external address/data bus is multiplexed. Users may configure the 80960Jx’s bus controller to match an application’s fundamental memory organization. Physical bus width is register-programmed for up to eight regions. Byte ordering and data caching are programmed through a group of logical memory templates and a defaults register. The BCU ’s features include: Multiplexed external bus to minimize pin count 32-, 16-, and 8-bit bus widths to simplify I/O interfaces External ready control for address-to-data, data-to-data and data-to-next-address wait state types Support for big or little endian byte ordering to facilitate the porting of existing program code Unaligned bus accesses performed transparently Three-deep load/store queue to decouple the bus from the core Upon reset, the 80960Jx conducts an internal self-test. Then, before executing its first instruction, it performs an external bus confidence test by performing a checksum on the first words of the initialization boot record (IBR).
2.3 Timer Unit
The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several clock rates and generating interrupts. Each is programmed by use of the TU registers. These memory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shot mode and auto-reload capabilities for continuous operation. Each timer has an independent interrupt request to the 80960Jx’s interrupt controller. The TU may generate a fault when unauthorized writes from user mode are detected. Clock prescaling is supported.
2.4 Priority Interrupt Controller
A programmable interrupt controller manages up to 240 external sources through an 8-bit external interrupt port. Alternatively, the interrupt inputs may be configured for individual edge- or level- triggered inputs. The interrupt unit (IU) also accepts interrupts from the two on-chip timer channels and a single Non-Maskable Interrupt (NMI#) pin. Interrupts are serviced according to their priority levels relative to the current process priority. Low interrupt latency is critical to many embedded applications. As part of its highly flexible interrupt mechanism, the 80960Jx exploits several techniques to minimize latency: Interrupt vectors and interrupt handler routines may be reserved on-chip. Register frames for high-priority interrupt handlers may be cached on-chip. The interrupt stack may be placed in cacheable memory space. Interrupt microcode executes at two or three times the bus frequency for the 80960JD/JC and 80960JT, respectively.
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
12 Datasheet
2.5 Instruction Set Summary
The 80960Jx adds several new instructions to the i960 processor core architecture. The new instructions are: Conditional Move Conditional Add Conditional Subtract Byte Swap Halt Cache Control Interrupt Control Table 2 identifies the instructions that the 80960Jx supports. Refer to the i960® Jx Microprocessor Developer’s Manual (272483) for a detailed description of each instruction.
2.6 Faults and Debugging
The 80960Jx employs a comprehensive fault model. The processor responds to faults by making implicit calls to a fault handling routine. Specific information collected for each fault allows the fault handler to diagnose exceptions and recover appropriately. The processor also has built-in debug capabilities. In software, the 80960Jx may be configured to detect as many as seven different trace event types. Alternatively, mark and fmark instructions may generate trace events explicitly in the instruction stream. Hardware breakpoint registers are also available to trap on execution and data addresses.
2.7 Low Power Operation
Intel fabricates the 80960Jx using an advanced sub-micron manufacturing process. The processor’s sub-micron topology provides the circuit density for optimal cache size and high operating speeds while dissipating modest power. The processor also uses dynamic power management to turn off clocks to unused circuits. Users may program the 80960Jx to enter Halt mode for maximum power savings. In Halt mode, the processor core stops completely while the integrated peripherals continue to function, reducing overall power requirements up to 90 percent. Processor execution resumes from internally or externally generated interrupts.
2.8 Test Features
The 80960Jx incorporates numerous features that enhance the user’s ability to test both the processor and the system to which it is attached. These features include ONCE (On-Circuit Emulation) mode and Boundary Scan (JTAG).
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor Datasheet 13 The 80960Jx provides testability features compatible with IEEE Standard Test Access Port and Boundary Scan Architecture (IEEE Std. 1149.1). One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins (ONCE mode). ONCE mode may also be initiated at reset without using the boundary scan mechanism. ONCE mode is useful for board-level testing. This feature allows a mounted 80960Jx to electrically “remove” itself from a circuit board. This allows for system-level testing in which a remote tester, such as an in-circuit emulator, may exercise the processor system. The provided test logic does not interfere with component or circuit board behavior and ensures that components function correctly, connections between various components are correct, and various components interact correctly on the printed circuit board. The JTAG Boundary Scan feature is an attractive alternative to conventional “bed-of-nails” testing. It may examine connections that might otherwise be inaccessible to a test system.
2.9 Memory-Mapped Control Registers
The 80960Jx, although compliant with the i960 processor core, has the added advantage of memory-mapped, internal control registers not found on the i960 Kx, Sx or Cx processors. These registers give software the interface to easily read and modify internal control registers. Each of these registers is accessed as a memory-mapped, 32-bit register. Access is accomplished through regular memory-format instructions. The processor ensures that these accesses do not generate external bus cycles.
2.10 Data Types and Memory Addressing Modes
As with all i960 processors, the 80960Jx instruction set supports several data types and formats: Bit Bit fields Integer (8-, 16-, 32-, 64-bit) Ordinal (8-, 16-, 32-, 64-bit unsigned integers) Triple word (96 bits) Quad word (128 bits) The 80960Jx provides a full set of addressing modes for C and assembly programming: Two Absolute modes Five Register Indirect modes Index with displacement IP with displacement
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Table 2. 80960Jx Instruction Set † Denotes new 80960 instructions unavailable on 80960CA/CF, 80960KA/KB and 80960SA/SB processors.
3.0 Packaging Information
3.1 Available Processors and Packages
The 80960Jx is offered in various speed grades and three package types. Table 3. 80960Jx Processors Available in 132-Pin PGA Package Table 4. 80960Jx Processors Available in 132-Pin PQFP Package variables in this document are now indicated with an "x".
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available in individual chapters, at http://www.intel.com.
3.2 Pin Descriptions
- Section 3.2.2, “80960Jx 132-Lead PGA Pinout” on page 23.
- Section 3.2.3, “80960Jx 132-Lead PQFP Pinout” on page 27.
- Section 3.2.4, “80960Jx 196-Ball MPBGA Pinout” on page 30.
3.2.1 Functional Pin Definitions
Table 5. 80960Jx Processors Available in Extended Temperature Table 6. 80960Jx Processors Available in 196-Ball MPBGA Package variables in this document are now indicated with an "x".
Table 7. Pin Description Nomenclature I/O Pin may be either an input or output. – Pin must be connected as described. Synchronous. Inputs must meet setup and hold times relative to CLKIN for proper operation. Asynchronous. Inputs may be asynchronous relative to CLKIN.
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Table 8. Pin Description— External Bus Signals (Sheet 1 of 4) number of data transfers during the bus transaction. write — AD[31:2] are driven with the last data value on the AD bus. are driven with the value of A[3:2] from the last data cycle. instruction fetch or load/store) that was executed before entering Halt mode. active HIGH and floats to a high impedance state during a hold cycle (Th). compatibility with existing 80960Kx systems. ADDRESS STROBE indicates a valid address and the start of a new bus access. typically samples ADS# at the end of the cycle. ADDRESS[3:2] comprise a partial demultiplexed address bus. partial word address increments with each assertion of RDYRCV# during a burst. assertion of RDYRCV# during a burst.
conjunction with A[3:2] described above. response to a HOLD request, regardless of prior operating state. access (0). D/C# has the same timing as W/R#. read (0). It is latched on-chip and remains valid during Td cycles. and Tw /Td cycles for a write. DT/R# never changes state when DEN# is asserted. Table 8. Pin Description— External Bus Signals (Sheet 2 of 4)
20 Datasheet
transceivers connected to the data bus. after the final data transfer in a bus cycle. READY/RECOVER indicates that data on AD lines may be sampled or removed. next cycle by inserting a wait state (Tw ). before the processor begins to drive address again. state, resuming control of the address/data and control lines. Table 8. Pin Description— External Bus Signals (Sheet 3 of 4)
h state during reset and while halted as well as during regular operation. access to the bus; see i960® Jx Microprocessor Developer’s Manual (272483). should acquire/relinquish the bus. Table 9. Pin Description— Processor Control Signals, Test Signals, and Power (Sheet 1 of 2) specified relative to a rising CLKIN edge. asserted for a minimum of 15 cycles. STEST is deasserted, the processor performs only the external bus confidence test. When self-test fails, the processor asserts FAIL# and then stops executing. processor on the rising edge; data is clocked out of the processor on the falling edge. of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port. Table 8. Pin Description— External Bus Signals (Sheet 4 of 4)
22 Datasheet
other times, TDO floats. TDO does not float during ONCE mode. Section 4.3, “Connection Recommendations” on page 36. the test logic for IEEE 1149.1 Boundary Scan testing. VCC – POWER pins intended for external connection to a VCC board plane.
5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O
SS – GROUND pins intended for external connection to a VSS board plane. NC – NO CONNECT pins. Do not make any system connections to these pins. Table 10. Pin Description— Interrupt Unit Signals may be programmed to be level (low) or edge (falling) sensitive. are level sensitive in this mode. Unused external interrupt pins should be connected to VCC . NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur. Table 9. Pin Description— Processor Control Signals, Test Signals, and Power (Sheet 2 of 2)
Figure 3. 132-Lead Pin Grid Array Top View-Pins Facing Down variables in this document are now indicated with an "x".
24 Datasheet
Figure 4. 132-Lead Pin Grid Array Bottom View-Pins Facing Up
Table 11. 132-Lead PGA Pinout— In Signal Order NOTE: Do not connect any external logic to pins marked NC (no connect pins).
26 Datasheet
Table 12. 132-Lead PGA Pinout— In Pin Order NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Figure 5. 132-Lead PQFP - Top View variables in this document are now indicated with an "x".
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Table 13. 132-Lead PQFP Pinout— In Signal Order NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Table 14. 132-Lead PQFP Pinout— In Pin Order
1 TRST# 34 BLAST# 67 NC 100 AD8
2 TCK 35 D/C# 68 AD26 101 AD7
3 TMS 36 ADS# 69 AD25 102 AD6
4 HOLD 37 W/R# 70 AD24 103 AD5
5 XINT0# 38 VSS (Core) 71 VSS (I/O) 104 AD4
6 XINT1# 39 VCC (Core) 72 VCC (I/O) 105 VCC (I/O)
7 XINT2# 40 VSS (I/O) 73 VSS (Core) 106 VSS (I/O)
8 XINT3# 41 VCC (I/O) 74 VCC (Core) 107 AD3
9 VCC (I/O) 42 DT/R# 75 AD23 108 AD2
10 VSS (I/O) 43 DEN# 76 AD22 109 AD1
11 XINT4# 44 HOLDA 77 AD21 110 AD0
12 XINT5# 45 ALE 78 AD20 111 VCC (I/O)
13 XINT6# 46 VSS (Core) 79 VSS (I/O) 112 VSS (I/O)
14 XINT7# 47 VCC (Core) 80 VCC (I/O) 113 VCC (Core)
15 NMI# 48 VSS (I/O) 81 AD19 114 VSS (Core)
16 VCC (Core) 49 VCC (I/O) 82 AD18 115 VCC (Core)
17 VSS (Core) 50 LOCK#/ONCE# 83 AD17 116 VSS (Core)
18 NC 51 BSTAT 84 AD16 117 CLKIN
19 NC 52 BE0# 85 VSS (I/O) 118 VSS (CLK)
20 VCC5 53 BE1# 86 VCC (I/O) 119 VCCPLL
21 NC 54 BE2# 87 AD15 120 VCC (CLK)
22 NC 55 BE3# 88 AD14 121 NC
23 FAIL# 56 VSS (I/O) 89 AD13 122 NC
24 ALE# 57 VCC (I/O) 90 AD12 123 VCC (Core)
25 TDO 58 VSS (Core) 91 VSS (Core) 124 VSS (Core)
26 VCC (I/O) 59 VCC (Core) 92 VCC (Core) 125 RESET#
27 VSS (I/O) 60 AD31 93 VSS (I/O) 126 NC
28 WIDTH/HLTD1 61 AD30 94 VCC (I/O) 127 NC
29 VCC (Core) 62 AD29 95 AD11 128 STEST
30 VSS (Core) 63 AD28 96 AD10 129 VCC (I/O)
31 WIDTH/HLTD0 64 VSS (I/O) 97 VSS (I/O) 130 TDI
32 A2 65 VCC (I/O) 98 VCC (I/O) 131 VSS (I/O)
33 A3 66 AD27 99 AD9 132 RDYRCV#
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
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Figure 6. 196-Ball Mini Plastic Ball Grid Array Top View-Balls Facing Down
Figure 7. 196-Ball Mini Plastic Ball Grid Array Bottom View-Balls Facing Up
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Table 15. 196-Ball MPBGA Pinout— In Signal Order (Sheet 1 of 2) NOTE: Do not connect any external logic to pins marked NC (no connect pins).
Table 16. 196-Ball MPBGA Pinout— In Pin Order (Sheet 1 of 2) NOTE: Do not connect any external logic to pins marked NC (no connect pins). Table 15. 196-Ball MPBGA Pinout— In Signal Order (Sheet 2 of 2) NOTE: Do not connect any external logic to pins marked NC (no connect pins).
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Table 16. 196-Ball MPBGA Pinout— In Pin Order (Sheet 2 of 2) NOTE: Do not connect any external logic to pins marked NC (no connect pins).
4.0 Electrical Specifications
4.1 Absolute Maximum Ratings
specification update before finalizing a design. are stress ratings only. Table 17 presents the absolute maximum ratings.
4.2 Operating Conditions
the “Operating Conditions” may affect device reliability. Table 18 presents the operating conditions for the 80960Jx 3.3 V processors. Table 17. Absolute Maximum Ratings Table 18. 80960Jx Operating Conditions † See Section 4.4, “VCC5 Pin Requirements (VDIFF)” on page 36.
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4.3 Connection Recommendations
cause transient power surges. testing), connect the TRST# pin to VSS. Do not connect the TDI, TDO, and TCK pins when the TAP Controller may not be used. Note: Pins identified as NC must not be connected in the system.
4.4 VCC5 Pin Requirements (VDIFF)
pin directly to the 3.3 V VCC plane. Use a regulator that is designed to prevent the voltage differential from exceeding 2.25 V . Figure 8. VCC5 Current-Limiting Resistor
power failure, where the 5 V supply remains on and the 3.3 V supply goes to zero.
4.5 VCCPLL Pin Requirements
VCCPLL must be as short as possible. VCCPLL voltage to exceed VCC by 0.5 V . The VCCPLL low-pass filter recommendation does not promote this problem. Table 19. VDIFF Parameters Figure 9. VCCPLL Lowpass Filter
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Table 20. 80960Jx D.C. Characteristics
- Typical is measured with VCC = 3.3 V and temperature = 25°C.
Table 21. 80960Jx ICC Characteristics (Sheet 1 of 3)
80960 JA/JF/JD
80960 JS/JC/JT
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Table 21. 80960Jx ICC Characteristics (Sheet 2 of 3)
- These pins have internal pullup devices. Typical leakage current is not tested.
- Measured with device operating and outputs loaded to the test condition in Figure 10, “A.C. Test Load” on
one of the worst case instruction mixes with VCC = 3.45 V. This parameter is characterized but not tested.
- ICC Active (Thermal) value is provided for your system’s thermal management. Typical ICC is measured
with VCC =3.3 V and temperature = 25° C. This parameter is characterized but not tested.
- ICC Test (Power modes) refers to the ICC values that are tested when the 80960JD is in Reset mode, Halt
mode or ONCE mode with VCC = 3.45 V. Table 21. 80960Jx ICC Characteristics (Sheet 3 of 3)
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The 80960Jx A.C. timings are based upon device characterization. Table 22. 80960Jx A.C. Characteristics (Sheet 1 of 3) NOTE: See Table 23 on page 45 for note definitions for this table.
Table 22. 80960Jx A.C. Characteristics (Sheet 2 of 3) NOTE: See Table 23 on page 45 for note definitions for this table.
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Table 22. 80960Jx A.C. Characteristics (Sheet 3 of 3) NOTE: See Table 23 on page 45 for note definitions for this table.
Table 23. Note Definitions for Table 22, 80960Jx AC Characteristics
- To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
- Inactive ALE/ALE# refers to the falling edge of ALE and the rising edge of ALE#. For inactive ALE/ALE#
timings, refer to Relative Output Timings in this table.
- A float condition occurs when the output current becomes less than I
designed to be no longer than the valid delay.
- AD[31:0] are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI#
for a minimum of two CLKIN periods to ensure recognition.
- RDYRCV# and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
- RESET# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a
- ONCE# and STEST# must be stable at the rising edge of RESET# for proper operation.
- Guaranteed by design. May not be 100% tested.
10.Relative to falling edge of TCK. Figure 10. A.C. Test Load
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Figure 11. Output Delay or Hold vs. Load Capacitance–80960JS/JC/JT (3.3 V Signals) Figure 12. Output Delay or Hold vs. Load Capacitance–80960JS/JC/JT (5 V Signals)
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Figure 15. TLX vs. AD Bus Load Capacitance–80960JS/JC/JT (5 V Signals) Figure 16. TLX vs. AD Bus Load Capacitance–80960JA/JF/JD Rise and Fall times are identical.
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Figure 19. 80960JD ICC Active (Power Supply) vs. Frequency Figure 20. 80960JD ICC Active (Thermal) vs. Frequency
52 Datasheet
Figure 23. 80960JS ICC Active (Power Supply) vs. Frequency Figure 24. 80960JS ICC Active (Thermal) vs. Frequency
54 Datasheet
Figure 27. TOF Output Float Waveform Figure 28. TIS1 and TIH1 Input Setup and Hold Waveform Figure 29. TIS2 and TIH2 Input Setup and Hold Waveform
1.5 VNMI#
56 Datasheet
Figure 32. TLX , TLXL and TLXA Relative Timings Waveform Figure 33. DT/R# and DEN# Timings Waveform
58 Datasheet
Figure 37. TBSOV2 and TBSOF2 Output Delay and Output Float Waveform Figure 38. TBSIS2 and TBSIH2 Input Setup and Hold Waveform
5.0 Device Identification
5 V supply voltages, and between non-clock-doubled and clock-doubled cores when stepping from
Upon reset, the identifier is placed into the g0 register. register at address FF008710H. The device and stepping letter is also printed on the top side of the product package. Table 24. 80960Jx Device Type and Stepping Reference
60 Datasheet
Figure 39. 80960JS/JC/JT Device Identification Register Fields Table 25. 80960JS/JC/JT Device ID Register Field Definitions Version See Table 26 Indicates major stepping changes. VCC 0 = 3.3 V device Indicates that a device is 3.3 V. (Indicates i960 CPU) Designates type of product. (Indicates Intel) Manufacturer ID assigned by IEEE. Table 26. 80960JS/JC/JT Device ID Model Types
Figure 40. 80960JD Device Identification Register Fields Table 27. 80960JD Device ID Field Definitions Version See Table 24. Indicates major stepping changes. 1 = 5 V device Indicates that a device is 3.3 V. (Indicates i960 CPU) Designates type of product. (Indicates Intel) Manufacturer ID assigned by IEEE. Table 28. 80960JD Device ID Model Types
62 Datasheet
Figure 41. 80960JA/JF Device Identification Register Fields Table 29. 80960JA/JF Device ID Field Definitions Version See Table 30. Indicates major stepping changes. 1 = 5 V device Indicates that a device is 3.3 V. (Indicates i960 CPU) Designates type of product. (Indicates Intel) Manufacturer ID assigned by IEEE. Table 30. 80960JA/JF Device ID Model Types
6.0 Thermal Specifications
range. The case temperature should be measured at the center of the top surface, opposite the pins. Compute P by multiplying ICC from Table 21, “80960Jx ICC Characteristics” on page 39 and VCC . and/or by increasing airflow. Table 31. Thermal Resistance for θCA and θJC Reference Table Table 32. Maximum Ambient Temperature Reference Table
64 Datasheet
Table 33. 132-Lead PGA Package Thermal Characteristics
- This table applies to a PGA device plugged into a socket or soldered directly into a board.
Table 34. 80960JA/JF/JD 196-Ball MPBGA Package Thermal Characteristics
- This table applies to an MPBGA device soldered directly into a board with all VSS connections.
Table 35. 80960JS/JC/JT 196-Ball MPBGA Package Thermal Characteristics
- This table applies to an MPBGA device soldered directly into a board with all VSS connections.
Table 36. 132-Lead PQFP Package Thermal Characteristics
- This table applies to a PQFP device soldered directly into board.
66 Datasheet
Table 37. Maximum TA at Various Airflows in °C (80960JT)
- 0.248 inch high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin
- 0.250 inch high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
Table 38. Maximum TA at Various Airflows in °C (80960JC)
- 0.248 inch high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin
- 0.250 inch high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
Table 39. Maximum TA at Various Airflows in °C (80960JD)
- 0.248 inch high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin
- 0.250 inch high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin spacing).
Table 40. Maximum TA at Various Airflows in °C (80960JS)
- 0.248 inch high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin
- 0.250 inch high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin
68 Datasheet
6.1 Thermal Management Accessories
endorsement or a warranty of the performance of any of the listed products and/or companies.
6.1.1 Heatsinks
2021 West Valley View Lane
60 Audubon Road
- Aavid Thermal Technologies, Inc.
Table 41. Maximum TA at Various Airflows in °C (80960JA/JF)
- 0.248 inch high omnidirectional heatsink (AI alloy 6061, 41 mil fin width, 124 mil center-to-center fin
- 0.250 inch high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 146 mil center-to-center fin
- To address the fact that many of the package prefix variables have changed, all package prefix variables
in this document are now indicated with an "x".
7.0 Bus Functional Waveforms
Figure 42. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus
70 Datasheet
Figure 43. Burst Read and Write Transactions Without Wait States, 32-Bit Bus
Figure 44. Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus
72 Datasheet
Figure 45. Burst Read and Write Transactions Without Wait States, 8-Bit Bus
Figure 46. Burst Read and Write Transactions With 1, 0 Wait States
74 Datasheet
Figure 47. Double Word Read Bus Request, Misaligned One Byte From
Figure 48. HOLD/HOLDA Waveform For Bus Arbitration the processor deasserts HOLDA on the same edge in which it recognizes the deassertion of HOLD.
76 Datasheet
Figure 49. Cold Reset Waveform 10,000 CLKIN periods, for PLL stabilization.
- The processor asserts FAIL# during built-in self-test. When self- test passes, the FAIL# pin is deasserted.The processor also asserts FAIL#
during the bus confidence test. When the bus confidence test passes, FAIL# is deasserted and the processor begins user program execution.
- If the processor fails built-in self-test, it initiates one dummy load bus access. The load address indicates the point of self-test failure.
- Since the bus is idle, hold requests are honored during reset and built-in self-test.
- When selected, built-in self test requires approximately (in CLKIN periods): 393,000 for 80960JT, 580,012 for the 80960JC,
Figure 50. Warm Reset Waveform
4 CLKIN Cycles
15 CLKIN Cycles
78 Datasheet
Figure 51. Entering the ONCE State
- ONCE# mode may be entered prior to the rising edge of RESET#: ONCE# input is not latched until the rising edge of RESET#.
CLKIN may not be allowed to float.
- The ONCE# input may be removed after the processor enters ONCE# Mode.
It must be driven high or low or continue to run.
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor Datasheet 79
7.1 Basic Bus States
The bus has five basic bus states: idle (Ti), address (Ta), wait/data (Tw/Td), recovery (Tr), and hold (Th). During system operation, the processor continuously enters and exits different bus states. Figure 52 shows the five bus states. The bus occupies the idle (Ti) state when no address/data transactions are in progress and when RESET# is asserted. When the processor needs to initiate a bus access, it enters the Ta state to transmit the address. Following a Ta state, the bus enters the Tw/Td state to transmit or receive data on the address/data lines. Assertion of the RDYRCV# input signal indicates completion of each transfer. When data is not ready, the processor may wait as long as necessary for the memory or I/O device to respond. After the data transfer, the bus exits the Tw/Td state and enters the recovery (Tr) state. In the case of a burst transaction, the bus exits the Td state and re-enters the Td/Tw state to transfer the next data word. The processor asserts the BLAST# signal during the last Tw/Td states of an access. Once all data words transfer in a burst access (up to four), the bus enters the Tr state to allow devices on the bus to recover. The processor remains in the Tr state until RDYRCV# is deasserted. When the recovery state completes, the bus enters the Ti state when no new accesses are required. When an access is pending, the bus enters the Ta state to transmit the new address.
80 Datasheet
7.2 Boundary-Scan Register
into the control cell, the associated pin(s) are HIGHZ or selected as input. Figure 52. Bus States with Arbitration
Table 42. Boundary-Scan Register— Bit Order
0 RDYRCV#
1 HOLD I2 5 HOLDA O4 9 AD16 I/O
2 XINT0# I2 6 ALE O5 0 AD15 I/O
3 XINT1# I2 7 LOCK#/
4 XINT2# I2 8 LOCK#/
5 XINT3# I2 9 BSTAT O5 3 AD12 I/O
6 XINT4# I3 0 BE0# O5 4 AD cells Enable
7 XINT5# I3 1 BE1# O5 5 AD11 I/O
8 XINT6# I3 2 BE2# O5 6 AD10 I/O
9 XINT7# I3 3 BE3# O5 7 AD9 I/O
10 NMI# I3 4 AD31 I/O 58 AD8 I/O
11 FAIL# I3 5 AD30 I/O 59 AD7 I/O
12 ALE# O3 6 AD29 I/O 60 AD6 I/O
13 WIDTH/HLTD1 O3 7 AD28 I/O 61 AD5 I/O
14 WIDTH/HLTD0 O3 8 AD27 I/O 62 AD4 I/O
15 A2 O3 9 AD26 I/O 63 AD3 I/O
16 A3 O4 0 AD25 I/O 64 AD2 I/O
17 CONTROL1 Enable cell† 41 AD24 I/O 65 AD1 I/O
18 CONTROL2 Enable cell† 42 AD23 I/O 66 AD0 I/O
19 BLAST# O4 3 AD22 I/O 67 CLKIN I
20 D/C# O4 4 AD21 I/O 68 RESET# I
21 ADS# O4 5 AD20 I/O 69 STEST
22 W/R# O4 6 AD19 I/O
23 DT/R# O4 7 AD18 I/O
† Enable cells are active low. Table 43. Natural Boundaries for Load and Store Accesses
82 Datasheet
Table 44. Summary of Byte Load and Store Accesses Table 45. Summary of Short Word Load and Store Accesses
Table 46. Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)
84 Datasheet
Figure 53. Summary of Aligned and Unaligned Accesses (32-Bit Bus)
Figure 54. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued)
80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor
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