251748-007

251748-007 INTEL | Alldatasheet

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Technical content

Datasheet sections

• 1 Introduction
• 1.1 Terminology
• 1.1.1 Processor Packaging Terminology
• 1.2 References
• 2 Electrical Specifications
• 2.1 System Bus and GTLREF
• 2.2 Power and Ground Pins
• 2.3 Decoupling Guidelines
• 2.3.1 VCC Decoupling
• 2.3.2 System Bus AGTL+ Decoupling
• 2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking
• 2.4 Voltage Identification
• 2.4.1 Phase Lock Loop (PLL) Power and Filter
• 2.5 Reserved, Unused Pins, and TESTHI[12:0]
• 2.6 System Bus Signal Groups
• 2.7 Asynchronous GTL+ Signals
• 2.8 Test Access Port (TAP) Connection
• 2.9 System Bus Frequency Select Signals (BSEL[1:0])
• 2.10 Maximum Ratings
• 2.11 Processor DC Specifications
• 2.11.1 Flexible Motherboard Guidelines (FMB)
• 2.12 AGTL+ System Bus Specifications
• 2.13 System Bus AC Specifications
• 2.14 Processor AC Timing Waveforms
• 3 System Bus Signal Quality Specifications
• 3.1 System Bus Clock (BCLK) Signal Quality Specifications
• 3.2 System Bus Signal Quality Specifications and Measurement Guidelines
• 3.3 System Bus Signal Quality Specifications and Measurement Guidelines
• 3.3.1 Overshoot/Undershoot Guidelines
• 3.3.2 Overshoot/Undershoot Magnitude
• 3.3.3 Overshoot/Undershoot Pulse Duration
• 3.3.4 Activity Factor
• 3.3.5 Reading Overshoot/Undershoot Specification Tables
• 3.3.6 Conformance Determination to Overshoot/Undershoot
• 4 Package Mechanical Specifications
• 4.1 Package Load Specifications
• 4.2 Processor Insertion Specifications
• 4.3 Processor Mass Specifications
• 4.4 Processor Materials
• 4.5 Processor Markings

Intel® Celeron® Processor on

0.13 Micron Process in the

The Intel® Celeron® processor on 0.13 micron process in the 478-pin package expands Intel’s processor family into the value-priced PC market segment. Celeron processors provide the value customer the capability to get onto the Internet affordably, and use educational programs, home- office software and productivity applications. All of the Celeron processors include an integrated L2 cache, and are built on Intel's advanced CMOS process technology. The Celeron processor is backed by over 30 years of Intel experience in manufacturing high-quality, reliable microprocessors. I Available at 2 GHz, 2.10 GHz, 2.20 GHz, 2.30 GHz, 2.40 GHz, 2.50 GHz, 2.60 GHz, 2.70 GHz, and 2.80 GHz I Binary compatible with applications running on previous members of the Intel microprocessor line I System bus frequency at 400 MHz I Rapid Execution Engine: Arithmetic Logic Units (ALUs) run at twice the processor core frequency I Hyper Pipelined Technology I Advanced Dynamic Execution —Very deep out-of-order execution —Enhanced branch prediction I 8-KB Level 1 data cache I Level 1 Execution Trace Cache stores 12K micro-ops and removes decoder latency from main execution loops I 128-KB Advanced Transfer Cache (on-die, full speed Level 2 (L2) cache) with Error Correction Code (ECC) I 144 Streaming SIMD Extensions 2 (SSE2) Instructions I Power Management capabilities —System Management mode —Multiple low-power states I Optimized for 32-bit applications running on advanced 32-bit operating systems November 2003 Document Number: 251748-007

2 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY , RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY , OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel ® Celeron® processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Intel, Celeron, Pentium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2002–2003, Intel Corporation

4 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet

Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet 5 Figures

24 Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD

25 High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD

43 Boxed Processor Fan Heatsink Airspace Keep-Out Requirements

44 Boxed Processor Fan Heatsink Airspace Keep-Out Requirements

6 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet Tables

24 Ringback Specifications for AGTL+ and Asynchronous GTL+ Signals

26 1.525V VID Source Synchronous (400 MHz) AGTL+ Signal Group 27 1.525 V VID Source Synchronous (200 MHz) AGTL+ Signal Group 28 1.525 V VID Common Clock (100 MHz) AGTL+ Signal Group 29 1.525 V VID Asynchronous GTL+, PWRGOOD Input, and TAP Signal

Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet 7

Revision History

-002 Updated document with 2.10 GHz and 2.20 GHz specifications. November 2002 -003 Added 2.30 GHz and 2.40 GHz specifications. March 2003 -004 Added 2.50 GHz and 2.60 GHz specifications. Updated thermal specifications and thermal monitor sections. Updated PROCHOT# pin definition. June 2003 -005 Updated Title page. August 2003 -006 Added 2.70 GHz specifications. Updated Table 20 and Figure 11. September 2003 -007 Added 2.80 GHz specifications. Updated Table 19. November 2003

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Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet 9 Introduction Introduction 1 The Intel® Celeron® processor on 0.13 micron process and in the 478-pin package uses Flip-Chip Pin Grid Array (FC-PGA2) package technology, and plugs into a 478-pin surface mount, Zero Insertion Force (ZIF) socket, referred to as the mPGA478B socket. The Celeron processor on 0.13 micron process maintains the tradition of compatibility with IA-32 software. In this document, the Celeron processor on 0.13 micron process may be referred to as the “Celeron processor” or simply “the processor.” The Celeron processor on 0.13 micron process is designed for uni-processor based Value PC desktop systems. Features of the processor include hyper pipelined technology, a 400 MHz system bus, and an execution trace cache. The 400 MHz system bus is a quad-pumped bus running off a 100 MHz system clock making 3.2 GB/s data transfer rates possible. The execution trace cache is a first level cache that stores approximately 12k decoded micro-operations, which removes the decoder from the main execution path. Additional features include advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2). The advanced dynamic execution improves speculative execution and branch prediction internal to the processor. The advanced transfer cache is a 128 KB, on-die level 2 (L2) cache. The floating point and multi- media units have 128-bit wide registers with a separate register for data movement. SSE2 support includes instructions for double-precision floating point, SIMD integer, and memory management. Power management capabilities such as AutoHALT, Stop-Grant, and Sleep have been retained. The Celeron processor on 0.13 micron process 400 MHz system bus uses a split-transaction, deferred reply protocol. This system bus is not compatible with the P6 processor family bus. The

400 MHz system bus uses Source-Synchronous Transfer (SST) of address and data to improve

throughput by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock, and is referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3.2 GB/s. Intel will be enabling support components for the Celeron processor on 0.13 micron process including a heatsink, heatsink retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly can be completed from the top of the motherboard and should not require any special tooling. The processor system bus uses a variant of GTL+ signalling technology called Assisted Gunning Transceiver Logic (AGTL+) signalling technology. The processor includes an address bus powerdown capability which removes power from the address and data pins when the system bus is not in use. This feature is always enabled on the processor.

1.1 Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating that the signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

10 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet Introduction “System Bus” refers to the interface between the processor and system core logic (the chipset components). The system bus is a multiprocessing interface to processors, memory, and I/O.

1.1.1 Processor Packaging Terminology

The following are commonly used terms:

• Intel® Celeron® processor on 0.13 micron process and in the 478-pin package (also referred as the Intel® Celeron® processor on 0.13 micron process or processor) — 0.13 micron processor core in the 478-pin FC-PGA2 package with a 128-KB L2 cache.
• Intel/Ga3 Celeron/Ga3 processor in the 478-pin package — 0.18 micron processor core in the 478-pin FC-PGA2 package with a 128-KB L2 cache.
• Intel/Ga3 Pentium/Ga3 4 processor with 512-KB L2 cache on 0.13 micron process — 0.13 micron process version of Pentium 4 processor in the 478-pin FC-PGA2 package with a 512-KB L2 cache.
• Processor — For this document, the term processor means Celeron processor on 0.13 micron process.
• Keep-Out Zone — The area on or near the processor that system design can not use. This area must be kept free of all components to make room for the processor package, retention mechanism, heatsink, and heatsink clips.
• Intel® 850 chipset — Chipset that supports RDRAM* memory technology for Celeron processor on 0.13 micron process.
• Intel® 845 chipset — Chipset that supports PC133 and DDR memory technology for the Celeron processor on 0.13 micron process.
• Intel® 845G chipset — Chipset with embedded graphics that supports DDR memory technology for the Celeron processor on 0.13 micron process.
• Intel® 845E chipset — Chipset that supports DDR memory technology for the Celeron processor on 0.13 micron process.
• Processor core — Celeron processor on 0.13 micron process core die with integrated L2 cache.
• FC-PGA2 package — Flip-Chip Pin Grid Array package with 50-mil pin pitch and Integrated Heat Spreader.
• mPGA478B socket — Surface mount, 478 pin, Zero Insertion Force (ZIF) socket with 50-mil pin pitch. The socket mates the processor to the system board.
• Integrated heat spreader — The surface used to make contact between a heatsink or other thermal solution and the processor. Abbreviated IHS.
• Retention mechanism — The structure mounted on the system board that provides support and retention of the processor heatsink.

1.2 References

Table 1. References CK408 Clock Design Guidelines Contact Intel field representative.

12 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet Introduction This page is intentionally left blank.

Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet 13 Electrical Specifications Electrical Specifications 2

2.1 System Bus and GTLREF

Most Celeron processor on 0.13 micron process system bus signals use Assisted Gunning Transceiver Logic (AGTL+) signalling technology. As with the P6 family of microprocessors, this signalling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Like the Intel/Ga3 Pentium/Ga3 4 processor, the termination voltage level for the Celeron processor on 0.13 micron process AGTL+ signals is VCC, which is the operating voltage of the processor core. The use of a termination voltage that is determined by the processor core allows better voltage scaling on the system bus for Celeron processor on 0.13 micron process. Because of the speed improvements to data and address bus, signal integrity and platform design methods have become more critical than with previous processor families. Design guidelines for the Celeron processor on 0.13 micron process system bus are described in the appropriate Platform Design Guide (refer to Table 1). The AGTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine whether a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board. Termination resistors are provided on the processor silicon, and are terminated to the processor core voltage (VCC). Intel chipsets also provide on-die termination, thus eliminating the need to terminate most AGTL+ signals on the system board. Some AGTL+ signals do not include on-die termination and must be terminated on the system board. See Table 4 for details regarding these signals. The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the system bus, including trace lengths, is highly recommended when designing a system.

2.2 Power and Ground Pins

For clean on-chip power distribution, the Celeron processor on 0.13 micron process has 85 VCC (power) and 181 VSS (ground) inputs. All power pins must be connected to VCC, and all VSS pins must be connected to a system ground plane.The processor VCC pins must be supplied with the voltage defined by the VID (V oltage ID) pins and the loadline specifications (see Figure 4).

2.3 Decoupling Guidelines

Because of the large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 7. Failure to do so can result in timing violations and/or affect the long term reliability of the processor. For further information and design guidelines, refer to Table 1 for the appropriate Platform Design Guide, and the Intel /Ga3 Pentium/Ga3 4 Processor VR-Down Design Guidelines.

14 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet Electrical Specifications

2.3.1 VCC Decoupling

Regulator solutions must provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on or is entering or exiting low power states must be provided by the voltage regulator solution (VR). For design guidelines, refer to Table 1 for the appropriate Platform Design Guide, and to the Intel /Ga3 Pentium/Ga3 4 Processor VR-Down Design Guidelines.

2.3.2 System Bus AGTL+ Decoupling

The Celeron processor on 0.13 micron process integrates signal termination on the die and incorporates high frequency decoupling capacitance on the processor package. Decoupling must also be provided by the system motherboard for proper AGTL+ bus operation. For more information, refer to the appropriate platform design guide listed in Table 1.

2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly control the system bus interface speed as well as the core frequency of the processor. As in previous generation processors, the Celeron processor on 0.13 micron process core frequency is a multiple of the BCLK[1:0] frequency. Like the Celeron processor in the 478-pin package, the Celeron processor on 0.13 micron process uses a differential clocking implementation. For more information on clocking, refer to the CK408 Clock Design Guidelines and also the CK00 Clock Synthesizer/Driver Design Guidelines.

2.4 Voltage Identification

can work with all supported frequencies. /Ga3 Pentium/Ga3 4 Processor VR-Down Design Guidelines for more details. Power source characteristics must be stable whenever the supply to the voltage regulator is stable. platform design guide listed in Table 1 for implementation details. requirements of the VCCVID pin. Table 2. VCCVID Pin Voltage Requirements

1. This specification applies to both static and transient components. The rising edge of VCCVID must be

Figure 1. VCCVID Pin Voltage and Current Requirements

1.2 V + 10%

1.2 V - 5%

2.4.1 Phase Lock Loop (PLL) Power and Filter

must be low pass filtered from VCC. A typical filter topology is shown in Figure 2.

• < 0.2 dB gain in pass band
• < 0.5 dB attenuation in pass band < 1 Hz
• > 34 dB attenuation from 1 MHz to 66 MHz
• > 28 dB attenuation from 66 MHz to core frequency The filter requirements are illustrated in Figure 3. For recommendations on implementing the filter, refer to the appropriate Platform Design Guide listed in Table 1.

Table 3. Voltage Identification Definition

1. No specification for frequencies beyond fcore (core frequency).
2. fpeak, if existent, should be less than 0.05 MHz.

Figure 2. Typical VCCIOPLL, VCCA and VSSA Power Distribution Figure 3. Phase Lock Loop (PLL) Filter Requirements

1 MHz 66 MHz fcorefpeak1 HzDC

18 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet Electrical Specifications

2.5 Reserved, Unused Pins, and TESTHI[12:0]

All RESERVED pins must remain unconnected. Connection of these pins to VCC, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 5 for a processor pin listing, and the location of all RESERVED pins. For reliable operation, always connect unused inputs or bidirectional signals that are not terminated on the die to an appropriate signal level. Note that on-die termination has been included on the Celeron processor on 0.13 micron process to allow signals to be terminated within the processor silicon. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Table 4 lists details on AGTL+ signals that do not include on-die termination. Unused active high inputs should be connected through a resistor to ground (VSS). Refer to the appropriate platform design guide in Table 1 for the appropriate resistor values. Unused outputs can be left unconnected. However, this may interfere with some TAP functions, may complicate debug probing, and may prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will allow for system testability. For unused AGTL+ input or I/O signals that do not have on-die termination, use pull-up resistors of the same value in place of the on-die termination resistors (R TT). See Table 15. The TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die termination. Inputs and used outputs must be terminated on the system board. Unused outputs can be terminated on the system board or can be left unconnected. Signal termination for these signal types is discussed in the appropriate Platform Design Guide listed in Table 1, and the ITP700 Debug Port Design Guide. The TESTHI pins should be tied to the processor VCC using a matched resistor with a resistance value within ± 20% of the impedance of the board transmission line traces. For example, if the trace impedance is 50 Ω , then a value between 40 Ω and 60 Ω is required. The TESTHI pins may use individual pull-up resistors, or may be grouped together as follows. A matched resistor should be used for each group: 1. TESTHI[1:0] 2. TESTHI[5:2] 3. TESTHI[10:8] 4. TESTHI[12:11] Additionally, if the ITPCLKOUT[1:0] pins are not used (refer to Section 5.2), they can be connected individually to VCC using matched resistors, or can be grouped with TESTHI[5:2] with a single matched resistor. If they are being used, individual termination with 1 kΩ resistors is required. Tying ITPCLKOUT[1:0] directly to VCC or sharing a pull-up resistor to VCC will prevent use of debug interposers. This implementation is strongly discouraged for system boards that do not implement an inboard debug port. As an alternative, group2 (TESTHI[5:2]), and the ITPCLKOUT[1:0] pins may be tied directly to the processor VCC. This has no impact on system functionality. TESTHI[0] and TESTHI[12] may also be tied directly to the processor VCC if resistor termination is a problem, but matched resistor termination is recommended. In the case of the ITPCLKOUT[1:0] pins, a direct tie to VCC is strongly discouraged for system boards that do not implement an onboard debug port.

2.6 System Bus Signal Groups

as well as the AGTL+ I/O group when driving. synchronous, and asynchronous. Table 4. System Bus Pin Groups

1. Refer to Section 5.2 for signal descriptions.
2. These AGTL+ signals do not have on-die termination. Refer to Section 2.5 and the appropriate Platform Design

Guide listed in Table 1 for termination requirements and further details.

1. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration

options. See Section 7.1 for details.

1. These signal groups are not terminated by the processor. Refer to Section 2.5, the ITP700 Debug Port Design
2. In processor systems where there is no debug port implemented on the system board, these signals are used

2.7 Asynchronous GTL+ Signals

timing requirements for entering and leaving the low power states.

2.8 Test Access Port (TAP) Connection

of the appropriate voltage level. Similar considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be required, with each driving a different voltage level.

2.9 System Bus Frequency Select Signals (BSEL[1:0])

and clock synthesizer. All agents must operate at the same frequency. at their specified system bus frequency. Table 5. BSEL[1:0] Frequency Table for BCLK[1:0]

2.10 Maximum Ratings

the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability. these signals are listed in Table 10. DC specifications for these signal groups are listed in Table 11. input voltages. Care should be taken to read all notes associated with each parameter.

2.11.1 Flexible Motherboard Guidelines (FMB)

specifications for future processors may differ. Multiple VID processors will be shipped either at VID=1.475 V , VID=1.500 V , or VID=1.525 V . example for the processors through 2.40 GHz, the Icc-max would be the one at VID=1.525 V . Table 6. Processor DC Absolute Maximum Ratings

1. Contact Intel for storage requirements in excess of one year.
2. This rating applies to any processor pin.

Table 7. Voltage and Current Specifications

2 GHz

2.10 GHz

2.20 GHz

2.30 GHz

2.40 GHz

2.50 GHz

2.60 GHz

2.70 GHz

2.80 GHz

2 GHz 12

1. Unless otherwise noted, all specifications in this table are based on the latest silicon measurements available
2. These voltages are targets only. A variable voltage source should exist on systems in the event that a different

with the minimum being defined according to current consumption at that voltage.

1. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE pins at the

noise from the system is not coupled in the scope probe.

1. Refer to Table 8 and Figure 4 for the minimum, typical, and maximum VCC allowed for a given current. The

can affect the long term reliability of the processor.

1. VCC_MIN is defined at ICC_MAX.
2. FMB is the flexible motherboard guideline. These guidelines are estimates based on the data available at the

time of publication. FMB2 Guideline is calculated at VID of 1.525 V.

1. FMB1 guidelines intend to support both the Celeron processor on 0.13 micron process, and the Celeron pro-

cessor in the 478-pin package.

1. The maximum instantaneous current the processor will draw while the thermal control circuit is active as in-

dicated by the assertion of PROCHOT# is the same as the maximum I CC for the processor.

1. These specifications apply to processor with maximum VID setting 1.525 V.
2. Also applies to processors with fixed VID=1.525 V
3. The current specified is also for the AutoHALT State and applies to all frequencies.
4. ICC Stop-Grant and ICC Sleep are specified at VCC_MAX.

Table 8. VCC Static and Transient Tolerance (Sheet 1 of 2)

1. The loadline specification includes both static and transient limits.
2. This loadline figure applies to any VID setting. Refer to Table 8 for the specific offsets from VID voltage.
3. The loadlines specify voltage limits at the die measured at VCC_SENSE and VSS_SENSE pins. Voltage

and VR implementation details.

1. Adherence to this loadline specification for the Celeron processor on 0.13 micron process is required to

ensure reliable processor operation.

1. The loadline specifications include both static and transient limits.
2. This table is intended to aid in reading discrete points on the following loadline figure and applies to any VID
3. The loadlines specify voltage limits at the die measured at VCC_SENSE and VSS_SENSE pins. Voltage reg-

and VR implementation details.

1. Adherence to this loadline specification for the Celeron processor on 0.13 micron process is required to en-

sure reliable processor operation. Figure 4. VCC Static and Transient Tolerance Table 8. VCC Static and Transient Tolerance (Sheet 2 of 2)

Table 9. System Bus Differential BCLK Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the
3. VHavg is the statistical average of the VH measured by the oscilloscope.
4. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
5. VHavg can be measured directly using “Vtop” on Agilent scopes and “High” on Tektronix scopes.
6. ∆VCROSS is defined as the total variation of all crossing voltages as defined in note 2.
7. Overshoot is defined as the absolute value of the maximum voltage.
8. Undershoot is defined as the absolute value of the minimum voltage.
9. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback

and the maximum Falling Edge Ringback.

1. Threshold Region is defined as a region entered around the crossing point voltage in which the differential

receiver switches. It includes input threshold hysteresis. Table 10. AGTL+ Signal Group DC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. The VCC referred to in these specifications is the instantaneous VCC.
4. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
5. VIH and V OH may experience excursions above VCC. However, input signal drivers must comply with the

signal quality specifications in this chapter.

1. Vol max of 0.450 V is guaranteed when driving into a test load of 50 Ω as indicated in Figure 6.
2. Leakage to VSS with pin held at VCC.
3. Leakage to VCC with Pin held at 300 mV.
4. Refer to processor I/O Buffer Models for I/V characteristics.

Table 11. Asynchronous GTL+ Signal Group DC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the

signal quality specifications in Chapter 3, “System Bus Signal Quality Specifications”.

1. The VCC referred to in these specifications refers to instantaneous VCC.
2. This specification applies to the asynchronous GTL+ signal group.
3. All outputs are open-drain.
4. The maximum output current is based on maximum current handling capability of the buffer and is not spec-

ified into the test load shown in Figure 6.

1. VOL max of 0.270 V is guaranteed when driving into a test load of 50 Ω as indicated in Figure 6 for the Asyn-
2. Leakage to VSS with pin held at VCC.
3. Leakage to VCC with pin held at 300 mV.
4. Refer to the processor I/O Buffer Models for I/V characteristics.

Table 12. PWRGOOD and TAP Signal Group DC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VHYS represents the amount of hysteresis, nominally centered about 1/2 VCC for all TAP inputs.
3. The VCC referred to in these specifications refers to instantaneous VCC.
4. All outputs are open-drain.
5. The TAP signal group must comply with the signal quality specifications in Chapter 3, “System Bus Signal Quality
6. The maximum output current is based on maximum current handling capability of the buffer and is not spec-

ified into the test load shown in Figure 6.

1. Vol max of 0.320 V is guaranteed when driving into a test load of 50 Ω as indicated in Figure 6 for the TAP
2. Leakage to VSS with pin held at VCC.
3. Leakage to VCC with pin held at 300 mV
4. Refer to I/O Buffer Models for I/V characteristics.

1. See Table 13 for range of RON.
2. The VCC referred to in this figure is the instantaneous VCC.
3. Refer to the ITP700 Debug Port Design Guide and the Platform Design Guide for the value of Rext.

Table 13. ITPCLKOUT[1:0] DC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. See Figure 5 for ITPCLKOUT[1:0] output buffer diagram.

Figure 5. ITPCLKOUT[1:0] Output Buffer Diagram Table 14. BSEL [1:0] and VID[4:0] DC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. Leakage to VSS with pin held at 2.50 V.

2.12 AGTL+ System Bus Specifications

resistors are integrated into the processor silicon. with a reference voltage called GTLREF (known as VREF in previous documentation). Table 15. AGTL+ Bus Voltage Definitions

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The tolerances for this specification have been stated generically to enable the system designer to calculate

the minimum and maximum values across the range of VCC.

1. GTLREF should be generated from VCC by a voltage divider of 1% tolerance resistors, or 1% tolerance

matched resistors. Refer to the appropriate Platform Design Guide listed in Table 1 for implementation details.

1. The VCC referred to in these specifications is the instantaneous VCC.
2. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Refer to processor

I/O buffer models for I/V characteristics.

1. COMP resistance must be provided on the system board with 1% tolerance resistors. See the appropriate

Platform Design Guide for implementation details.

2.13 System Bus AC Specifications

The processor system bus timings specified in this section are defined at the processor silicon. See Chapter 5 for the Celeron processor on 0.13 micron process pin signal definitions. AGTL+ layout guidelines are available in the appropriate Platform Design Guide (see Table 1). Care should be taken to read all notes associated with a particular timing parameter. Table 16. System Bus Differential Clock Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The period specified here is the average period. A given period may vary from this specification as governed

by the period stability specification (T2).

1. For the clock jitter specification, refer to the CK408 Clock Design Guidelines.
2. In this context, period stability is defined as the worst case timing difference between successive crossover
3. Slew rate is measured between the 35% and 65% points of the clock swing (V L to VH).

Table 17. System Bus Common Clock AC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (V CROSS) of the
4. Valid delay timings for these signals are specified into the test circuit described in Figure 6 and with GTLREF
5. Specification is for a minimum swing defined between AGTL+ V IL_MAX to V IH_MIN. This assumes an edge

rate of 0.4 V/ns to 4.0 V/ns.

1. RESET# can be asserted asynchronously, but must be deasserted synchronously.
2. This should be measured after VCC and BCLK[1:0] become stable .
3. Maximum specification applies only while PWRGOOD is asserted.

Table 18. System Bus Source Synch AC Specifications AGTL+ Signal Group

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source synchro-

synchronous AGTL+ signal timings are referenced to GTLREF at the processor core.

1. Unless otherwise noted, these specifications apply to both data and address timings.
2. Valid delay timings for these signals are specified into the test circuit described in Figure 6 and with GTLREF.
3. This specification represents the minimum time the data or address will be valid before its strobe. Refer to
4. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the

appropriate Platform Design Guide listed in Table 1.

1. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate
2. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each
3. The rising edge of ADSTB# must come approximately 1/2 BCLK period (5 ns) after the falling edge of AD-
4. For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively.
5. The second data strobe (falling edge of DSTBN#) must come approximately 1/4 BCLK period (2.5 ns) after

must come approximately 3/4 BCLK period (7.5 ns) after the first falling edge of DSTBp#.

1. This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe.

Table 19. Miscellaneous Signals AC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All AC timings for the Asynch GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage.
3. These signals may be driven asynchronously.
4. See Section 7.2 for additional timing requirements for entering and leaving the low power states.
5. Refer to the PWRGOOD definition for more details regarding the behavior of this signal.
6. Length of assertion for PROCHOT# does not equal TCC activation time. The processor requires time to en-

specification applies to PROCHOT# as both an input and an output. Table 20. System Bus AC Specifications (Reset Conditions)

1. Before the deassertion of RESET#.
2. After clock that deasserts RESET#.

Table 21. TAP Signals AC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*VCC at the processor pins. All TAP

signal timings (TMS, TDI, etc) are referenced at 0.5*VCC at the processor pins.

1. Rise and fall times are measured from the 20% to 80% points of the signal swing.
2. It is recommended that TMS be asserted while TRST# is being deasserted.
3. Referenced to the rising edge of TCK.
4. Specifications for a minimum swing defined between TAP VT- to VT+. This assumes a minimum edge rate
5. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.

2.14 Processor AC Timing Waveforms

1. All common clock AC timings for AGTL+ signals are referenced to the Crossing V oltage

timings are referenced at GTLREF at the processor core.

1. All source synchronous AC timings for AGTL+ signals are referenced to their associated

AGTL+ signal timings are referenced at GTLREF at the processor core silicon.

1. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at V CROSS. All

AGTL+ strobe signal timings are referenced at GTLREF at the processor core silicon.

1. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*VCC at the

The circuit used to test the AC specifications is shown in Figure 6. Table 22. ITPCLKOUT[1:0] AC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. This delay is from rising edge of BCLK0 to the falling edge of ITPCLK0.

Figure 6. AC Test Circuit

Figure 13. Source Synchronous 4X Timings

40 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet Electrical Specifications This page is intentionally left blank.

acceptable signal quality across all systematic variations encountered in volume manufacturing. through simulation and for interpreting results for signal quality measurements of actual designs.

3.1 System Bus Clock (BCLK) Signal Quality

bus clock at the processor core silicon. Table 23. BCLK Signal Quality Specifications

1. Unless otherwise noted, all specifications in this table apply to all Celeron processor on 0.13 micron process
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute

ification is an absolute value.

3.2 System Bus Signal Quality Specifications and

available in the Platform Design Guideline. Table 29. Figure 22 shows the system bus ringback tolerance for low-to-high transitions, and Figure 23 shows ringback tolerance for high-to-low transitions. Figure 21. BCLK Signal Integrity Waveform Table 24. Ringback Specifications for AGTL+ and Asynchronous GTL+ Signals Groups

1. All signal integrity specifications are measured at the processor silicon.
2. Unless otherwise noted, all specifications in this table apply to all Celeron processor on 0.13 micron process
3. Specifications are for the edge rate of 0.3 – 4.0 V/ns.
4. All values specified by design characterization.
5. See Section 3.3 for maximum allowable overshoot duration.
6. Ringback between GTLREF + 10% and GTLREF – 10% is not supported.
7. Intel recommends that simulations not exceed a ringback value of GTLREF ± 200 mV to allow margin for

other sources of system noise.

Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet 45 System Bus Signal Quality Specifications

3.3 System Bus Signal Quality Specifications and

3.3.1 Overshoot/Undershoot Guidelines

Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage (or below VSS) as shown in Figure 26. The overshoot guideline limits transitions beyond VCC or VSS because of the fast signal edge rates. The processor can be damaged by repeated overshoot or undershoot events on any input, output, or I/O buffer if the charge is large enough (i.e., if the over/undershoot is great enough). Determining the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse direction, and the activity factor (AF). Permanent damage to the processor is the likely result of excessive overshoot/undershoot. When performing simulations to determine impact of overshoot and undershoot, ESD diodes must be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide overshoot or undershoot protection. ESD diodes modeled within Intel I/O buffer models do not clamp undershoot or overshoot, and will yield correct simulation results. If other I/O buffer models are being used to characterize the Celeron processor on 0.13 micron process system bus, care must be taken to ensure that ESD models do not clamp extreme voltage levels. Intel I/O buffer models also contain I/O capacitance characterization. Therefore, removing the ESD diodes from an I/O buffer model will impact results and may yield excessive overshoot/undershoot.

3.3.2 Overshoot/Undershoot Magnitude

Magnitude describes the maximum potential difference between a signal and its voltage reference level. For the Celeron processor on 0.13 micron process, both are referenced to VSS. It is important to note that overshoot and undershoot conditions are separate, and their impact must be determined independently. Overshoot/undershoot magnitude levels must observe the absolute maximum specifications listed in Table 26 through Table 29. These specifications must not be violated at any time regardless of bus activity or system state. Within these specifications are threshold levels that define different allowed pulse durations. Provided that the magnitude of the overshoot/undershoot is within the absolute maximum specifications, the pulse magnitude, duration and activity factor must all be used to determine whether the overshoot/undershoot pulse is within specifications.

3.3.3 Overshoot/Undershoot Pulse Duration

Pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/ undershoot reference voltage (maximum overshoot = 1.800 V , maximum undershoot = -0.335 V). The total time could encompass several oscillations above the reference voltage. Multiple overshoot/undershoot pulses within a single overshoot/undershoot event may have to be measured to determine the total pulse duration. Note: Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot pulse duration.

46 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet System Bus Signal Quality Specifications

3.3.4 Activity Factor

Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a clock. Since the highest frequency of assertion of any signal is every other clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs EVERY OTHER clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs one time in every 200 clock cycles. For source synchronous signals (address, data, and associated strobes), the activity factor is in reference to the strobe edge because the highest frequency of assertion of any source synchronous signal is every active edge of its associated strobe. An AF = 1 indicates that the specific overshoot (undershoot) waveform occurs every strobe cycle. The specifications provided in Table 26 through Table 29 show the maximum pulse duration allowed for a given overshoot/undershoot magnitude at a specific activity factor. Each table entry is independent of all others, meaning that the pulse duration reflects the existence of overshoot/ undershoot events of that magnitude ONLY . A platform with an overshoot/undershoot that just meets the pulse duration for a specific magnitude where the AF < 1, means that there can be no other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the event occurs at all times and no other events can occur). Notes: 1. Activity factor for AGTL+ signals is referenced to BCLK[1:0] frequency. 2. Activity factor for source synchronous (2X) signals is referenced to ADSTB[1:0]#. 3. Activity factor for source synchronous (4X) signals is referenced to DSTBP[3:0]# and DSTBN[3:0]#.

3.3.5 Reading Overshoot/Undershoot Specification Tables

The overshoot/undershoot specification for the Celeron processor on 0.13 micron process is not a simple single value. Many factors are needed to determine what the over/undershoot specification is. In addition to the magnitude of the overshoot, the following parameters must also be known: the width of the overshoot (as measured above VCC), and the activity factor (AF). To determine the allowed overshoot for a particular overshoot event, the following must be done: 1. Determine the VID voltage, System Bus speed, and signal group that a particular signal falls into and use the appropriate table. 2. Determine the magnitude of the overshoot (relative to VSS). 3. Determine the activity factor (how often does this overshoot occur?). 4. Next, from the appropriate specification table, determine the maximum pulse duration (in nanoseconds) allowed. 5. Compare the specified maximum pulse duration to the signal being measured. If the pulse duration measured is less than the pulse duration shown in the table, then the signal meets the specifications. The above procedure is similar for undershoot after the undershoot waveform has been converted to look like an overshoot. Undershoot events must be analyzed separately from overshoot events because the two are mutually exclusive.

3.3.6 Conformance Determination to Overshoot/Undershoot

1. Ensure no signal ever exceeds VCC or –0.25 V
2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot
3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse

(measured time < specifications) in the table (where AF=1), then the system passes. The following notes apply to Table 26 through Table 29.

1. Absolute Maximum Overshoot magnitude of 1.80 V must never be exceeded.
2. Absolute Maximum Overshoot is measured relative to VSS, and Pulse Duration of overshoot

is measured relative to VCC.

1. Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to
2. Ringback below VCC can not be subtracted from overshoots/undershoots.

Lesser undershoot does not allocate longer or larger overshoot.

1. OEMs are strongly encouraged to follow the Intel provided layout guidelines.
2. All values are specified by design characterization.

Table 26. 1.525V VID Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/

1. These specifications are measured at the processor core silicon.

1. These specifications are measured at the processor core silicon.

Table 27. 1.525 V VID Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/ Table 28. 1.525 V VID Common Clock (100 MHz) AGTL+ Signal Group Overshoot/

1. These specifications are measured at the processor core silicon.

Table 29. 1.525 V VID Asynchronous GTL+, PWRGOOD Input, and TAP Signal Group

1. These specifications are measured at the processor core silicon.

Figure 26. Maximum Acceptable Overshoot/Undershoot Waveform

50 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet System Bus Signal Quality Specifications This page is intentionally left blank.

Guidelines for complete details on the mPGA478B socket.

1. Unless otherwise specified, the following drawings are dimensioned in millimeters.
2. Figures and drawings labeled as “Reference Dimensions” are provided for informational

parentheses without tolerances are reference dimensions.

1. Drawings are not to scale.

Figure 27. Exploded View of Processor Components on a System Board

Figure 28. Processor Package Table 30. Description Table for Processor Dimensions

0.13 micron process may contain pin side capacitors mounted to the processor package. datum set to the bottom of the processor substrate.

1. Pin plating consists of 0.2 micrometers Au over 2.0 micrometer Ni.
2. 0.254 mm diametric true position, pin-to-pin.

Figure 29. Processor Cross-Section and Keep-In Figure 30. Processor Pin Detail

0.3 MAX

1. Flatness is specified as overall, not per unit of length.
2. All Dimensions are in millimeters.

4.1 Package Load Specifications

mechanical reference or load bearing surface for thermal solutions. Figure 31. IHS Flatness Specification Table 31. Package Dynamic and Static Load Specifications

1. This specification applies to a uniform compressive load.
2. This is the maximum static force that can be applied by the heatsink and clip to maintain

the heatsink and processor interface.

1. Dynamic loading specifications are defined assuming a maximum duration of 11 ms and

4.2 Processor Insertion Specifications

4.3 Processor Mass Specifications

4.4 Processor Materials

material properties are described in Table 33.

4.5 Processor Markings

Celeron processor on 0.13 micron process. Table 32. Processor Mass Table 33. Processor Material Properties Figure 32. Processor Markings

Figure 33. Processor Pinout Coordinates (Top View, Left Side)

Figure 34. Processor Pinout Coordinates (Top View, Right Side)

58 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet Package Mechanical Specifications This page is intentionally left blank.

5.1 Processor Pin Assignments

Table 35. Table 34 is a listing of all processor pins ordered alphabetically by pin name. Table 35 is a listing of all processor pins ordered by pin number.

Table 34. Pin Listing by Pin Name

1. The PROCHOT# signal is input/output only on

Table 35. Pin Listing by Pin Number

1. The PROCHOT# signal is input/output only on

5.2 Alphabetical Signals Reference

Table 36. Signal Description (Sheet 1 of 8) phase 1 of the address phase, these pins transmit the address of a transaction. on 0.13 micron process. A[35:3]# are protected by parity signals AP[1:0]#. is supported only in real mode. assertion of the corresponding Input/Output Write bus transaction.

signal any bus condition that prevents reliable future operation. system bus and attempt completion of their bus queue and IOQ entries. cannot issue any new transactions. BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. is used by debug tools to request debug operation of the processor. Debug Port Design Guide for more detailed information. Platform Design Guide for termination requirements. requests are completed, then releases the bus by deasserting BPRI#. NOTE: This signal does not have on-die termination and must be terminated. BSEL[1:0] (Bus Select) are used to select the processor input clock frequency. Section 2.9 and the appropriate platform design guidelines. COMP[1:0] must be terminated on the system board using precision resistors. Table 36. Signal Description (Sheet 2 of 8)

data signals to data strobes and DBI#. corresponding data group is inverted and therefore sampled active high. signals for that particular sub-phase for that 16-bit group. pins on all processor system bus agents. connect the appropriate pins of all processor system bus agents. Table 36. Signal Description (Sheet 3 of 8)

appropriate pins of all processor system bus agents. Data strobe used to latch in D[63:0]#. Data strobe used to latch in D[63:0]#. compatibility with systems using MS-DOS*-type floating-point error reporting. Design Guide for details on implementation. IERR# asserted until the assertion of RESET#. Table 36. Signal Description (Sheet 4 of 8)

floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. assertion of the corresponding Input/Output Write bus transaction. pins of all processor system bus agents. processor executes its Built-in Self-Test (BIST). properly. Refer to Section 2.5 for additional details and termination requirements. port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals. ® Pentium® processor. Both signals are asynchronous. first transaction to the end of the last transaction. the bus locked operation and ensure the atomicity of lock.

• Enabled or disabled.
• Asserted, if configured, for internal errors along with IERR#.
• Asserted, if configured, by the request initiator of a bus transaction after it observes an error.
• Asserted by any bus agent when it observes an error in a bus transaction. For more details regarding machine check architecture, Refer to the IA-32 Software Developer’s Manual, Volume 3: System Programming Guide.

Table 36. Signal Description (Sheet 5 of 8)

active until the system deasserts PROCHOT#. See Section 7.3 for more details. beyond; otherwise, it is an output signal. Table 19, and be followed by a 1 to 10 ms RESET# pulse. throughout boundary scan operation. parity checking of these signals. RESET#, all system bus agents will deassert their outputs within two clocks. appropriate pins of all processor system bus agents. appropriate pins of all processor system bus agents. board designers may use this pin to determine if the processor is present. Table 36. Signal Description (Sheet 6 of 8)

signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. clock signals to the bus and processor core units. serial input needed for JTAG specification support. the serial output needed for JTAG specification support. THERMDA Other Thermal Diode Anode. See Section 7.3.1. THERMDC Other Thermal Diode Cathode. See Section 7.3.1. temperature has reached a level where permanent silicon damage may occur. sequence and timing requirements.

• Driving of the THERMTRIP# signal is enabled within 10 µs of the assertion of PWRGOOD, and is disabled on de-assertion of PWRGOOD. Once activated, THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-assertion of the PWRGOOD signal will de-assert THERMTRIP#, if the processor’s junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 µs of the assertion of PWRGOOD. TMS Input TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRDY# Input TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all system bus agents.

Table 36. Signal Description (Sheet 7 of 8)

Table 1 for the appropriate Platform Design Guide for details on implementation. VCCIOPLL provides isolated power for internal processor system bus PLLs. Guide for details on implementation. processor on 0.13 micron process Voltage Identification circuit. VSSA Input VSSA is the isolated ground for internal PLLs. can be used to sense or measure ground near the silicon with little noise. Table 36. Signal Description (Sheet 8 of 8)

80 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet Pin Listing and Signal Definitions This page is intentionally left blank.

the 478-pin Package Thermal Design Guidelines. details on boxed processors. Figure 35. Example Thermal Solution (Not to Scale)

82 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet Thermal Specifications and Design Considerations

6.1 Processor Thermal Specifications

The Celeron processor 0.13 micron process requires a thermal solution to maintain temperatures within the operating limits as set forth in Section 6.1.1. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components in the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete thermal solution includes both component and system level thermal management features. Component-level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of system fans combined with ducting and venting. For more information on designing a component level thermal solution, refer to Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Thermal Design Guide.

6.1.1 Thermal Specifications

To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (TC) specifications when operating at or below the Thermal Design Power (TDP) value listed per frequency in Table 37. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, refer to the appropriate processor thermal design guidelines. The case temperature is defined at the geometric top center of the processor IHS. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained periods of time. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 37 instead of the maximum processor power consumption. The Thermal Monitor feature is intended to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more details on the usage of this feature, refer to Section 7.3. To ensure maximum flexibility for future requirements, systems should be designed to the Flexible Motherboard (FMB) guidelines, even if a processor with a lower thermal dissipation is currently planned. In all cases, the Thermal Monitor feature must be enabled for the processor to remain within specification. Multiple VID processors will be shipped either at VID=1.475 V , VID=1.500 V , or VID=1.525 V . Processors with multiple VIDs have TDP _max of the highest VID for the specified frequency. For example, for the processors through 2.40 GHz, the TDP would be 59.8 W.

1. These values are specified at VCC_ MAX for the processor. Systems must be designed to ensure that the

specified ICC. Refer to loadline specifications in Chapter 2.

1. The numbers in this column reflect Intel’s recommended design point and are not indicative of the maximum

® Pentium/Ga3 4 Processor in the 478-pin Package Thermal Design Guidelines .

1. Also applies to processors with fixed VID=1.525 V.

6.1.2 Thermal Metrology

6.1.2.1 Processor Case Temperature Measurement

Table 37. Processor Thermal Design Power

2 GHz 3

Figure 36. Guideline Locations for Case Temperature (TC) Thermocouple Placement

84 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet Thermal Specifications and Design Considerations This page is intentionally left blank.

Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet 85

Features

7.1 Power-On Configuration Options

Several configuration options can be configured by hardware. Celeron processor on 0.13 micron process sample their hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these options, refer to Table 38. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor. For reset purposes, the processor does not distinguish between a “warm” reset and a “power-on” reset.

7.2 Clock Control and Low Power States

The use of AutoHALT, Stop-Grant, and Sleep states is allowed in Celeron processor on 0.13 micron process based systems to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 37 for a visual representation of the processor low power states.

7.2.1 Normal State—State 1

This is the normal operating state for the processor. Table 38. Power-On Configuration Option Pins

1. Asserting this signal during RESET# will select the corresponding option.

86 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet

7.2.2 AutoHALT Powerdown State—State 2

AutoHALT is a low power state entered when the processor executes the HALT instruction. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or the AutoHALT Power Down state. See the Intel ® Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in AutoHALT Power Down state, the processor will process bus snoops and interrupts. Figure 37. Stop Clock State Machine

1. Auto HALT Power Down State

Snoops and interrupts allowed. Snoops and interrupts allowed.

Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet 87

7.2.3 Stop-Grant State—State 3

When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle. Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to VCC) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the system bus should be driven to the inactive state. BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched and can be serviced by software upon exit from the Stop-Grant state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the de-assertion of the STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should only be de-asserted one or more bus clocks after the de-assertion of SLP#. A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the assertion of the SLP# signal. While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process snoops on the system bus and it will latch interrupts delivered on the system bus. The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be asserted if there is any pending interrupt latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that it should return the processor to the Normal state.

7.2.4 HALT/Grant Snoop State—State 4

The processor will respond to snoop or interrupt transactions on the system bus while in Stop-Grant state or in AutoHALT Power Down state. During a snoop or interrupt transaction, the processor enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the system bus has been serviced (whether by the processor or another agent on the system bus) or the interrupt has been latched. After the snoop is serviced or the interrupt is latched, the processor will return to the Stop-Grant state or AutoHALT Power Down state, as appropriate.

88 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet

7.2.5 Sleep State—State 5

The Sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the SLP# signal. The SLP# pin should be asserted only when the processor is in the Stop Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation. Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will cause unpredictable behavior. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#) are allowed on the system bus while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state and held active as specified in the RESET# pin specification, the processor will reset itself, ignoring the transition through Stop- Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence. Once in the Sleep state, the SLP# pin must be de-asserted if another asynchronous system bus event must occur. The SLP# pin has a minimum assertion of one BCLK period. When the processor is in Sleep state, it will not respond to interrupts or snoop transactions.

7.3 Thermal Monitor

The Thermal Monitor feature helps control the processor temperature by activating the Thermal Control Circuit (TCC) when the processor silicon reaches its maximum operating temperature. The TCC reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications. The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. When the Thermal Monitor feature is enabled, and a high temperature situation exists (i.e., TCC is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30%–50%). Clocks often will not be off for more than 3.0 µs when the TCC is active. Cycle times are processor speed dependent and will decrease as processor core frequencies increase. A small amount of hysteresis has been included to prevent rapid active/ inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases. With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a T C that exceeds the

Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet 89 specified maximum temperature and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Thermal Design Guide for information on designing a thermal solution. The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and cannot be modified. The Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines. The TCC may also be activated via On-Demand mode. If bit 4 of the ACPI Thermal Monitor Control Register is written to a 1 the TCC will be activated immediately, independent of the processor temperature. When using On-Demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Thermal Monitor Control Register. In automatic mode, the duty cycle is fixed, however in On-Demand mode, the duty cycle Demand mode may be used while Automatic mode is enabled. However, if the system tries to enable the TCC via On-Demand mode while automatic mode is enabled and a high temperature condition exists, the duty cycle of the automatic mode will override the duty cycle selected by the On-Demand mode. An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is at the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active. The temperature at which the thermal control circuit activates is not user configurable and is not software visible. Besides the thermal sensor and TCC, the Thermal Monitor feature also includes one ACPI register, performance monitoring logic, bits in three model specific registers (MSR), and one I/O pin (PROCHOT#). All are available to monitor and control the state of the Thermal Monitor feature. Thermal Monitor can be configured to generate an interrupt upon the assertion or de-assertion of PROCHOT#. If automatic mode is disabled, the processor will be operating out of specification. Regardless of enabling of the automatic or On-Demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 135 °C. At this point the system bus signal THERMTRIP# will go active and stay active until RESET# has been initiated. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. If THERMTRIP# is asserted, processor core voltage (VCC) must be removed within the time frame defined in Table 19.

90 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet

7.3.1 Thermal Diode

The Celeron processor on 0.13 micron process incorporates an on-die thermal diode. A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management/long term die temperature change purposes. Table 39 and Table 40 provide the diode parameter and interface specifications. This thermal diode is separate from the Thermal Monitor’s thermal sensor and cannot be used to predict the behavior of the Thermal Monitor. Table 39. Thermal Diode Parameters

1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. Not 100% tested. Specified by design characterization.
3. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equa-

and T = absolute temperature (Kelvin).

1. The series resistance, RT, is provided to allow for a more accurate measurement of the diode junction tem-

by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Table 40. Thermal Diode Interface

8.1 Introduction

The Celeron processor on 0.13 micron process will also be offered as an Intel boxed processor. cooling solution that will be supplied with the boxed Celeron processor on 0.13 micron process. Processor in the 478-pin Package Thermal Design Guidelines for further guidance. NOTE: The airflow is into the center and out of the sides of the fan heatsink. Figure 38. Mechanical Representation of the Boxed Processor

8.2 Mechanical Specifications

8.2.1 Boxed Processor Cooling Solution Dimensions

0.13 micron process. The boxed processor will be shipped with an unattached fan heatsink. boxed processor fan heatsink must also be incorporated into new motherboard and system designs. lines shown (marked with alphabetic designations) to clarify relative dimensioning. Figure 39. Side View Space Requirements for the Boxed Processor

8.2.2 Boxed Processor Fan Heatsink Weight

8.2.3 Boxed Processor Retention Mechanism and Heatsink

documentation should include appropriate retention mechanism installation instructions. Figure 40. Top View Space Requirements for the Boxed Processor

94 Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet Boxed Processor Specifications heatsink attach clip assembly is latched to the retention tab features at each corner of the retention mechanism. The target load applied by the clips to the processor heat spreader for Intel’s reference design is 75 ±15 lbf (maximum load is constrained by the package load capability). It is normal to observe a bow or bend in the board due to this compressive load on the processor package and the socket. The level of bow or bend depends on the motherboard material properties and component layout. Any additional board stiffening devices (like plates) are not necessary and should not be used along with the reference mechanical components and boxed processor. Using such devices increases the compressive load on the processor package and socket, likely beyond the maximum load that is specified for those components. See the Pentium /Ga3 4 Processor in the 478-pin Package in the 478-pin Package Thermal Design Guidelines for details on the Intel reference design. Chassis that have adequate clearance between the motherboard and chassis wall (minimum 0.250 inch) should be selected to ensure that the board's underside bend does not contact the chassis.

8.3 Electrical Requirements

8.3.1 Fan Heatsink Power Supply

The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable will be shipped with the boxed processor to draw power from a power header on the motherboard. The power cable connector and pinout are shown in Figure 41. Motherboards must provide a matched power header to support the boxed processor. Table 41 contains specifications for the input and output signals at the fan heatsink connector. The fan heatsink outputs a SENSE signal, which is an open-collector output that pulses at a rate of two pulses per fan revolution. A motherboard pull-up resistor provides V OH to match the system board-mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND. Note: The motherboard must supply a constant +12 V to the processor’s power header to ensure proper operation of the variable speed fan for the boxed processor. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation or on the system board itself. Figure 42 shows the location of the fan power connector relative to the processor socket. The motherboard power header should be positioned within 4.33 inches from the center of the processor socket.

Figure 41. Boxed Processor Fan Heatsink Power Cable Connector Description Table 41. Fan Heatsink Power and Signal Specifications

1. Motherboard should pull this pin up to VCC with a resistor.

polarizing ribs and friction locking ramp. 0.100" pin pitch, 0.025" square pin width. Waldom/Molex P/N 22-01-3037 or equivalent.

Figure 42. MotherBoard Power Header Placement Relative to Processor Socket

8.4 Thermal Specifications

8.4.1 Boxed Processor Cooling Requirements

specification is the responsibility of the system integrator. Figure 43. Boxed Processor Fan Heatsink Airspace Keep-Out Requirements

8.4.2 Variable Speed Fan

(see Chapter 6) is the responsibility of the system integrator. operation of the variable speed fan for the boxed processor. Figure 44. Boxed Processor Fan Heatsink Airspace Keep-Out Requirements

Figure 45. Boxed Processor Fan Heatsink Set Points Table 42. Boxed Processor Fan Heatsink Set Points chassis temperature for nominal operating environment.

1. Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink.

internal chassis temperature for worst-case operating environment.

43 When the internal chassis temperature is above or equal to this set point,

the fan operates at its highest speed.

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Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Datasheet 101 Debug Tools Specifications Debug Tools Specifications 9 Refer to the ITP700 Debug Port Design Guide and the appropriate Platform Design Guide for more detailed information regarding debug tools specifications.

9.1 Logic Analyzer Interface (LAI)

Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Celeron processor on 0.13 micron process systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Because of the complexity of Celeron processor on 0.13 micron process systems, the LAI is critical in providing the ability to probe and capture system bus signals. There are two sets of considerations to keep in mind when designing a Celeron processor on 0.13 micron process system that can make use of an LAI: mechanical and electrical.

9.1.1 Mechanical Considerations

The LAI is installed between the processor socket and the processor. The LAI pins plug into the socket, while the processor pins plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keep-out volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keep-out volume remains unobstructed inside the system. Note that it is possible that the keep-out volume reserved for the LAI may differ from the space normally occupied by the Celeron processor on 0.13 micron process heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as part of the LAI.

9.1.2 Electrical Considerations

The LAI will also affect the electrical performance of the system bus; therefore, it is critical to obtain electrical load models from each of the logic analyzer vendors to allow running system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide.

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