250686-007

250686-007 INTEL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 97

Technical content

Datasheet sections

• 1.1 Terminology
• 1.2 References
• 2.1 System Bus and GTLREF
• 2.2 Power and Ground Pins
• 2.3 Decoupling Guidelines
• 2.3.1 VCC Decoupling
• 2.3.2 System Bus AGTL+ Decoupling
• 2.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking
• 2.4 Voltage Identification and Power Sequencing
• 2.4.1 Enhanced Intel® SpeedStep® Technology
• 2.4.2 Phase Lock Loop (PLL) Power and Filter
• 2.4.3 Catastrophic Thermal Protection
• 2.5 Signal Terminations, Unused Pins and TESTHI[10:0]
• 2.6 System Bus Signal Groups
• 2.7 Asynchronous GTL+ Signals
• 2.8 Test Access Port (TAP) Connection
• 2.9 System Bus Frequency Sele ct Signals (BSEL[1:0])
• 2.10 Maximum Ratings
• 2.11 Processor DC Specifications
• 2.12 AGTL+ System Bus Specifications
• 2.13 System Bus AC Specifications
• 2.14 Processor AC Timing Waveforms
• 3.1 System Bus Clock (BCLK) Signal Quality Specifications and Measurement
• 3.2 System Bus Signal Quality Specifications and Measurement Guidelines
• 3.3 System Bus Signal Quality Specifications and Measurement Guidelines
• 3.3.1 Overshoot/Undershoot Guidelines
• 3.3.2 Overshoot/Undershoot Magnitude
• 3.3.3 Overshoot/Undershoot Pulse Duration
• 3.3.4 Activity Factor
• 3.3.5 Reading Overshoot/Undershoot Specification Tables
• 4.1 Processor Pin-Out
• 5.1 Mobile Intel Pentium 4 Processor-M Pin Assignments
• 5.2 Alphabetical Signals Reference
• 6.1 Thermal Specifications

Mobile Intel Pentium 4 Processor-M Datasheet June 2003 Order Number: 250686-007

2 Mobile Intel Pentium 4 Processor-M Datasheet

Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information contained herein supersedes previously published specifications on these devices from Intel. Actual system-level properties, such as skin temperature, are a function of various factors, including component placement, component power characteristics, system power and thermal management techniques, software application usage and general system design. Intel is not responsible for its customers' system designs, nor is Intel responsible for ensuring that its customers' products comply with all applicable laws and regulations. Intel provides this and other thermal design information for informational purposes only. System design is the sole responsibility of Intel's customers, and Intel's customers should not rely on any Intel- provided information as either an endorsement or recommendation of any particular system design characteristics. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Mobile Intel Pentium 4 Processor-M may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725 or by visiting Intel’s Website at http://www.intel.com Copyright © Intel Corporation 2000-2003. Intel, Pentium, Intel NetBurst, and SpeedStep are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States and other countries. * Other brands and names are the property of their respective owners.

4 Mobile Intel Pentium 4 Processor-M Datasheet

Mobile Intel Pentium 4 Processor-M

Mobile Intel Pentium 4 Processor-M Datasheet 5 Figures

6 Illustration of Deep Sleep VCC Stat ic and Transient Tolerances (VID

28 Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP

29 High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP

34 The Coordinates of the Processor Pins as Viewed From the Top of the

6 Mobile Intel Pentium 4 Processor-M Datasheet

Mobile Intel Pentium 4 Processor-M Tables 8 IMVP-III Voltage Regulator Tolerances for VID = 1.30 V Operating Mode 9 IMVP-III Voltage Regulator Tolerances for VID = 1.20 V Operating Mode

10 IMVP-III Deep Sleep State Voltage Regulator Tolerances for Maximum

11 IMVP-III Deep Sleep State Voltage Regulator Tolerances for Battery Optimized

26 Stop Grant/Sleep/Deep Sleep/Enhanc ed Intel SpeedStep Technology AC

28 Ringback Specifications for AGTL+ and Asynchronous GTL+ Signal Groups.... 52

30 Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot

31 Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot

32 Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot

33 Asynchronous GTL+, PWRGOOD Input, and TAP Signal Groups

Mobile Intel Pentium 4 Processor-M Datasheet 7

8 Mobile Intel Pentium 4 Processor-M Datasheet

Mobile Intel Pentium 4 Processor-M

Revision History

March 2002 001 Initial release of the Datasheet April 2002 002 Updates include:

• Added new processor speeds: 1.4 GHz, 1.5 GHz, & 1.8 GHz
• Added PROCHOT# signal in Table 21
• Updated signal description for PROCHOT# in Table 37 and Section 6.1.2
• Updated the description of the E nhanced Intel Speedstep Technology in sections 2.4.1 and 7.3
• Updated PWRGOOD signal in Table 3, Section 2.7, Table 14, Table 21, Table 28, Table 35, Figure 28, and FIgure 29 June 2002 003 Updates include:
• Added specifications for new processor speeds: 1.90 GHz and 2 GHz
• Added die length and die width for processors based on B0-step shrink process in Table 33 September 2002 004 Updates include:
• Added 2.2 GHz Mobile Intel Pentium 4 Processor-M specifications.
• Current and power specifications updated in Table 7 & Table 38.
• Corrected STPCLK#/SLP# timing relationship in Section 7.2.3 to match parameter T75. January 2003 005 Updates include:
• Added 2.4 GHz Mobile Intel Pentium 4 Processor-M specifications.
• Current and power specifications updated in Table 7 & Table 38.
• Clarified DBI[3:0]# and THERMTRIP# descriptions in Table 37.
• Clarified thermal solution requirements in Section 6. April 2003 006 Updates include:
• Added 2.5 GHz Mobile Intel Pentium 4 Processor-M specifications.
• Current and power specifications updated in Table 7 & Table 38. June 2003 007 Updates include:
• Added 2.6 GHz Mobile Intel Pentium 4 Processor-M specifications.
• Updated note 5 in Table 22.
• Updated THERMTRIP# description in Table 37.

Mobile Intel Pentium 4 Processor-M Datasheet 9 1. Introduction The Mobile Intel Pentium 4 Processor-M is the first Intel mobile processor with the Intel NetBurstTM micro-architecture. The Mobile Intel Pentium 4 Processor-M utilizes a 478-pin, Micro Flip-Chip Pin Grid Array (Micro-FCPGA) package, and plugs into a surface-mount, Zero Insertion Force (ZIF) socket. The Mobile Intel Pentium 4 Processor-M maintains full compatibility with IA- 32 software. In this document the Mobile Intel Pentium 4 Processor-M will be referred to as the “Mobile Intel Pentium 4 Processor-M” or simply “the processor.” The Intel NetBurst micro-architecture features include hyper-pipelined technology, a rapid execution engine, a 400-MHz system bus, and an execution trace cache. The hyper pipelined technology doubles the pipeline depth in the Mobile Intel Pentium 4 Processor-M allowing the processor to reach much higher core frequencies. The rapid execution engine allows the two integer ALUs in the processor to run at twice the core frequency, which allows many integer instructions to execute in 1/2 clock tick. The 400-MHz system bus is a quad-pumped bus running off a 100-MHz system clock making 3.2 GB/sec data transfer rates possible. The execution trace cache is a first level cache that stores approximately 12-k decoded micro-operations, which removes the instruction decoding logic from the main execution path, thereby increasing performance. Additional features within the Intel NetBurst micro-architecture include advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and Streaming SIMD Extensions 2 (SSE2). The advanced dynamic execution improves speculative execution and branch prediction internal to the processor. The advanced transfer cache is a 512 kB, on-die level 2 (L2) cache. A new floating point and multi media unit has been implemented which provides superior performance for multi-media and mathematically intensive applications. Finally, SSE2 adds 144 new instructions for double-precision floating point, SIMD integer, and memory management. Power management capabilities such as AutoHALT, Stop-Grant, Sleep, Deep Sleep, and Deeper Sleep have been incorporated. The processor includes an address bus powerdown capability which removes power from the address and data pins when the system bus is not in use. This feature is always enabled on the processor. The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition. The new packed double-precision floating-point instructions enhance performance for applications that require greater range and precision, including scientific and engineering applications and advanced 3-D geometry techniques, such as ray tracing. The Mobile Intel Pentium 4 Processor-M’s 400-MHz Intel NetBurst micro-architecture system bus utilizes a split-transaction, deferred reply protocol like the Intel Pentium 4 Processor. This system bus is not compatible with the P6 processor family bus. The 400-MHz Intel NetBurst micro- architecture system bus uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3.2 Gbytes/second. The processor, when used in conjunction with the requisite Intel SpeedStep technology applet or its equivalent, supports Enhanced Intel SpeedStep technology, which enables real-time dynamic switching of the voltage and frequency between two performance modes. This occurs by switching the bus ratios, core operating voltage, and core processor speeds without resetting the system.

10 Mobile Intel Pentium 4 Processor-M Datasheet

The processor system bus uses a variant of GTL+ signalling technology called Assisted Gunning Transceiver Logic (AGTL+) signal technology. The Mobile Intel Pentium 4 Processor-M is available at the following core frequencies:

• 2.6 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V)
• 2.5 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V)
• 2.4 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V)
• 2.2 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V)
• 2.0 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V)
• 1.9 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V)
• 1.8 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V)
• 1.7 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V)
• 1.6 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V)
• 1.5 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V)
• 1.4 GHz (in Maximum Performance Mode at 1.30 V). This processor runs at 1.2 GHz (in Battery Optimized Mode at 1.20 V)

1.1 Terminology

state when driven to a low level. For example, when RESET# is low, a reset has been requested. hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level). components). The system bus is a multiprocessing interface to processors, memory, and I/O.

• Processor — For this document, the term processor shall mean the Mobile Intel Pentium 4 Processor-M in the 478-pin package.
• Keep out zone — The area on or near the processor th at system design can not utilize.
• Intel 845MP/845MZ chipsets — Mobile chipsets that will support the Mobile Intel Pentium 4 Processor-M.
• Processor core — Mobile Intel Pentium 4 Processor-M core die with integrated L2 cache.
• Micro-FCPGA package — Micro Flip-Chip Pin Grid Array package with 50-mil pin pitch.

1.2 References

Table 1. References

12 Mobile Intel Pentium 4 Processor-M Datasheet

This page intentionally left blank.

1. Electrical Specifications

2.1 System Bus and GTLREF

845MZ Chipset Platform Design Guide. determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board. Chipset Platform Design Guide. system bus, including trace lengths, is highly recommended when designing a system.

2.2 Power and Ground Pins

2.3 Decoupling Guidelines

voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Table 7. Failure to do so can result in timing violations and/or

14 Mobile Intel Pentium 4 Processor-M Datasheet

2.3.1 V CC Decoupling

2.3.2 System Bus AGTL+ Decoupling

2.3.3 System Bus Clock (BCLK[ 1:0]) and Processor Clocking

4 Processor-M supported ratios.

1. Ratio is used for debug purposes only.

Table 2. Core Frequency to System Bus Multipliers

800 MHz 1/8 1

1.2 GHz 1/12

1.4 GHz 1/14

1.5 GHz 1/15

1.6 GHz 1/16

1.7 GHz 1/17

1.8 GHz 1/18

1.9 GHz 1/19

2.0 GHz 1/20

2.2 GHz 1/22

2.4 GHz 1/24

2.5 GHz 1/25

2.6 GHz 1/26

1. Listed frequencies are not necessarily committed production frequencies.

information on Mobile Intel Pentium 4 Processor-M clocking.

2.4 Voltage Identification and Power Sequencing

have been set such that one voltage regulator can work with all supported frequencies. Processor-M are open drain outputs driven by the processor VID circuitry. level and a “0” refers to low-voltage level. Power source characteristics must be stable whenever the supply to the voltage regulator is stable. supply. This voltage must be routed to the processor VCCVID pin. current requirements of the VCCVID pin. Figure 1. VCCVID Pin Voltage and Current Requirements

16 Mobile Intel Pentium 4 Processor-M Datasheet

2.4.1 Enhanced Intel ® SpeedStep® Technology

SpeedStep technology applet or its equivalent, supports Enhanced Intel SpeedStep technology. Table 3. Voltage Identification Definition

performing an operating mode transition.

2.4.2 Phase Lock Loop (PLL) Power and Filter

must be low pass filtered from VCCVID. A typical filter topology is shown in Figure 2.

• < 0.2 dB gain in pass band
• < 0.5 dB attenuation in pass band < 1 Hz
• > 34 dB attenuation from 1 MHz to 66 MHz
• > 28 dB attenuation from 66 MHz to core frequency The filter requirements are illustrated in Figure 3. For recommendations on implementing the filter refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide.

Figure 2. Typical V CCIOPLL, VCCA and VSSA Power Distribution

18 Mobile Intel Pentium 4 Processor-M Datasheet

1. No specification for frequencies beyond fcore (core frequency).
2. fpeak, if existent, should be less than 0.05 MHz.

2.4.3 Catastrophic Thermal Protection

Section 5.2 for more details on THERMTRIP#.

2.5 Signal Terminations, Unus ed Pins and TESTHI[10:0]

Figure 3. Phase Lock Loop (PLL) Filter Requirements

1 MHz 66 MHz fcorefpeak1 HzDC

Mobile Intel Pentium 4 Processor-M Datasheet 19 For reliable operation, always connect unused inputs or bidirectional signals that are not terminated on the die to an appropriate signal level. Note that on-die termination has been included on the Mobile Intel Pentium 4 Processor-M to allow signals to be terminated within the processor silicon. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Table 4 lists details on AGTL+ signals that do not include on-die termination. Unused active high inputs should be connected through a resistor to ground (VSS). Refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for the appropriate resistor values. Unused outputs can be left unconnected, however, this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. For unused AGTL+ input or I/O signals that don’t have on-die termination, use pull-up resistors of the same value in place of the on-die termination resistors TT). See Table 18. The TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die termination. Inputs and used outputs must be terminated on the system board. Unused outputs may be terminated on the system board or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. Signal termination for these signal types is discussed in the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide. The TESTHI pins should be tied to the processor VCC using a matched resistor, where a matched resistor has a resistance value within + 20% of the impedance of the board transmission line traces. For example, if the trace impedance is 50 Ω , then a value between 40 Ω and 60 Ω is required. The TESTHI pins may use individual pull-up resistors or be grouped together as detailed below. A matched resistor should be used for each group: 1. TESTHI[1:0] 2. TESTHI[5:2] 3. TESTHI[10:8] Additionally, if the ITPCLKOUT[1:0] pins are not used then they may be connected individually to VCC using matched resistors or grouped with TESTHI[5:2] with a single matched resistor. If they are being used, individual termination with 1-kΩ resistors is required. Tying ITPCLKOUT[1:0] directly to VCC or sharing a pull-up resistor to VCC will prevent use of debug interposers. This implementation is strongly discouraged for system boards that do not implement an onboard debug port. As an alternative, group 2 (TESTHI[5:2]), and the ITPCLKOUT[1:0] pins may be tied directly to the processor VCC. This has no impact on system functionality. TESTHI[0] may also be tied directly to processor VCC if resistor termination is a problem, but matched resistor termination is recommended. In the case of the ITPCLKOUT[1:0] pins, direct tie to VCC is strongly discouraged for system boards that do not implement an onboard debug port. Tying any of the TESTHI pins together will prevent the ability to perform boundary scan testing. Pullup/down resistor requirements for the VID[4:0] and BSEL[1:0] signals are included in the signal descriptions in Section 5.

20 Mobile Intel Pentium 4 Processor-M Datasheet

2.6 System Bus Signal Groups

In order to simplify the following discussion, the system bus signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependant upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 4 identifies which signals are common clock, source synchronous, and asynchronous.

1. Refer to Section 5.2 for signal descriptions.
2. These AGTL+ signals do not have on-die termination. Refer to Section 2.5 for termination requirements.
3. In processor systems where there is no debug port implemented on the system board, these signals are used
4. These signal groups are not terminated by the processor. Signals not driven by the ICH3-M component must

Intel 845MP/845MZ Chipset Platform Design Guide for termination requirements and further details.

1. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration

options. See Section 7.1 for details. Table 4. System Bus Pin Groups

22 Mobile Intel Pentium 4 Processor-M Datasheet

2.7 Asynchronous GTL+ Signals

Section 2.13 for the DC and AC specifications for the Asynchronous GTL+ signal groups.

2.8 Test Access Port (TAP) Connection

copies of each signal may be required, with each driving a different voltage level.

2.9 System Bus Frequency Se lect Signals (BSEL[1:0])

and clock synthesizer. All agents must operate at the same frequency. specified system bus frequency. Table 5. BSEL[1:0] Frequency Table for BCLK[1:0]

2.10 Maximum Ratings

the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability.

1. This rating applies to any processor pin.
2. Contact Intel for storage requirements in excess of one year.

2.11 Processor DC Specifications

these signals are listed in Table 13. DC specifications for these signal groups are listed in Table 14 and Table 15. are at TJ = 100°C. Care should be taken to read all notes associated with each parameter. Table 6. Processor DC Absolute Maximum Ratings

24 Mobile Intel Pentium 4 Processor-M Datasheet

1. Unless otherwise noted, all specifications in this table are based on latest post-silicon measurements

available at the time of publication.

1. These voltages are targets only. A variable voltage source should exist on systems in the event that a

VCC with the minimum being defined according to current consumption at that voltage.

1. The voltage specification requirements are measured at the system board socket ball with a 100 MHz
2. Refer to Table 8 to Table 11 and Figure 4 to Figure 6 for the minimum, typical, and maximum VCC (measured

specification can affect the long term reliability of the processor.

1. VCC_MIN is defined at ICC_MAX.
2. The current specified is also for AutoHALT State.
3. Typical VCC indicates the VID encoded voltage. Voltage supplied must conform to the load line specification

shown in Table 8 to Table 11.

1. The maximum instantaneous current the processor will draw while the thermal control circuit is active as

indicated by the assertion of PROCHOT# is the same as the maximum ICC for the processor.

1. Maximum specifications for ICC Core, ICC Stop-Grant, ICC Sleep, and ICC Deep Sleep are specified at VCC

Table 7. Voltage and Current Specifications

10.The specification is defined per PLL pin. several microseconds after the transient event. nanoseconds to several microseconds after the transient event. superimposed on the rising edge. Table 8. IMVP-III Voltage Regulator Tolerances for VID = 1.30 V Operating Mode (Maximum

26 Mobile Intel Pentium 4 Processor-M Datasheet

Figure 4. Illustration of V CC Static and Transient Tolerances (VID = 1.30 V)

Table 9. IMVP-III Voltage Regulator Tolerances for VID = 1.20 V Operating Mode (Battery

28 Mobile Intel Pentium 4 Processor-M Datasheet

Figure 5. Illustration of V CC Static and Transient Tolerances (VID = 1.20 V) Table 10. IMVP-III Deep Sleep State Voltage Regulator Tolerances for Maximum Performance

Table 11. IMVP-III Deep Sleep State Voltage Regulator Tolerances for Battery Optimized Mode Figure 6. Illustration of Deep Sleep V CC Static and Transient Tolerances (VID Setting = 1.30 V)

30 Mobile Intel Pentium 4 Processor-M Datasheet

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the
3. VHavg is the statistical average of the VH measured by the oscilloscope.
4. Overshoot is defined as the absolute value of the maximum voltage.
5. Undershoot is defined as the absolute value of the minimum voltage.
6. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback

and the maximum Falling Edge Ringback.

1. Threshold Region is defined as a region entered around the crossing point voltage in which the differential

receiver switches. It includes input threshold hysteresis.

1. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
2. VHavg can be measured directly using "Vtop" on Agilent* scopes and "High" on Tektronix* scopes.

10.∆VCROSS is defined as the total variation of all crossing voltages as defined in note 2. Table 12. System Bus Differential BCLK Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
4. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the

signal quality specifications in Section 3.

1. Refer to processor I/O Buffer Models for I/V characteristics.
2. The VCC referred to in these specifications is the instantaneous VCC.
3. Vol max of 0.450 Volts is guaranteed when driving into a test load of 50 Ω as indicated in Figure 8.
4. Leakage to VSS with pin held at VCC.
5. Leakage to VCC with pin held at 300 mV.

Table 13. AGTL+ Signal Group DC Specifications

32 Mobile Intel Pentium 4 Processor-M Datasheet

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All outputs are open-drain.
3. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the

signal quality specifications in Section 3.

1. The VCC referred to in these specifications refers to instantaneous VCC.
2. This specification applies to the asynchronous GTL+ signal group.
3. The maximum output current is based on maximum current handling capability of the buffer and is not

specified into the test load shown in Figure 8.

1. Refer to the processor I/O Buffer Models for I/V characteristics.
2. Vol max of 0.270 Volts is guaranteed when driving into a test load of 50 Ω as indicated in Figure 8 for the
3. Leakage to VSS with pin held at VCC.

10.Leakage to VCC with pin held at 300 mV. Table 14. Asynchronous GTL+ Signal Group DC Specifications

Table 15. PWRGOOD and TAP Signal Group DC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All outputs are open-drain.
3. TAP signal group must comply with the signal quality specifications in Section 3.
4. Refer to I/O Buffer Models for I/V characteristics.
5. The VCC referred to in these specifications refers to instantaneous VCC.
6. The maximum output current is based on maximum current handling capability of the buffer and is not

specified into the test load shown if Figure 8.

1. Vol max of 0.320 Volts is guaranteed when driving into a test load of 50 Ohms as indicated in Figure 8 for the
2. VHYS represents the amount of hysteresis, nominally centered about 1/2 Vcc for all TAP inputs.
3. Leakage to VSS with pin held at VCC.

10.Leakage to VCC with pin held at 300 mV. Table 16. ITPCLKOUT[1:0] DC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. See Figure 7 for ITPCLKOUT[1:0] output buffer diagram.

34 Mobile Intel Pentium 4 Processor-M Datasheet

Figure 7. ITPCLKOUT[1:0] Output Buffer Diagram

1. See Table 16 for range of Ron.
2. The Vcc referred to in this figure is the instantaneous Vcc.
3. Refer to the appropriate platform design guidelines for the value of Rext.

Table 17. BSEL [1:0] and VID[4:0] DC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. Leakage to Vss with pin held at 2.50 V.

2.12 AGTL+ System Bus Specifications

for most AGTL+ signals, as these are integrated into the processor silicon. with a reference voltage called GTLREF (known as VREF in previous documentation).

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The tolerances for this specification have been stated generically to enable the system designer to calculate

the minimum and maximum values across the range of VCC.

1. GTLREF should be generated from VCC by a voltage divider of 1% tolerance resistors or 1% tolerance

Platform Design Guide for implementation details.

1. RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Refer to processor I/O

buffer models for I/V characteristics.

1. COMP resistance must be provided on the system board with 1% tolerance resistors. See the Mobile Intel
2. The VCC referred to in these specifications is the instantaneous VCC.

2.13 System Bus AC Specifications

(pads). See Section 5.2 for the Mobile Intel Pentium 4 Processor-M pin signal definitions. Table 19 through Table 26 list the AC specifications associated with the processor system bus. 100°C. Care should be taken to read all notes associated with a particular timing parameter. Table 18. AGTL+ Bus Voltage Definitions

36 Mobile Intel Pentium 4 Processor-M Datasheet

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The period specified here is the average period. A given period may vary from this specification as governed

by the period stability specification (T2).

1. In this context, period stability is defined as the worst case timing difference between successive crossover
2. Slew rate is measured between the 35% and 65% points of the clock swing (VL to VH).
3. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
4. Not 100% tested. Specified by design characterization.
5. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the
6. Valid delay timings for these signals are specified into the test circuit described in Figure 8 and with GTLREF
7. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate
8. RESET# can be asserted asynchronously, but must be deasserted synchronously.
9. This should be measured after VCC and BCLK[1:0] become stable.
10. Maximum specification applies only while PWRGOOD is asserted.

Table 19. System Bus Differential Clock Specifications Table 20. System Bus Common Clock AC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All source synchronous AC timings are referenced to their associated strobe at GTLREF. Source

synchronous address signals are referenced to the rising and falling edge of their associated address strobe. All source synchronous AGTL+ signal timings are referenced to GTLREF at the processor core.

1. Unless otherwise noted these specifications apply to both data and address timings.
2. Valid delay timings for these signals are specified into the test circuit described in Figure 8 and with GTLREF
3. Specification is for a minimum swing defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate
4. All source synchronous signals must meet the specified setup time to BCLK as well as the setup time to each
5. This specification represents the minimum time the data or address will be valid before its strobe. Refer to the

information on the definitions and use of these specifications.

1. This specification represents the minimum time the data or address will be valid after its strobe. Refer to the

information on the definitions and use of these specifications. 11.For this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively. come approximately 3/4 BCLK period (7.5 ns) after the first falling edge of DSTBp#. 13.This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe. Table 21. System Bus Source Synch AC Specifications AGTL+ Signal Group

38 Mobile Intel Pentium 4 Processor-M Datasheet

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. All AC timings for the Asynch GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage. All
3. These signals may be driven asynchronously.
4. Refer to the PWRGOOD definition for more details regarding the behavior of this signal.
5. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the

requirements for when PROCHOT# is asserted by the system.

1. See Section 7.2 for additional timing requirements for entering and leaving the low power states.
2. Before the deassertion of RESET#.
3. After clock that deasserts RESET#.

Table 22. Miscellaneous Si gnals AC Specifications Table 23. System Bus AC Specifications (Reset Conditions)

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*VCC at the processor pins. All TAP

signal timings (TMS, TDI, etc) are referenced at 0.5*VCC at the processor pins.

1. Rise and fall times are measured from the 20% to 80% points of the signal swing.
2. Referenced to the rising edge of TCK.
3. Referenced to the falling edge of TCK.
4. Specifications for a minimum swing defined between TAP VT- to VT+. This assumes a minimum edge rate of

0.5 V/ns

1. TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.
2. It is recommended that TMS be asserted while TRST# is being deasserted.

Table 25. ITPCLKOUT[1:0] AC Specifications

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are not tested and are based on design simulations.
3. This delay is from rising edge of BCLK0 to the falling edge of ITPCLK0.

Table 24. TAP Signals AC Specifications

40 Mobile Intel Pentium 4 Processor-M Datasheet

1. Input signals other than RESET# must be held constant in the Sleep state.
2. The BCLK can be stopped after DPSLP# is asserted. The BCLK must be turned on and within specification

before DPSLP# is deasserted.

2.14 Processor AC Timing Waveforms

1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the
2. All source synchronous AC timings for AGTL+ signals are referenced to their associated strobe (address or
3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at VCROSS. All AGTL+ strobe signal

timings are referenced at GTLREF at the processor core silicon.

1. All AC timings for the TAP signals are referenced to the TCK signal at 0.5*VCC at the processor pins. All TAP

signal timings (TMS, TDI, etc.) are referenced at 0.5*VCC at the processor pins. The circuit used to test the AC specifications is shown in Figure 8. Table 26. Stop Grant/Sleep/Deep Sleep/Enhanced Intel SpeedStep Technology AC

10 BCLKs 23, 24

42 Mobile Intel Pentium 4 Processor-M Datasheet

Figure 10. Differential Clock Waveform

44 Mobile Intel Pentium 4 Processor-M Datasheet

Figure 13. System Bus Reset and Configuration Timings Figure 14. Source Synchronous 2X (Address) Timings

Figure 15. Source Synchronous 4X Timings

46 Mobile Intel Pentium 4 Processor-M Datasheet

Figure 16. Power Up Sequence Figure 17. Power Down Sequence Processor and Intel 845MP Platform RDDP. Processor and Intel 845MP Platform RDDP.

1. This timing diagram is not intended to show specific times. Instead a

general ordering of events with respect to time should be observed.

1. When VCCVID is less than 1V, VID_GOOD must be low.
2. Vcc must be disabled before VID[4:0] becomes invalid.
3. VCCVID and Vcc regulator can be disabled simultaneously

48 Mobile Intel Pentium 4 Processor-M Datasheet

Figure 21. TAP Valid Delay Timing Figure 22. ITPCLKOUT Valid Delay Timing

Figure 23. Stop Grant/Sleep/Deep Sleep Timing

50 Mobile Intel Pentium 4 Processor-M Datasheet

Figure 24. Enhanced Intel SpeedStep Technology/Deep Sleep Timing

1. System Bus Signal Quality Specifications

acceptable signal quality across all systematic variations encountered in volume manufacturing. through simulation and for interpreting results for signal quality measurements of actual designs.

3.1 System Bus Clock (BCLK) Signal Quality Specifications

clock at the processor pads.

1. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute

specification is an absolute value. Table 27. BCLK Signal Quality Specifications

52 Mobile Intel Pentium 4 Processor-M Datasheet

3.2 System Bus Signal Quality Specifications and

simulating signal quality at the processor core silicon (pads).

1. All signal integrity specifications are measured at the processor silicon (pads).
2. Unless otherwise noted, all specifications in this table apply to all Mobile Intel Pentium 4 Processor-M
3. Specifications are for the edge rate of 0.3 - 4.0 V/ns.
4. All values specified by design characterization.
5. Please see Section 3.3 for maximum allowable overshoot.
6. Ringback between GTLREF + 10% and GTLREF - 10% is not supported.
7. Intel recommends simulations not exceed a ringback value of GTLREF +/- 200 mV to allow margin for other

Figure 25. BCLK Signal Integrity Waveform Table 28. Ringback Specifications for AGTL+ and Asynchronous GTL+ Signal Groups

54 Mobile Intel Pentium 4 Processor-M Datasheet

Figure 28. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Figure 29. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP

System Bus Signal Quality Specifications Mobile Intel Pentium 4 Processor-M Datasheet 55

3.3 System Bus Signal Qu ality Specifications and

3.3.1 Overshoot/Undershoot Guidelines

Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage (or below VSS) as shown in Figure 30. The overshoot guideline limits transitions beyond VCC or VSS due to the fast signal edge rates. The processor can be damaged by repeated overshoot or undershoot events on any input, output, or I/O buffer if the charge is large enough (i.e., if the over/undershoot is great enough). Determining the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse direction, and the activity factor (AF). Permanent damage to the processor is the likely result of excessive overshoot/undershoot. When performing simulations to determine impact of overshoot and undershoot, ESD diodes must be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide overshoot or undershoot protection. ESD diodes modelled within Intel I/O buffer models do not clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models are being used to characterize the Mobile Intel Pentium 4 Processor-M system bus, care must be taken to ensure that ESD models do not clamp extreme voltage levels. Intel I/O buffer models also contain I/O capacitance characterization. Therefore, removing the ESD diodes from an I/O buffer model will impact results and may yield excessive overshoot/undershoot.

3.3.2 Overshoot/Unde rshoot Magnitude

Magnitude describes the maximum potential difference between a signal and its voltage reference level. For the Mobile Intel Pentium 4 Processor-M both are referenced to VSS. It is important to note that overshoot and undershoot conditions are separate and their impact must be determined independently. Overshoot/undershoot magnitude levels must observe the absolute maximum specifications listed in Table 30 through Table 33. These specifications must not be violated at any time regardless of bus activity or system state. Within these specifications are threshold levels that define different allowed pulse durations. Provided that the magnitude of the overshoot/undershoot is within the absolute maximum specifications, the pulse magnitude, duration and activity factor must all be used to determine if the overshoot/undershoot pulse is within specifications.

3.3.3 Overshoot/Undershoot Pulse Duration

Pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/ undershoot reference voltage (maximum overshoot = 1.700 V , maximum undershoot = -0.400 V). The total time could encompass several oscillations above the reference voltage. Multiple overshoot/undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total pulse duration.

System Bus Signal Quality Specifications

56 Mobile Intel Pentium 4 Processor-M Datasheet

Note: Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot pulse duration.

3.3.4 Activity Factor

Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a clock. Since the highest frequency of assertion of any signal is every other clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs EVERY OTHER clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs one time in every 200 clock cycles. For source synchronous signals (address, data, and associated strobes), the activity factor is in reference to the strobe edge, since the highest frequency of assertion of any source synchronous signal is every active edge of its associated strobe. An AF = 1 indicates that the specific overshoot (undershoot) waveform occurs every strobe cycle. The specifications provided in Table 30 through Table 33 show the maximum pulse duration allowed for a given overshoot/undershoot magnitude at a specific activity factor. Each table entry is independent of all others, meaning that the pulse duration reflects the existence of overshoot/ undershoot events of that magnitude ONLY . A platform with an overshoot/undershoot that just meets the pulse duration for a specific magnitude where the AF < 1, means that there can be no other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the event occurs at all times and no other events can occur). Note: 1: Activity factor for AGTL+ signals is referenced to BCLK[1:0] frequency. Note: 2: Activity factor for source synchronous (2x) signals is referenced to ADSTB[1:0]#. Note: 3: Activity factor for source synchronous (4x) signals is referenced to DSTBP[3:0]# and DSTBN[3:0]#.

3.3.5 Reading Overshoot/Unders hoot Specification Tables

The overshoot/undershoot specification for the Mobile Intel Pentium 4 Processor-M is not a simple single value. Instead, many factors are needed to determine what the over/undershoot specification is. In addition to the magnitude of the overshoot, the following parameters must also be known: the width of the overshoot (as measured above V CC) and the activity factor (AF). To determine the allowed overshoot for a particular overshoot event, the following must be done: 1. Determine the signal group a particular signal falls into. If the signal is an AGTL+ signal operating in the common clock domain, use Table 32. For AGTL+ signals operating in the 2x source synchronous domain, use Table 31. For AGTL+ signals operating in the 4x source synchronous domain, use Table 30. Finally, all other signals reside in the 100MHz domain (asynchronous GTL+, TAP, etc.) and are referenced in Table 33. 2. Determine the magnitude of the overshoot (relative to VSS). 3. Determine the activity factor (how often does this overshoot occur?) 4. Next, from the appropriate sp ecification table, determine the maximum pulse duration (in nanoseconds) allowed. 5. Compare the specified maximum pulse duration to the signal being measured. If the pulse duration measured is less than the pulse duration shown in the table, then the signal meets the specifications.

they are mutually exclusive.

3.3.6 Conformance Determination to Ov ershoot/Undershoot Specifications

system passes the overshoot and undershoot specifications is shown below.

1. Ensure no signal ever exceeds V CC or -0.25 V OR
2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot
3. If multiple overshoots and/or multiple under shoots occur, measure the worst case pulse

specifications) in the table (where AF=1), then the system passes. The following notes apply to Table 30 through Table 33.

1. Absolute Maximum Overshoot magnitude of 1.70 V must never be exceeded.
2. Absolute Maximum Overshoot is measured relative to VSS, Pulse Duration of overshoot is measured relative
3. Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to VSS.
4. Ringback below VCC can not be subtracted from overshoots/undershoots.
5. Lesser undershoot does not allocate longer or larger overshoot.
6. OEM's are strongly encouraged to follow Intel provided layout guidelines.
7. All values specified by design characterization.
8. These specifications are measured at the processor core silicon.

Table 30. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot

58 Mobile Intel Pentium 4 Processor-M Datasheet

1. These specifications are measured at the processor core silicon.
2. These specifications are measured at the processor core silicon.

Table 31. Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Table 32. Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance

1. These specifications are measured at the processor core silicon.

Table 33. Asynchronous GTL+, PWRGOOD I nput, and TAP Signal Groups Overshoot/ Figure 30. Maximum Acceptable Overshoot/Undershoot Waveform

System Bus Signal Quality Specifications

60 Mobile Intel Pentium 4 Processor-M Datasheet

This page intentionally left blank.

1. Package Mechanical Specifications

The Mobile Intel Pentium 4 Processor-M is packaged in a 478 pin Micro-FCPGA package. Figure 31. Micro-FCPGA Package Top and Bottom Isometric Views

62 Mobile Intel Pentium 4 Processor-M Datasheet

Figure 32. Micro-FCPGA Package Top and Side View All dimensions in millimeters. Values shown are for reference only.

1.25 MAX

Table 34. Micro-FCPGA Package Dimensions

1. All Dimensions are subject to change. Values shown are for reference only.
2. Overall height with socket is based on design dimensions of the Micro-FCPGA package and socket with no

subject to change based on socket design, OEM motherboard design, or OEM SMT process.

64 Mobile Intel Pentium 4 Processor-M Datasheet

Figure 33. Micro-FCPGA Package - Bottom View NOTE: All dimensions in millimeters. Values shown are for reference only.

4.1 Processor Pin-Out

Figure 34 shows the top view pinout of the Mobile Intel Pentium 4 Processor-M.

Figure 34. The Coordinates of the Processor Pins as Viewed From the Top of the Package.

8 D#[52] VSS D#[50] D#[49] VSS D#[48]

9 INIT# VSS VSS DSTBN#[3] DSTBP#

10 VSS BPM#[3] D#[60] VSS D#[58] D#[59] VSS D#[56]

0 DPSLP# ITP_CL

Package Mechanical Specifications

66 Mobile Intel Pentium 4 Processor-M Datasheet

This page intentionally left blank.

Pin Listing and Signal Definitions Mobile Intel Pentium 4 Processor-M 67 5. Pin Listing and Signal Definitions

5.1 Mobile Intel Pentium 4 Pr ocessor-M Pin Assignments

Section 5.1 contains the pin list for the Mobile Intel Pentium 4 Processor-M in Table 35 and Table 36. Table 35 is a listing of all processor pins ordered alphabetically by pin name. Table 36 is also a listing of all processor pins but ordered by pin number.

68 Mobile Intel Pentium 4 Processor-M Datasheet

Table 35. Pin Listing by Pin Name

70 Mobile Intel Pentium 4 Processor-M Datasheet

72 Mobile Intel Pentium 4 Processor-M Datasheet

74 Mobile Intel Pentium 4 Processor-M Datasheet

Table 36. Pin Listing by Pin Number

76 Mobile Intel Pentium 4 Processor-M Datasheet

78 Mobile Intel Pentium 4 Processor-M Datasheet

80 Mobile Intel Pentium 4 Processor-M Datasheet

5.2 Alphabetical Signals Reference

Table 37. Signal Description (Page 1 of 8) Processor-M system bus. A[35:3]# are protected by parity signals AP[1:0]#. assertion of the corresponding Input/Output Write bus transaction. snoop, or deferred reply ID match operations associated with the new transaction. edges. Strobes are associated with signals as shown below. signals are low. This allows parity to be high when all the covered signals are high.

82 Mobile Intel Pentium 4 Processor-M Datasheet

signal any bus condition that prevents reliable future operation. system bus and attempt completion of their bus queue and IOQ entries. cannot issue any new transactions. BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. processor output used by debug tools to determine processor debug readiness. used by debug tools to request debug operation of the processor. 845MZ Chipset Platform Design Guide. are completed, then releases the bus by deasserting BPRI#. This signal does not have on-die termination and must be terminated. BSEL[1:0] (Bus Select) are used to select the processor input clock frequency. appropriate platform design guidelines. COMP[1:0] must be terminated on the system board using precision resistors. Chipset Platform Design Guide for details on implementation. Table 37. Signal Description (Page 2 of 8)

on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. the corresponding data group is inverted and therefore sampled active high. system, DBR# is a no connect in the system. DBR# is not a processor signal. on all processor system bus agents. appropriate pins of all processor system bus agents. appropriate pins of all Mobile Intel Pentium 4 Processor-M system bus agents. Table 37. Signal Description (Page 3 of 8)

84 Mobile Intel Pentium 4 Processor-M Datasheet

must be deasserted and BCLK[1:0] must be running. pins of all processor system bus agents. Data strobe used to latch in D[63:0]#. Data strobe used to latch in D[63:0]#. FERR#/PBE# indicates that the processor should be returned to the Normal state. termination and connection guidelines. and Intel 845MP/845MZ Chipset Platform Design Guide for more information. Table 37. Signal Description (Page 4 of 8)

IERR# (Internal Error) is asserted by a processor as the result of an internal error. asserted until the assertion of RESET#. floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. assertion of the corresponding Input/Output Write bus transaction. of all processor system bus agents. processor executes its Built-in Self-Test (BIST). Section 2.5 for additional details and termination requirements. port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals. processor. Both signals are asynchronous. transaction to the end of the last transaction. operation and ensure the atomicity of lock. Table 37. Signal Description (Page 5 of 8)

86 Mobile Intel Pentium 4 Processor-M Datasheet

Asserted, if configured, for internal errors along with IERR#. Asserted by any bus agent when it observes an error in a bus transaction. Software Developer’s Manual, Volume 3: System Programming Guide. temperature has reached its thermal limit. See Section 6 for more details. monotonically to a high state. by a 1 to 10 ms RESET# pulse. throughout boundary scan operation. asserted for more than 10 ms while PWRGOOD is asserted. appropriate pins of all processor system bus agents. processor system bus agents. Table 37. Signal Description (Page 6 of 8)

board designers may use this pin to determine if the processor is present. SMI# (System Management Interrupt) is asserted asynchronously by system logic. serial input needed for JTAG specification support. the serial output needed for JTAG specification support. a resistor for proper processor operation. See Section 2.5 for more details. THERMDA Other Thermal Diode Anode. See Section 6. THERMDC Other Thermal Diode Cathode. See Section 6. Table 37. Signal Description (Page 7 of 8)

88 Mobile Intel Pentium 4 Processor-M Datasheet

sequence and timing requirements. asserted within 10 us of the assertion of PWRGOOD. low during power on Reset. This can be done with a 680 ohm pull-down resistor. Design Guide for complete implementation details. can be used to sense or measure power near the silicon with little noise. Pentium 4 Processor-M’s Voltage Identification circuit. VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. requested by the pins, or disable itself. VSSA Input VSSA is the isolated ground for internal PLLs. used to sense or measure ground near the silicon with little noise. Table 37. Signal Description (Page 8 of 8)

1. Thermal Specifications and Design

Table 38. Power Specifications for th e Mobile Intel Pentium 4 Processor-M

1. TDP is defined as the worst case power dissipated by the processor while executing publicly available

90 Mobile Intel Pentium 4 Processor-M Datasheet

1. Not 100% tested. These power specifications are determined by characterization of the processor currents at

higher temperatures and extrapolating the values for the temperature indicated.

1. The maximum junction temperature (TJ) is specified as the hottest location on the die. The thermal monitor’s

measurement guidelines (Refer to Section 6.1.2 for thermal monitor details).

6.1 Thermal Specifications

6.1.1 Thermal Diode

sampling rate of the sensor is much slower than the die level temperature changes. processor thermal diode to implement power management events. Table 39. Thermal Diode Interface Table 40. Thermal Diode Specifications

1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. Not 100% tested. Specified by design characterization.
3. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode

Thermal Specifications and Design Considerations Mobile Intel Pentium 4 Processor-M Datasheet 91 Where IS = saturation current, q = electronic charge, VD = voltage across the diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin). 5. The series resistance, RT, is provided to allow for a more accurate measurement of the diode junction temperature. RT as defined includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. RT can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: Terror = [RT*(N-1)*IFWmin]/[(nk/q)*ln N] Where Terror = sensor temperature error, N = sensor current ration, k = Boltzmann Constant, q = electronic charge.

6.1.2 Thermal Monitor

The thermal monitor feature found in the Mobile Intel Pentium 4 Processor-M allows system designers to design lower cost thermal solutions without compromising system integrity or reliability. By using a factory-tuned, precision on-die thermal sensor, and a fast acting thermal control circuit (TCC), the processor, without the aid of any additional software or hardware, can keep the processor’s die temperature within factory specifications under nearly all conditions. The thermal monitor thus allows the processor and system thermal solutions to be designed much closer to the power envelopes of real applications, instead of being designed to the much higher maximum processor power envelopes. The thermal monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks. The processor clocks are modulated when the thermal control circuit (TCC) is activated. The thermal monitor uses two modes to activate the TCC: Automatic mode and On- Demand mode. Automatic mode is required for the processor to operate within specifications and must first be enabled via BIOS. Once automatic mode is enabled, the TCC will activate only when the internal die temperature is very near the temperature limits of the processor. When TCC is enabled, and a high temperature situation exists (i.e. TCC is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30-50%). An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss. Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. Once the temperature has returned to a non-critical level, modulation ceases and TCC goes inactive. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. Processor performance will be decreased by approximately the same amount as the duty cycle when the TCC is active, however, with a properly designed and characterized thermal solution, the TCC will only be activated briefly when running the most power intensive applications in a high ambient temperature environment. For automatic mode, the duty cycle is factory configured and cannot be modified. Also, automatic mode does not require any additional hardware, software drivers or interrupt handling routines. The TCC may also be activated via On-Demand mode. If bit 4 of the ACPI Thermal Monitor Control register is written to a 1 the TCC will be activated immediately, independent of the processor temperature. When using On-Demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Thermal Monitor Control register. In automatic mode, the duty cycle is fixed, however in On-Demand mode, the duty cycle Demand mode may be used at the same time Automatic mode is enabled, however, if the system tries to enable the TCC via On-Demand mode at the same time automatic mode is enabled AND a high temperature condition exists, the duty cycle of the automatic mode will override the duty cycle selected by the On-Demand mode.

Thermal Specifications and Design Considerations

92 Mobile Intel Pentium 4 Processor-M Datasheet

An external signal, PROCHOT# (processor hot) is asserted when the processor die temperature has reached its thermal limit. If the TCC is enabled (note that the TCC must be enabled for the processor to be operating within spec), TCC will be active when the PROCHOT# signal is active. The temperature at which the thermal control circuit activates is not user configurable and is not software visible. Bus snooping and interrupt latching are active while the TCC is active. Besides the thermal sensor and TCC, the thermal monitor feature also includes one ACPI register, performance monitoring logic, bits in three model specific registers (MSR), and one I/O pin (PROCHOT#). All are available to monitor and control the state of the thermal monitor feature. Thermal monitor can be configured to generate an interrupt upon the assertion or de-assertion of PROCHOT#. If automatic mode is disabled the processor will be operating out of specification. Regardless of enabling of the automatic or On-Demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 135 °C. At this point the system bus signal THERMTRIP# will go active and stay active until RESET# has been initiated. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. If THERMTRIP# is asserted, processor core voltage CC) must be removed within the timeframe defined in Table 22.

1. Configuration and Low Power Features

7.1 Power-On Configuration Options

RESET#. For specifications on these options, please refer to Table 41. locked during manufacturing and can only be operated at the rated frequency. options cannot be changed except by another reset. All resets reconfigure the processor. NOTE: Asserting this signal during RESET# will select the corresponding option.

7.2 Clock Control an d Low Power States

visual representation of the processor low-power states.

7.2.1 Normal State

This is the normal operating state for the processor.

7.2.2 AutoHALT Powerdown State

immediately initialize itself. Table 41. Power-On Configuration Option Pins

94 Mobile Intel Pentium 4 Processor-M Datasheet

III: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state. While in AutoHALT Powerdown state, the processor will process bus snoops.

7.2.3 Stop-Grant State

after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. state. In addition, all other input pins on the system bus should be driven to the inactive state. and can be serviced by software upon exit from the Stop-Grant state. only be de-asserted ten or more bus clocks after the deassertion of SLP#. assertion of the SLP# signal. Figure 35. Clock Control States

Configuration and Low Power Features Mobile Intel Pentium 4 Processor-M Datasheet 95 While in the Stop-Grant State, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process a system bus snoop.

7.2.4 HALT/Grant Snoop State

The processor will respond to snoop transactions on the system bus while in Stop-Grant state or in AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the system bus has been serviced (whether by the processor or another agent on the system bus). After the snoop is serviced, the processor will return to the Stop-Grant state or AutoHALT Power Down state, as appropriate.

7.2.5 Sleep State

The Sleep state is a low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is in the Stop Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation. Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will cause unpredictable behaviour. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the system bus while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behaviour. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence. While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state, by asserting the DPSLP# pin. (See Section 7.2.6.) Once in the Sleep or Deep Sleep states, the SLP# pin must be de-asserted if another asynchronous system bus event needs to occur. The SLP# pin has a minimum assertion of one BCLK period. When the processor is in Sleep state, it will not respond to interrupts or snoop transactions.

7.2.6 Deep Sleep State

Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep Sleep state is entered by asserting the DPSLP# pin. The DPSLP# pin must be de-asserted to re- enter the Sleep state. A period of 30 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep State. Once in the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.

Configuration and Low Power Features

96 Mobile Intel Pentium 4 Processor-M Datasheet

The clock may be stopped when the processor is in the Deep Sleep state in order to support the ACPI S1 state. The clock may only be stopped after DPSLP# is asserted and must be restarted before DPSLP# is deasserted. To provide maximum power conservation when stopping the clock during Deep Sleep, hold the BLCK0 input at VOL and the BCLK1 input at VOH. While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the system bus while the processor is in Deep Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behaviour.

7.2.7 Deeper Sleep State

The Deeper Sleep State is the lowest state power the processor can enter. This state is functionally identical to the Deep Sleep state but at a lower core voltage. The control signals to the voltage regulator to initiate a transition to the Deeper Sleep state are provided on the platform. Please refer the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide.

7.3 Enhanced Intel SpeedStep Technology

The Mobile Intel Pentium 4 Processor-M, when used in conjunction with the requisite Intel SpeedStep technology applet or its equivalent, supports Enhanced Intel SpeedStep technology. Enhanced Intel SpeedStep technology allows the processor to switch between two core frequencies automatically based on CPU demand, without having to reset the processor or change the system bus frequency. The processor has two bus ratios and voltages programmed into it instead of one and the GHI# signal controls which bus ratio and voltage is used. After reset, the processor will start in the lower of its two core frequencies, the “Battery Optimized” mode. An operating mode transition to the high core frequency can be made by setting GHI# low, putting the processor into the Deep Sleep state, regulating to the new VID output, and returning to the Normal state. This puts the processor into the high core frequency, or “Maximum Performance” operating mode. Going through these steps with GHI# set high, transitions the processor back to the low core frequency operating mode. The processor will drive the VID[4:0] pins with the VID of the current operating mode and the system logic is required to regulate the core voltage within specification for the driven VID.

Debug Tools Specifications Mobile Intel Pentium 4 Processor-M Datasheet 97 8. Debug Tools Specifications Please refer to the Mobile Intel Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Platform Design Guide for information regarding debug tools specifications.

8.1 Logic Analyzer Interface (LAI)

Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Mobile Intel Pentium 4 Processor-M systems. Tektronix* and Agilent* should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of Mobile Intel Pentium 4 Processor-M systems, the LAI is critical in providing the ability to probe and capture system bus signals. There are two sets of considerations to keep in mind when designing a Mobile Intel Pentium 4 Processor-M system that can make use of an LAI: mechanical and electrical.

8.1.1 Mechanical Considerations

The LAI is installed between the processor socket and the Mobile Intel Pentium 4 Processor-M. The LAI pins plug into the socket, while the Mobile Intel Pentium 4 Processor-M pins plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the Mobile Intel Pentium 4 Processor-M and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keepout volume remains unobstructed inside the system.

8.1.2 Electrical Considerations

The LAI will also affect the electrical performance of the system bus; therefore, it is critical to obtain electrical load models from each of the logic analyzer vendors to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide.