243658-020

243658-020 INTEL | Alldatasheet

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Technical content

Datasheet sections

• 1.0 Introduction
• 1.1 Terminology
• 1.1.1 Package Terminology
• 1.1.2 Processor Naming Convention
• 1.2 References
• 2.0 Electrical Specifications
• 2.1 System Bus and Vref
• 2.2 Clock Control and Low Power States
• 2.2.1 Normal State—State
• 2.2.2 AutoHALT Power Down State—State
• 2.2.3 Stop-Grant State—State
• 2.2.4 HALT/Grant Snoop State—State
• 2.2.5 Sleep State—State
• 2.2.6 Deep Sleep State—State
• 2.2.7 Clock Control
• 2.3 Power and Ground Pins
• 2.3.1 Phase Lock Loop (PLL) Power
• 2.4 Processor Decoupling
• 2.4.1 System Bus AGTL+ Decoupling
• 2.5 Voltage Identification
• 2.6 System Bus Unused Pins
• 2.7 Processor System Bus Signal Groups
• 2.7.2 System Bus Frequency Select Signal (BSEL[1:0])
• 2.8 Test Access Port (TAP) Connection
• 2.9 Maximum Ratings
• 2.10 Processor DC Specifications
• 2.11 AGTL+ System Bus Specifications
• 2.12 System Bus AC Specifications
• 3.0 System Bus Signal Simulations
• 3.1 System Bus Clock (BCLK) Signal Quality Specifications and
• 3.2 AGTL+ Signal Quality Specifications and Measurement Guidelines
• 3.3 Non-AGTL+ Signal Quality Specifications and Measurement Guidelines
• 3.3.1 Overshoot/Undershoot Guidelines
• 3.3.2 Ringback Specification
• 3.3.3 Settling Limit Guideline
• 3.4 AGTL+ Signal Quality Specifications and Measurement Guidelines
• 3.4.1 Overshoot/Undershoot Guidelines (FC-PGA/FC-PGA2 Packages)
• 3.4.2 Overshoot/Undershoot Magnitude (FC-PGA/FC-PGA2 Packages)
• 3.4.3 Overshoot/Undershoot Pulse Duration (FC-PGA/FC-PGA2
• 3.4.4 Activity Factor (FC-PGA/FC-PGA2 Packages)

Intel® Celeron® Processor up to 1.10 GHz Datasheet The Intel® Celeron® processor is designed for uni-processor based Value PC desktops and is binary compatible with previous generation Intel architecture processors. The Celeron processor provides good performance for applications running on advanced operating systems such as Microsoft* Windows*98, Windows NT*, Windows* 2000, Windows XP* and Linux*. This is achieved by integrating the best attributes of Intel processors—the dynamic execution performance of the P6 microarchitecture plus the capabilities of MMX™ technology—bringing a balanced level of performance to the Value PC market segment. The Celeron processor offers the dependability you would expect from Intel at an exceptional value. Systems based on Celeron processors also include the latest features to simplify system management and lower the cost of ownership for small business and home environments. I Available at 1.10 GHz, 1 GHz, 950 MHz,

900 MHz, 850 MHz, 800 MHz, 766 MHz,

733 MHz, 700 MHz, 667 MHz, 633 MHz,

600 MHz, 566 MHz, 533 MHz,

533A MHz, 500 MHz, 466 MHz,

433 MHz, 400 MHz, 366 MHz, 333 MHz,

and 300A MHz core frequencies with

128 KB level-two cache (on die); 300 MHz

and 266 MHz core frequencies without level-two cache. I Intel’s latest Celeron® processors in the FC-PGA/FC-PGA2 package are manufactured using the advanced 0.18 micron technology. I Binary compatible with applications running on previous members of the Intel microprocessor line. I Dynamic execution microarchitecture. I Operates on a 100/66 MHz, transaction- oriented system bus. I Specifically designed for uni-processor based Value PC systems, with the capabilities of MMX™ technology. I Power Management capabilities. I Optimized for 32-bit applications running on advanced 32-bit operating systems. I Uses cost-effective packaging technology. —Single Edge Processor (S.E.P.) Package to maintain compatibility with SC242 (processor core frequencies (MHz): 266, 300, 300A, 333, 366, 400, 433). —Plastic Pin Grid Array (PPGA) Package (processor core frequencies (MHz): 300A, 333, 366, 400, 433, 466, 500, 533). —Flip-Chip Pin Grid Array (FC-PGA / FC-PGA2) Package (processor core frequencies (MHz); 533A, 566, 600, 633, 667, 700, 733, 766, 800, 850, 900, I Integrated high-performance 32 KB instruction and data, nonblocking, level- one cache: separate 16 KB instruction and 16 KB data caches. I Integrated thermal diode. S.E.P. PackageFC-PGA2 Package FC-PGA Package Document Number: 243658-020 January 2002

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel ® Celeron® processor may contain design defects or errors known as errata which may cause the product to deviate from published specifi- cations. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtain ed by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com. Intel, Celeron, Pentium, MMX and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiarie s in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 1996–2002, Intel Corporation

Intel® Celeron® Processor up to 1.10 GHz

4 Datasheet

3.4.5 Reading Overshoot/Undershoot Specification Tables

3.4.6 Determining if a System meets the Overshoot/Undershoot

5.3.2.1 Recommended Mechanical Keep-Out Zones

6.1 Mechanical Specifications for the Boxed Intel

Intel® Celeron® Processor up to 1.10 GHz Figures 6 System Bus Reset and Configuration Timings (For the S.E.P. and

7 System Bus Reset and Configuration Timings (For the

12 BCLK, TCK, PICCLK Generic Clock Waveform at the Processor

15 Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform

31 Retention Mechanism for the Boxed Intel® Celeron

® Processor in the 32 Side View Space Requirements for the Boxed Processor in the S.E.P. 33 Front View Space Requirements for the Boxed Processor in the S.E.P.

35 Side View Space Requirements for the Boxed Processor in the PPGA

36 Conceptual Drawing of the Boxed Intel ® Celeron® Processor in the

37 Dimensions of Mechanical Step Feature in Heatsink Base for the

38 Top View Airspace Requirements for the Boxed Processor in the

Intel® Celeron® Processor up to 1.10 GHz

6 Datasheet

39 Side View Airspace Requirements for the Boxed Intel ® Celeron®

Intel® Celeron® Processor up to 1.10 GHz Tables 3I n t e l

9 System Bus AC Specifications (Clock) at the Processor Edge Fingers

10 System Bus AC Specifications (Clock) at the Processor

12 Valid Intel

13 System Bus AC Specifications (AGTL+ Signal Group) at the Processor

14 System Bus AC Specifications (AGTL+ Signal Group) at the Processor

15 Processor System Bus AC Specifications (AGTL+ Signal Group) at the

16 System Bus AC Specifications (AGTL+ Signal Group) at the Processor

17 System Bus AC Specifications (CMOS Signal Group) at the Processor

18 System Bus AC Specifications (CMOS Signal Group) at the Processor

20 System Bus AC Specifications (Reset Conditions)

21 System Bus AC Specifications (Reset Conditions) (for the

22 System Bus AC Specifications (APIC Clock and APIC I/O) at the

23 System Bus AC Specifications (APIC Clock and APIC I/O) at the

25 System Bus AC Specifications (TAP Connection) at the Processor

26 System Bus AC Specifications (TAP Connection) at the Processor

28 BCLK Signal Quality Specifications for Simulation at the Processor Core

29 BCLK/PICCLK Signal Quality Specifications for Simulation at the

30 BCLK Signal Quality Guidelines for Edge Finger Measurement

31 AGTL+ Signal Groups Ringback Tolerance Specifications at the

Intel® Celeron® Processor up to 1.10 GHz

8 Datasheet

32 AGTL+ Signal Groups Ringback Tolerance Specifications at the

33 AGTL+ Signal Groups Ringback Tolerance Guidelines for Edge Finger

34 Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the

35 Signal Ringback Guidelines for Non-AGTL+ Signal Edge Finger

36 Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the

38 66 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance at 39 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance at

41 Intel

® Celeron® Processor for the FC-PGA2 Package Thermal Design Power . 67

Intel® Celeron® Processor up to 1.10 GHz

Revision History

-020 January 2002 • Added IHS specifications for 900 MHz, 950 MHz, and 1 GHz.

• Added 566 MHz specification for CPUID of 068Ah.

Intel® Celeron® Processor up to 1.10 GHz

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Intel® Celeron® Processor up to 1.10 GHz

1.0 Introduction

The Intel® Celeron® processor is based on the P6 microarchitecture and is optimized for the Value PC market segment. The Intel Celeron processor, like the Pentium® II processor, features a Dynamic Execution microarchitecture and executes MMX™ technology instructions for enhanced media and communication performance. The Intel Celeron processor also utilizes multiple low- power states such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep to conserve power during idle times. The Intel Celeron processor is capable of running today’s most common PC applications with up to 4 GB of cacheable memory space. As this processor is intended for Value PC systems, it does not provide multiprocessor support. The Pentium II and Pentium ® III processors should be used for multiprocessor system designs. To be cost-effective at both the processor and system level, the Intel Celeron processor utilizes cost-effective packaging technologies. They are the S.E.P. (Single-Edge Processor) package, the PPGA (Plastic Pin Grid Array) package, the FC-PGA (Flip-Chip Pin Grid Array) package, and the FC-PGA2 (Flip-Chip Pin Grid Array) package. Refer to the Intel ® Celeron® Processor Specification Update for the latest packaging and frequency support information (Order Number 243337). Note: This datasheet describes the Intel Celeron processor for the PPGA package, FC-PGA/FC-PGA2 packages, and the S.E.P. Package versions. Unless otherwise specified, the information in this document applies to all versions and information on PGA packages, refer to both PPGA and FC-PGA packages.

1.1 Terminology

In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a signal is in the active state (based on the name of the signal) when driven to a low level. For example, when FLUSH# is low, a flush has been requested. When NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level). The term “system bus” refers to the interface between the processor, system core logic (a.k.a. the AGPset components), and other bus agents. The system bus is an interface to the processor, memory, and I/O.

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Intel® Celeron® Processor up to 1.10 GHz

1.1.1 Package Terminology

The following terms are used often in this document and are explained here for clarification:

• Processor substrate—The structure on which passive components (resistors and capacitors) are mounted.
• Processor core—The processor’s execution engine.
• S.E.P. Package—Single-Edge Processor Package, which consists of a processor substrate, processor core, and passive components. This package differs from the S.E.C. Cartridge as this processor has no external plastic cover, thermal plate, or latch arms.
• PPGA package— Plastic Pin Grid Array package. The package is a pinned laminated printed circuit board structure.
• FC-PGA — Flip-Chip Pin Grid Array. The FC-PGA uses the same 370-pin zero insertion force socket (PGA370) as the PPGA. Thermal solutions are attached directly to the back of the processor core package without the use of a thermal plate or heat spreader.
• FC-PGA2 — Flip Chip Pin Grid Array 2. The FC-PG2A uses the same 370-pin zero insertion force socket (PGA370) as the PPGA. The FC-PGA2 package contains an Integrated Heat Spreader that covers the processor die.
• Keepout zone - The area on or near a FC-PGA/FC-PGA2 packaged processor that system designs can not utilize.
• Keep-in zone - The area of a FC-PGA packaged processor that thermal solutions may utilize. Additional terms referred to in this and other related documentation:
• SC242—242-contact slot connector. A processor in the S.E.P. Package uses this connector to interface with a system board.
• 370-pin socket (PGA370)— The zero insertion force (ZIF) socket in which a processor in the PPGA package will use to interface with a system board.
• Retention mechanism—A mechanical assembly which holds the package in the SC242 connector.

1.1.2 Processor Naming Convention

listing all the FC-PGA/FC-PGA2 processors for the PGA370 socket.

1. Refer to the Intel® Celeron® Processor Specification Update for the exact CPUID for each processor.

Table 1. Processor Identification

300 MHz 300 MHz 66 065xh

366 MHz 366 MHz 66 066xh

400 MHz 400 MHz 66 066xh

433 MHz 433 MHz 66 066xh

466 MHz 466 MHz 66 066xh

500 MHz 500 MHz 66 066xh

533 MHz 533 MHz 66 066xh

566 MHz 566 MHz 66 068xh

600 MHz 600 MHz 66 068xh

633 MHz 633 MHz 66 068xh

667 MHz 667 MHz 66 068xh

700 MHz 700 MHz 66 068xh

733 MHz 733 MHz 66 068xh

766 MHz 766 MHz 66 068xh

800 MHz 800 MHz 100 068xh

850 MHz 850 MHz 100 068xh

900 MHz 900 MHz 100 068xh

950 MHz 950 MHz 100 068xh

1 GHz 1 GHz 100 068xh

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Intel® Celeron® Processor up to 1.10 GHz

1.2 References

The reader of this specification should also be familiar with material and concepts presented in the following documents:

• AP-485, Intel® Processor Identification and the CPUID Instruction (Order Number 241618)1
• AP-589, Design for EMI (Order Number 243334)1
• AP-900, Identifying Support for Streaming SIMD Extensions in the Processor and Operating System1
• AP-905, Pentium® III Processor Thermal Design Guidelines1
• AP-907, Pentium® III Processor Power Distribution Guidelines1
• Intel® Pentium® III Processor for the PGA370 Socket at 500 MHz to 933 MHz Datasheet (Order Number 245264)
• Intel® Pentium® III Processor Thermal Metrology for CPUID 068h Family1
• Intel® Pentium® III Processor Software Application Development Application Notes1
• Intel® Celeron® Processor Specification Update (Order Number 243748)
• 370-Pin Socket (PGA370) Design Guidelines (Order Number 244410)
• Intel® Architecture Software Developer's Manual (Order Number 243193) — Volume I: Basic Architecture (Order Number 243190) — Volume II: Instruction Set Reference (Order Number 243191) — Volume III: System Programming Guide (Order Number 243192)
• Intel® 440EX AGPset Design Guide (Order Number 290637)
• Intel® Celeron® Processor with the Intel® 440LX AGPset Design Guide (Order Number 245088)
• Intel® 440BX AGPset Design Guide (Order Number 290634)
• Intel® Celeron® Processor with the Intel® 440ZX-66 AGPset Design Guide (Order Number 245126)
• Intel® Celeron® Processor (PPGA) at 466 MHz Thermal Solutions Guidelines (Order Number 245156) Notes: 1. This reference material can be found on the Intel Developer’s Web site located at http://developer.intel.com. 2. For a complete listing of the Intel ® Celeron® processor reference material, refer to the Intel Developer’s Web site when this processor is formally launched. The Web site is located at http://developer.intel.com/design/celeron/.

Intel® Celeron® Processor up to 1.10 GHz

2.0 Electrical Specifications

2.1 System Bus and V REF

Celeron processor signals use a variation of the low voltage Gunning Transceiver Logic (GTL) signaling technology. The Intel Celeron processor system bus specification is similar to the GTL specification, but has been enhanced to provide larger noise margins and reduced ringing. The improvements are accomplished by increasing the termination voltage level and controlling the edge rates. Because this specification is different from the standard GTL specification, it is referred to as Assisted Gunning Transceiver Logic (AGTL+) in this document. The Celeron processor varies from the Pentium Pro processor in its output buffer implementation. The buffers that drive the system bus signals on the Celeron processor are actively driven to V CCCORE for one clock cycle during the low-to-high transition. This improves rise times and reduces overshoot. These signals should still be considered open-drain and require termination to a supply that provides the logic-high signal level. The AGTL+ inputs use differential receivers which require a reference signal (VREF). VREF is used by the receivers to determine if a signal is a logic-high or a logic-low, and is provided to the processor core by either the processor substrate (S.E.P. Package) or the motherboard (PGA370 socket). Local V REF copies should be generated on the motherboard for all other devices on the AGTL+ system bus. Termination is used to pull the bus up to the high voltage level and to control reflections on the transmission line. The processor may contain termination resistors (S.E.P. Package, FC-PGA processor system bus. Otherwise, this termination must exist on the motherboard. Solutions exist for single-ended termination as well, though this implementation changes system design and eliminate backwards compatibility for Celeron processors in the PPGA package. Single-ended termination designs must still provide an AGTL+ termination resistor on the motherboard for the RESET# signal. The AGTL+ bus depends on incident wave switching. Therefore timing calculations for AGTL+ signals are based on motherboard flight time as opposed to capacitive deratings. Analog signal simulation of the Intel Celeron processor system bus, including trace lengths, is highly recommended when designing a system. See the Pentium ® II Processor AGTL+ Layout Guidelines and the Pentium® II Processor I/O Buffer Models, Quad Format (Electronic Form) for details.

2.2 Clock Control and Low Power States

Celeron processors allow the use of AutoHALT, Stop-Grant, Sleep, and Deep Sleep states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 1 for a visual representation of the Intel Celeron processor low power states. For the processor to fully realize the low current consumption of the Stop-Grant, Sleep, and Deep Sleep states, a Model Specific Register (MSR) bit must be set. For the MSR at 02Ah (hex), bit 26 must be set to a ‘1’ (this is the power on default setting) for the processor to stop all internal clocks during these modes. For more information, see the Pentium ® II Processor Developer's Manual (Order Number 243502).

16 Datasheet

2.2.1 Normal State—State 1

This is the normal operating state for the processor.

2.2.2 AutoHALT Power Down State—State 2

LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself. Volume III: System Programmer's Guide (Order Number 243192) for more information. The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state. Figure 1. Clock Control State Machine

1. Auto HALT Power Down State

Snoops and interrupts allowed.

1. Auto HALT Power Down State

Snoops and interrupts allowed. Snoops and interrupts allowed. Snoops and interrupts allowed. No Snoops and interrupts allowed.

Intel® Celeron® Processor up to 1.10 GHz

2.2.3 Stop-Grant State—State 3

The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted. Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to VTT) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the system bus should be driven to the inactive state. BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched and can be serviced by software upon exit from Stop-Grant state. FLUSH# will not be serviced during Stop-Grant state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal. A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the assertion of the SLP# signal. While in the Stop-Grant State, SMI#, INIT#, and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state.

2.2.4 HALT/Grant Snoop State—State 4

The processor will respond to snoop transactions on the Celeron processor system bus while in Stop-Grant state or in AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the Intel Celeron processor system bus has been serviced (whether by the processor or another agent on the Intel Celeron processor system bus). After the snoop is serviced, the processor will return to the Stop-Grant state or AutoHALT Power Down state, as appropriate.

2.2.5 Sleep State—State 5

The Sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted, causing the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or AutoHALT states. Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will cause unpredictable behavior. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#) are allowed on the system bus while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence.

18 Datasheet

Intel® Celeron® Processor up to 1.10 GHz While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep state, by stopping the BCLK input. (See Section 2.2.6.) Once in the Sleep state, the SLP# pin can be deasserted if another asynchronous system bus event occurs. The SLP# pin has a minimum assertion of one BCLK period.

2.2.6 Deep Sleep State—State 6

The Deep Sleep state is the lowest power state the processor can enter while maintaining context. The Deep Sleep state is entered by stopping the BCLK input (after the Sleep state was entered from the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BLCK is stopped. It is recommended that the BLCK input be held low during the Deep Sleep State. Stopping of the BCLK input lowers the overall current consumption to leakage levels. To re-enter the Sleep state, the BCLK input must be restarted. A period of 1 ms (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep State. Once in the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state. While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals are allowed on the system bus while the processor is in Deep Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.

2.2.7 Clock Control

BCLK provides the clock signal for the processor and on die L2 cache. During AutoHALT Power Down and Stop-Grant states, the processor processes a system bus snoop. The processor does not stop the clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance into the Halt/Grant Snoop state allows the L2 cache to be snooped, similar to the Normal state. When the processor is in the Sleep or Deep Sleep states, it does not respond to interrupts or snoop transactions. During the Sleep state, the internal clock to the L2 cache is not stopped. During the Deep Sleep state, the internal clock to the L2 cache is stopped. The internal clock to the L2 cache will be restarted only after the internal clocking mechanism for the processor is stable (i.e., the processor has re-entered Sleep state). PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant states. PICCLK can be removed during the Sleep or Deep Sleep states. When transitioning from the Deep Sleep state to the Sleep state, PICCLK must be restarted with BCLK.

2.3 Power and Ground Pins

There are five pins defined on the S.E.P. Package for voltage identification (VID) and four pins on the PPGA, FC-PGA, and FC-PGA2 packages. These pins specify the voltage required by the processor core. These have been added to cleanly support voltage specification variations on current and future Celeron processors. For clean on-chip power distribution, Intel Celeron processors in the S.E.P. Package have 27 V CC (power) and 30 VSS (ground) inputs. The 27 VCC pins are further divided to provide the different voltage levels to the components. VCCCORE inputs for the processor core account for 19 of the VCC pins, while 4 VTT inputs (1.5 V) are used to provide a AGTL+ termination voltage to the processor. For only the S.E.P. Package, one VCC5 pin is provided for V oltage Transient Tools. VCC5 and VCCCORE must remain electrically separated from each other.

Intel® Celeron® Processor up to 1.10 GHz The PPGA package has more power (88) and ground (80) pins than the S.E.P. Package. Of the power pins, 77 are used for the processor core (VCCCORE) and 8 are used as a AGTL+ reference voltage (VREF). The other 3 power pins are VCC1.5, VCC2.5 and VCCCMOS and are used for future processor compatibility. FC-PGA/FC-PGA2 packages have 77 VCCCORE, 77 ground pins, eight VREF, one VCC1.5, one VCC2.5, and one VCCCMOS. VCCCORE inputs supply the processor core, including the on-die L2 cache. The VREF inputs are used as the AGTL+ reference voltage for the processor. The VCCCMOS pin is provided as a feature for future processor support in a flexible design. In such a design, the VCCCMOS pin is used to provide the CMOS voltage for use by the platform. Additionally, 2.5 V must be provided to the VCC2.5 input and 1.5 V must be provided to the Vcc1.5 input. The processor routes the CMOS voltage level through the package that it is compatible with. For example, processors requiring 1.5 V CMOS voltage levels route 1.5 V to the VCCCMOS output. Each power signal, regardless of package, must meet the specifications stated in Table 4. In addition, all VCCCORE pins must be connected to a voltage island while all VSS pins have to connect to a system ground plane. In addition, the motherboard must implement the VTT pins as a voltage island or large trace. Similarly, all VSS pins must be connected to a system ground plane.

2.3.1 Phase Lock Loop (PLL) Power

It is highly critical that phase lock loop power delivery to the processor meets Intel’s requirements. A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated, decoupled power source for the internal PLL.

2.4 Processor Decoupling

Due to the large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This causes voltages on power planes to sag below their nominal values if bulk decoupling is not adequate. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 5. Failure to do so can result in timing violations or a reduced lifetime of the component.

2.4.1 System Bus AGTL+ Decoupling

The S.E.P. Package and FC-PGA/FC-PGA2 packages contain high frequency decoupling capacitance on the processor substrate, where the PPGA package does not. Therefore, Celeron processors in the PGA packages require high frequency decoupling on the system motherboard. Bulk decoupling must be provided on the motherboard for proper AGTL+ bus operation for all packages. See AP-585, Pentium ® II Processor AGTL+ Guidelines (Order Number 243330), AP- 587, Pentium® II Processor Power Distribution Guidelines (Order Number 243332), and the Pentium® II Processor Developer's Manual (Order Number 243502) for more information.

20 Datasheet

2.5 Voltage Identification

voltage from a compatible voltage regulator. There are five VID pins (VID[4:0]) on the S.E.P. Celeron processors in the PGA package that require more than 2.05 V (see Table 2). allow for compatibility with current and future Intel Celeron processors. slot (S.E.P. Package only), as long as the power supply used does not affect the VID signals. Detection logic and pull-ups should not affect VID inputs at the power source (see Section 7.0). external resistors to the power source of the regulator. pull-ups. In addition, the power supply must supply the requested voltage or disable itself.

1. 0 = Processor pin connected to V SS.
2. 1 = Open on processor; may be pulled up to TTL V IH on motherboard.
3. The Celeron processor core uses a 2.0 V power source.

Table 2. Voltage Identification Definition

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Intel® Celeron® Processor up to 1.10 GHz

2.6 System Bus Unused Pins

All RESERVED pins must remain unconnected. Connection of these pins to VCCCORE, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future Celeron processor products. See Section 5.0 for a pin listing of the processor and the location of each RESERVED pin. For Intel Celeron processors in the S.E.P. Package, the TESTHI pin must be at a logic-high level when the core power supply comes up. For more information, please refer to erratum C26 of the Intel ® Celeron® Processor Specification Update (Order Number 243748). Also note that the TESTHI signal is not available on Intel Celeron processors in the PGA package. PICCLK must be driven with a valid clock input and the PICD[1:0] lines must be pulled-up to 2.5 V even when the APIC will not be used. A separate pull-up resistor must be provided for each PICD line. For reliable operation, always connect unused inputs or bi-directional signals to their deasserted signal level. The pull-up or pull-down resistor value is system dependent and should be chosen such that the logic-high (V IH) and logic-low (VIL) requirements are met. For the S.E.P. Package, unused AGTL+ inputs should not be connected as the package substrate has termination resistors. On the other hand, the PGA packages do not have AGTL+ termination in their package and must have any unused AGTL+ inputs terminated through a pull-up resistor. For designs that intend to only support the FC-PGA/FC-PGA2 processors, unused AGTL+ inputs will be terminated by the processor’s on-die termination resistors and, thus, do not need to be terminated on the motherboard. However, the reset pin should always be terminated on the motherboard. For unused CMOS inputs, active-low signals should be connected through a pull-up resistor to meet V IH requirements and active-high signals should be connected through a pull-down resistor to meet VIL requirements. Unused CMOS outputs can be left unconnected. A resistor must be used when tying bi-directional signals to power or ground. For any signal pulled to either power or ground, a resistor will allow for system testability.

2.7 Processor System Bus Signal Groups

To simplify the following discussion, the Celeron processor system bus signals have been combined into groups by buffer type. All Celeron processor system bus outputs are open drain and require a high-level source provided externally by the termination or pull-up resistor. AGTL+ input signals have differential input buffers, which use V REF as a reference signal. AGTL+ output signals require termination to 1.5 V . In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. EMI pins (S.E.P. Package only) should be connected to motherboard ground and/or to chassis ground through zero ohm (0 Ω ) resistors. The zero ohm resistors should be placed in close proximity to the SC242 connector. The path to chassis ground should be short in length and have a low impedance. The PWRGOOD, BCLK, and PICCLK inputs can each be driven from ground to 2.5 V . Other CMOS inputs (A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI, SLP#, and STPCLK#) must be pulled up to V CCCMOS. In addition, the CMOS, APIC, and TAP outputs are

22 Datasheet

for descriptions of these signals.

1. See Section 7.0 for information on the PWRGOOD signal.
2. See Section 7.0 for information on the SLP# signal.
3. See Section 7.0 for information on the THERMTRIP# signal.

operation for the FC-PGA/FC-PGA2 packages.

1. VCCCORE is the power supply for the processor core.

VID[4:0] and VID[3:0] are described in Section 2.0. VTT is used to terminate the system bus and generate V REF on the processor substrate. VCC5 is not connected to the Celeron processor. This supply is used for Voltage Transient Tools. SLOTOCC# is described in Section 7.0. BSEL is described in Section 2.7.2 and Section 7.0. EMI pins are described in Section 7.0. processor and may be left as a no-connect for “Intel Celeron processor-only” designs.

1. Only applies to Intel Celeron processors in the PPGA and FC-PGA/FC-PGA2 packages.
2. The BR0# pin is the only BREQ# signal that is bidirectional. See Section 7.0 for more information.
3. These signals are specified for 2.5 V operation.

10.BSEL1 is not used in Celeron processors. provided for this signal on FC-PGA/FC-PGA2 packages. 13.Only applies to Intel Celeron processors in the FC-PGA/FC-PGA2 packages. Table 3. Intel ® Celeron® Processor System Bus Signal Groups

Intel® Celeron® Processor up to 1.10 GHz 2.7.1 Asynchronous Vs. Synchronous for System Bus Signals All AGTL+ signals are synchronous to BCLK. All of the CMOS, APIC, and TAP signals can be applied asynchronously to BCLK. All APIC signals are synchronous to PICCLK. All TAP signals are synchronous to TCK.

2.7.2 System Bus Frequency Select Signal (BSEL[1:0])

The BSEL pins have two functions. First, they can act as outputs and can be used by an external clock generator to select the proper system bus frequency. Second, they can act as an inputs and can be used by a system BIOS to detect and report the processor core frequency. See the Intel® Celeron® Processor with the Intel® 440ZX-66 AGPset Design Guide (Order Number 245126) for an example implementation of BSEL. logic-low on BSEL0 is defined as 66 MHz. On the FC-PGA/FC-PGA2 packages a logic low on both BSEL0 and BSEL1 are defined as 66 MHz and are 3.3V tolerant.

2.8 Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the Celeron processor be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting a Vcc CMOS (1.5V or 2.5 V) input. Similar considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be required with each driving a different voltage level. A Debug Port may be placed at the start and end of the TAP chain with the TDI of the first component coming from the Debug Port and the TDO from the last component going to the Debug Port.

2.9 Maximum Ratings

Table 4 contains the Celeron processor stress ratings only. Functional operation at the absolute maximum and minimum is not implied nor guaranteed. The processor should not receive a clock while subjected to these conditions. Functional operating conditions are given in the AC and DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor contains protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid high static voltages or electric fields.

24 Datasheet

1. Operating voltage is the voltage to which the component is designed to operate. See Table 5.
2. This rating applies to the V CCCORE, VCC5, and any input (except as noted below) to the processor.
3. Parameter applies to CMOS, APIC, and TAP bus signal groups only.
4. The electrical and mechanical integrity of the processor edge fingers are specified to last for 50 insertion/
5. Input voltage can never exceed V
6. Input voltage can never go below V TT - 2.18 volts.
7. Parameter applies to CMOS (except BCLK, PICCLK, and PWRGOOD), APIC, and TAP bus signal groups

only for VinCMOS on the FC-PGA/FC-PGA2 Packages only.

2.10 Processor DC Specifications

Section 7.0 for signal definitions and Section 5.0 for signal listings. Most of the signals on the Intel Celeron processor system bus are in the AGTL+ signal group. interface at non-AGTL+ levels. The DC specifications for these pins are listed in Table 7. read all notes associated with each parameter. Table 4. Absolute Maximum Ratings

• FC-PGA/FC-PGA2 –0.5 2.1 V VinAGTL+ AGTL+ buffer DC input voltage with respect to VSS
• F C - P G A / F C - P G A 2 V TT - 2.18 2.18 V 7, 8 VinCMOS CMOS buffer DC input voltage with respect to VSS
• F C - P G A / F C - P G A 2 V TT - 2.18 -0.58 2.18 3.18 V V 7, 8, 9 IVID Max VID pin current 5 mA ISLOTOCC# Max SLOTOCC# pin current 5 mA 5 ICPUPRES# Max CPUPRES# pin current 5 mA 6 Mech Max Edge Fingers5 Mechanical integrity of processor edge fingers 50 Insertions/ Extractions 4, 5

Table 5. Voltage and Current Specifications (Sheet 1 of 5)

266 MHz 0650h

566 MHz

600 MHz

633 MHz

667 MHz

700 MHz

733 MHz

766 MHz

26 Datasheet

800 MHz

850 MHz

900 MHz

950 MHz

1.10 GHz

• SC242 edge fingers — — –0.085 — 0.100 V 7
• PPGA processor pins — — -0.089 — 0.100 V 8
• FC-PGA/ FC-PGA2 processor pins

Table 5. Voltage and Current Specifications (Sheet 2 of 5)

• SC242 edge fingers — — –0.140 — 0.140 V 7
• P P G A processor pins — — -0.144 — 0.144 V 8
• F C - P G A / FC-PGA2 processor pins -0.130 -0.110 — 0.080

0.080 V 17

266 MHz —

Table 5. Voltage and Current Specifications (Sheet 3 of 5)

28 Datasheet

266 MHz

Table 5. Voltage and Current Specifications (Sheet 4 of 5)

• S.E.P.P and PPGA ——— — 0 . 9 0 A
• F C - P G A / ICCCMOS ICC for VCCCMOS
• S.E.P.P and PPGA ——— — 5 0 0 m A
• F C - P G A / FC-PGA2 ——— — 2 5 0 m A dICCCORE/dt Power supply current slew rate
• PPGA and FC-PGA/ FC-PGA2 dI CCVTT/dt Termination current slew rate ——— — 8 A / µ s See Table 8, Table 20, Table 22

Table 5. Voltage and Current Specifications (Sheet 5 of 5)

30 Datasheet

Intel® Celeron® Processor up to 1.10 GHz NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. V CCCORE and ICCCORE supply the processor core. 3. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. 4. Use the Typical Voltage specification with the Tolerance specifications to provide correct voltage regulation to the processor. 5. VTT must be held to 1.5 V ± 9%. It is recommended that V TT be held to 1.5 V ± 3% while the Celeron ® processor system bus is idle. This is measured at the processor edge fingers. 6. These are the tolerance requirements, across a 20 MHz bandwidth, at the SC242 connector pin on the bottom side of the baseboard. The requirements at the SC242 connector pins account for voltage drops (and impedance discontinuities) across the connector, processor edge fingers, and to the processor core. V CCCORE must return to within the static voltage specification within 100 µs after a transient event. 7. These are the tolerance requirements, across a 20 MHz bandwidth, at the processor edge fingers. The requirements at the processor edge fingers account for voltage drops (and impedance discontinuities) at the processor edge fingers and to the processor core. V CCCORE must return to within the static voltage specification within 100 µs after a transient event. 8. These are the tolerance requirements, across a 20 MHz bandwidth, at the top of the PPGA package. VCCCORE must return to within the static voltage specification within 100 µs after a transient event. 9. Max ICCCORE measurements are measured at VCCCORE max voltage (VCCCORE_TYP + maximum static tolerance), under maximum signal loading conditions. 10.Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output voltage, at maximum current output, is no greater than the nominal (i.e., typical) voltage level of V CCCORE (VCCCORE_TYP). In this case, the maximum current level for the regulator, ICCCORE_REG, can be reduced from the specified maximum current ICCCORE_MAX and is calculated by the equation: ICCCORE_REG = ICCCORE_MAX × VCCCORE_TYP/(VCCCORE_TYP + VCCCORE Tolerance, Transient) 11.The current specified is the current required for a single Intel Celeron processor. A similar amount of current is drawn through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended termination is used (see Section 2.1). 12.The current specified is also for AutoHALT state. 13.Maximum values are specified by design/characterization at nominal V CCCORE. 14.Based on simulation and averaged over the duration of any change in current. Use to compute the maximum inductance tolerable and reaction time of the voltage regulator. This parameter is not tested. 15.dICC/dt specifications are measured and specified at the SC242 connector pins. 16.FC-PGA/FC-PGA2 packages only 17.These are the tolerance requirements across a 20 MHz bandwidth at the FC-PGA/FC-PGA2 socket pins on the solder side of the motherboard. V CCCORE must return to within the static voltage specification within 100 µs after a transient event. 18.PGA only 19.S.E.P Package and FC-PGA/FC-PGA2 Packages only 20.These processors implement independent V TT and VCCCORE power planes. 21.For processors with CPUID of 0686h, the I SGNT is 2.5 A. 22.For processors with CPUID of 0686h, the I SLP is 2.5 A. 23.For processors with CPUID of 0686h, the I DSLP is 2.2 A. 24.This specification is applicable only for processor frequencies of 933 MHz and above. 25.This Intel ® Celeron® processor is a Telecommunications and Embedded Group (TSEG) and Embedded Intel Architecture Division (EID) product only.

1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies and cache
2. VIH and VOH for the Intel Celeron processor may experience excursions of up to 200 mV above V TT for a
3. Parameter correlated to measurement into a 25 Ω resistor terminated to 1.5 V.
4. IOH for the Intel Celeron processor may experience excursions of up to 12 mA for a single system bus clock.
5. Refer to the I/O Buffer Models for IV characteristics.
6. Steady state input voltage must not be above V

Table 6. AGTL+ Signal Groups DC Specifications

• FC-PGA/FC-PGA2 –0.150 V REF – 0.200 V 9 VIH Input High Voltage
• S.E.P.P and PPGA 1.22 V TT V2 , 3
• F C - P G A / F C - P G A 2 VREF + 0.200 V TT V2 , 3 RON Buffer On Resistance 16.67 Ω 8 IL Leakage Current for inputs, outputs, and I/O ±100 µA 6, 7

32 Datasheet

1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. Parameter measured at 14 mA (for use with TTL inputs) for S.E.P Package and PPGA Package. It is 9 mA

for FC-PGA/FC-PGA2 packages. IN ≤ 2.5 V +5%) for PPGA package and S.E.P package only.

1. (0≤ VIN ≤ 1.5V +3%) for FC-PGA/FC-PGA2 packages only.
2. (0≤ VOUT ≤ 1.5V +3%) for FC-PGA/FC-PGA2 packages only.
3. Applies to non-AGTL+ signals BCLK, PICCLK, and PWRGOOD for FC-PGA/FC-PGA2 Packages only.
4. Applies to non-AGTL+ signals except BCLK, PICCLK, and PWRGOOD for FC-PGA/FC-PGA2 packages
5. These values are specified at the processor pins for FC-PGA/FC-PGA2 packages only.

Table 7. Non-AGTL+ Signal Group DC Specifications

• S.E.P.P and PPGA N/A 2.625 V All outputs are open- drain to 2.5 V +5%
• F C - P G A / F C - P G A 2 V TT V6 , 8 , 9 IOL Output Low Current
• S.E.P.P and PPGA 14 mA
• FC-PGA/FC-PGA2 9 mA 9 IL Leakage Current for Inputs, Outputs, and I/O ±100 µA 3, 4, 5, 6

2.11 AGTL+ System Bus Specifications

Number 245088) for more information.

• ±20% tolerance (S.E.E.P. and PPGA)
• ±15% tolerance (FC-PGA/FC-PGA2) It is also important that the intrinsic trace capacitance for the AGTL+ signal group traces is known and well-controlled. For more details on AGTL+, see the Pentium® II Processor Developer's Manual (Order Number 243502) and AP-585, Pentium® II Processor AGTL+ Guidelines (Order Number 243330). NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies. 2. V TT must be held to 1.5 V ± 9%; dI CCVTT/dt is specified in Table 5. It is recommended that VTT be held to 1.5 V ± 3% while the Intel Celeron processor system bus is idle. This is measured at the processor edge fingers. 3. V REF is generated on the processor substrate to be 2/3 VTT nominally with the S.E.P. package. It must be created on the motherboard for processors in the PPGA package. processor system bus is idle (static condition). This is measured at the PGA370 socket pins on the bottom side of the baseboard. 5. The value of the on-die R TT is determined by the resistor value measured by the RTTCTRL signal pin. The on-die RTT tolerance is ±15% based on the RTTCTRL resistor pull-down of ±1%. See Section 7.0 for more details on the RTTCTRL signal. Refer to the recommendation guidelines for the specific chipset/processor combination. 6. V REF is generated on the motherboard and should be 2/3 V TT ±2% nominally. Insure that there is adequate VREF decoupling on the motherboard.

Table 8. Processor AGTL+ Bus Specifications

• F C - P G A / F C - P G A 2 1 . 5 0 V 4 RTT Termination Resistor
• S.E.P.P and PPGA 56 Ω ± 5%
• F C - P G A / F C - P G A 2 (on die RTT) 40 130 Ω 5 VREF Bus Reference Voltage
• S.E.P.P and PPGA 2/3 VTT V± 2 % 3
• FC-PGA/FC-PGA2 0.950 2/3 V TT 1.05 V 6

34 Datasheet

Intel® Celeron® Processor up to 1.10 GHz

2.12 System Bus AC Specifications

The Celeron processor system bus timings specified in this section are defined at the Intel Celeron processor edge fingers and the processor core pins. Timings specified at the processor edge fingers Package and PGA packages. Unless otherwise specified, timings are tested at the processor core during manufacturing. Timings at the processor edge fingers are specified by design characterization. See Section 7.0 for the Intel Celeron processor signal definitions. Note that at

66 MHz system bus operation, the Intel Celeron processor timings at the processor edge

fingers are identical to the Pentium II processor timings at the edge fingers. See the Pentium II Processor at 233, 266, 300, and 333 MHz (Order Number 243335) for more detail. Table 9 through Table 26 list the AC specifications associated with the Intel Celeron processor system bus. These specifications are broken into the following categories: Table 9 through Table 12 contain the system bus clock specifications, Table 13 and Table 14 contain the AGTL+ specifications, Table 17 and Table 18 are the CMOS signal group specifications, Table 20 contains timings for the Reset conditions, Table 22 and Table 23 cover APIC bus timing, and Table 25 and Table 26 cover TAP timing. For each pair of tables, the first table contains timing specifications for measurement or simulation at the processor edge fingers. The second table contains specifications for simulation at the processor core pads. All Intel Celeron processor system bus AC specifications for the AGTL+ signal group are relative to the rising edge of the BCLK input. All AGTL+ timings are referenced to VREF for both ‘0’ and ‘1’ logic levels unless otherwise specified. The timings specified in this section should be used in conjunction with the I/O buffer models provided by Intel. These I/O buffer models, which include package information, are available in Quad format as the Intel Celeron ® Processor I/O Buffer Models, Quad XTK Format (Electronic Form). AGTL+ layout guidelines are also available in AP-585, Pentium® II Processor AGTL+ Guidelines (Order Number 243330). Care should be taken to read all notes associated with a particular timing parameter.

1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 0.70 V at the processor edge

bus, etc.) are referenced at 1.00 V at the processor edge fingers.

1. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.70 V at the processor edge

signals, etc.) are referenced at 1.25 V at the processor edge fingers.

1. The internal core clock frequency is derived from the Intel Celeron processor system bus clock. The system
2. The BCLK period allows a +0.5 ns tolerance for clock driver variation.
3. This specification applies to Intel Celeron processors when operating at a system bus frequency of 66 MHz.
4. The BCLK offset time is the absolute difference needed between the BCLK signal arriving at the Intel Celeron

processor core and the core logic receive the BCLK edge concurrently.

1. See Section 3.1 for Intel Celeron processor system bus clock signal quality specifications.
2. Not 100% tested. Specified by design characterization as a clock driver requirement.

Table 9. System Bus AC Specifications (Clock) at the Processor Edge Fingers

36 Datasheet

1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the processor core

pin. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V at the processor core pins.

1. The internal core clock frequency is derived from the Intel Celeron processor system bus clock. The system
2. The BCLK period allows a +0.5 ns tolerance for clock driver variation.
3. This specification applies to the Intel Celeron processor when operating at a system bus frequency of
4. See Section 3.1 for Intel Celeron processor system bus clock signal quality specifications.
5. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be

present must be accounted for as a component of BCLK timing skew between devices.

1. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the

10.Not 100% tested. Specified by design characterization as a clock driver requirement. Table 10. System Bus AC Specifications (Clock) at the Processor

• S.E.P.P. and PPGA
• F C - P G A / F C - P G A 2 0.34 0.40 1.36 1.6 ns ns (0.5 V–2.0 V) 6, 10 10, 11 T6: BCLK Fall Time
• S.E.P.P. and PPGA
• F C - P G A / F C - P G A 2 0.34 0.40 1.36 1.6 ns ns (2.0 V–0.5 V) 6, 10 10, 11

1. Unless otherwise noted, all specifications in this table apply to Celeron processors at all frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor pin.

All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor pins.

1. Not 100% tested. Specified by design characterization as a clock driver requirement.
2. The internal core clock frequency is derived from the processor system bus clock. The system bus clock to
3. The BCLK period allows a +0.5 ns tolerance for clock driver variation. See the appropriate clock synthesizer/

driver specification for details.

1. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be

must be accounted for as a component of BCLK timing skew between devices.

1. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
2. BCLK high time is measured as the period of time above 2.0 V. BCLK low time is measured as the period of

processors operating at a system bus frequency of 66 MHz. Table 11. System Bus AC Specifications (SET Clock) 1, 2

100.00 MHz 4

38 Datasheet

1. Contact your local Intel representative for the latest information on processor frequencies and/or frequency
2. While other bus ratios are defined, operation at frequencies other than those listed are not supported.

Table 12. Valid Intel® Celeron® Processor System Bus, Core Frequency

1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 0.50 V at the processor edge
4. This specification applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor
5. Valid delay timings for these signals are specified into 50 Ω to 1.5 V and with V
6. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
7. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
8. Specification is for a minimum 0.40 V swing.
9. Specification is for a maximum 1.0 V swing.

CCCORE, and BCLK become stable.

1. Unless otherwise noted, all specifications in this table apply to all Intel ®Celeron® processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core

pin. All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V at the processor core pins.

1. This specification applies to the Intel Celeron processor operating with a 66 MHz Intel Celeron processor
2. Valid delay timings for these signals are specified into 25 Ω to 1.5 V and with V
3. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
4. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
5. Specification is for a minimum 0.40 V swing.
6. Specification is for a maximum 1.0 V swing.

CCCORE and BCLK become stable. Table 13. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Edge Table 14. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins

40 Datasheet

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are

REFerenced to the BCLK rising edge at 1.25 V at the processor pin. All GTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V at the processor pins.

1. This specification applies to the processor operating with a 66 MHz system bus only.
2. Valid delay timings for these signals are specified into 25 Ω to 1.5 V and with V
3. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
4. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.

CCCORE and BCLK become stable.

1. Unless otherwise noted, all specifications in this table apply to all Celeron processors at all frequencies and
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor pin.

All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00V at the processor pins.

1. Valid delay timings for these signals are specified into 50 Ω to 1.5 V and with V
2. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
3. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
4. Specification is for a minimum 0.40 V swing from V
5. Specification is for a maximum 1.0 V swing from V TT – 1V to VTT. This assumes an edge rate of 3 V/ns.
6. This should be measured after V CCCORE, VCCCMOS, and BCLK become stable.

10.This specification applies to the FC-PGA/FC-PGA2 packages running at 66 MHz system bus frequency. 11.This specification applies to the FC-PGA/FC-PGA2 packages running at 100 MHz system bus frequency. Table 15. Processor System Bus AC Specifications (AGTL+ Signal Group) at the Processor Table 16. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins

1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.50 V at the processor edge

fingers. All CMOS signal timings (address bus, data bus, etc.) are referenced at 1.25 V.

1. These signals may be driven asynchronously.
2. This specification only applies when the APIC is enabled and the LINT1 or LINT0 pin is configured as an

edge-triggered interrupt with fixed delivery; otherwise, specification T14 applies. cycles. PWRGOOD must rise glitch-free and monotonically to 2.5 V.

1. When driven inactive or after V CCCORE, and BCLK become stable.
2. If the BCLK signal meets its AC specification within 150 ns of turning on, then the PWRGOOD inactive pulse

IL,max until all the voltage planes meet the voltage tolerance specifications.

1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the processor core

pins. All CMOS signal timings (address bus, data bus, etc.) are referenced at 1.25 V.

1. These signals may be driven asynchronously.
2. This specification only applies when the APIC is enabled and the LINT1 or LINT0 pin is configured as an

edge-triggered interrupt with fixed delivery; otherwise, specification T14 applies.

1. When driven inactive or after V

CCCORE, and BCLK become stable.

1. If the BCLK signal meets its AC specification within 150 ns of turning on, then the PWRGOOD inactive pulse

IL,max until all the voltage planes meet the voltage tolerance specifications. cycles. PWRGOOD must rise glitch-free and monotonically to 2.5 V. Table 17. System Bus AC Specifications (CMOS Signal Group) at the Processor Edge Fingers Table 18. System Bus AC Specifications (CMOS Signal Group) at the Processor Core Pins

42 Datasheet

1. Unless otherwise noted, all specifications in this table apply to Celeron processors at all frequencies
2. These specifications are tested during manufacturing.
3. These signals may be driven asynchronously.
4. All CMOS outputs shall be asserted for at least 2 BCLKs.
5. When driven inactive or after V

CCCORE, VTT, VCCCMOS, and BCLK become stable.

1. Unless otherwise noted, all specifications in this table apply to all Intel ® Celeron® processor frequencies.
2. Unless otherwise noted, all specifications in this table apply to Celeron FC-PGA/FC-PGA2 processors at all

frequencies and cache sizes.

1. For a reset, the clock ratio defined by these signals must be a safe value (their final or a lower-multiplier)

within this delay unless PWRGOOD is being driven inactive.

1. These parameters apply to processor engineering samples only. For production units, the processor core

frequency will be determined through the processor internal logic. Table 19. System Bus AC Specifications (CMOS Signal Group) 1, 2, 3, 4 Table 20. System Bus AC Specifications (Reset Conditions) Table 21. System Bus AC Specifications (Reset Conditions) (for the FC-PGA/FC-PGA2

1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 0.7 V at the processor

edge fingers. All APIC I/O signal timings are referenced at 1.25 V at the processor edge fingers.

1. This specification applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor
2. Referenced to PICCLK rising edge.
3. For open drain signals, valid delay is synonymous with float delay.
4. Valid delay timings for these signals are specified to 2.5 V +5%.

Table 22. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Edge

44 Datasheet

1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor

core pins. All APIC I/O signal timings are referenced at 1.25 V at the processor core pins.

1. This specification applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor
2. Referenced to PICCLK rising edge.
3. For open drain signals, valid delay is synonymous with float delay.
4. Valid delay timings for these signals are specified to 2.5 V +5%.
5. Valid delay timings for these signals are specified to 1.5 V +5%.

Table 23. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Core

• S.E.P.P and PPGA
• F C - P G A / F C - P G A 2 11.0 10.5 ns ns @>2.0 V @>1.7 V T24: PICCLK Low Time
• S.E.P.P and PPGA
• F C - P G A / F C - P G A 2 11.0 10.5 ns ns @<0.5 V @<0.7 V T25: PICCLK Rise Time 0.25 3.0 ns 3 (0.5 V–2.0 V) T26: PICCLK Fall Time 0.25 3.0 ns 3 (2.0 V–0.5 V) T27: PICD[1:0] Setup Time
• S.E.P.P and PPGA
• F C - P G A / F C - P G A 2 8.0 5.0 ns ns T28: PICD[1:0] Hold Time 2.5 ns 5 5 T29: PICD[1:0] Valid Delay (S.E.P.P and PPGA only) 1.5 10.0 ns 4 5, 6, 7 T29a: PICD[1:0] Valid Delay (Rising Edge) (FC-PGA/FC-PGA2 only) 1.5 8.7 ns 4 5, 6, 8 T29b: PICD[1:0] Valid Delay (Falling Edge) (FC-PGA/FC-PGA2 only) 1.5 12.0 ns 4 5, 6, 8

1. Unless otherwise noted, all specifications in this table apply to Celeron processors at all frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor

pins. All APIC I/O signal timings are referenced at 0.75 V at the processor pins.

1. Referenced to PICCLK rising edge.
2. For open drain signals, valid delay is synonymous with float delay.
3. Valid delay timings for these signals are specified into 150 Ω load pulled up to 1.5 V.
4. Unless otherwise noted, all specifications in this table apply to all Intel ® Celeron® processor frequencies.
5. All AC timings for the TAP signals are referenced to the TCK rising edge at 0.70 V at the processor edge

fingers. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V at the processor edge fingers.

1. Not 100% tested. Specified by design characterization.
2. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
3. Referenced to TCK rising edge.
4. Referenced to TCK falling edge.
5. Valid delay timing for this signal is specified to 2.5 V +5%.
6. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and

TMS). These timings correspond to the response of these signals due to TAP operations.

1. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.

Table 24. System Bus AC Specifications (APIC Clock and APIC I/O) 1, 2, 3 Table 25. System Bus AC Specifications (TAP Connection) at the Processor Edge Fingers

46 Datasheet

1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. For the S.E.P . and PPGA packages: All AC timings for the TAP signals are referenced to the TCK rising edge
3. These specifications are tested during manufacturing, unless otherwise noted.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.

For the FC-PGA/FC-PGA2 packages: Valid delay timing for this signal is specified to 1.5 V +3%.

1. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and

TMS). These timings correspond to the response of these signals due to TAP operations.

1. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.

10.Not 100% tested. Specified by design characterization. Table 26. System Bus AC Specifications (TAP Connection) at the Processor Core Pins

1. Unless otherwise noted, all specifications in this table apply to all Celeron processors frequencies.
2. All AC timings for the TAP signals are referenced to the TCK rising edge at 0.75 V at the processor pins. All

TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the processor pins.

1. These specifications are tested during manufacturing, unless otherwise noted.
2. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
3. Referenced to TCK rising edge.
4. Referenced to TCK falling edge.
5. Valid delay timing for this signal is specified to 1.5 V (1.25 V for AGTL platforms).
6. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and

TMS). These timings correspond to the response of these signals due to TAP operations.

1. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.

10.Not 100% tested. Specified by design characterization. Table 27. System Bus AC Specifications (TAP Connection) 1, 2, 3

48 Datasheet

1. Figure 3 through Figure 10 are to be used in conjunction with Table 9 through Table 26.
2. All AC timings for the AGTL+ signals at the processor edge fingers are referenced to the
3. All AC timings for the AGTL+ signals at the processor core pins are referenced to the BCLK

1.00 V at the processor core pins.

1. All AC timings for the CMOS signals at the processor edge fingers are referenced to the
2. All AC timings for the APIC I/O signals at the processor edge fingers are referenced to the
3. All AC timings for the TAP signals at the processor edge fingers are referenced to the TCK

Figure 2. BCLK to Core Logic Offset

50 Datasheet

Figure 6. System Bus Reset and Configuration Timings (For the S.E.P. and PPGA Packages) Figure 7. System Bus Reset and Configuration Timings (For the FC-PGA/FC-PGA2 Package)

52 Datasheet

3.0 System Bus Signal Simulations

guidelines are intended for use during testing and measurement of system signal integrity. guarantee that the guidelines in Table 30, Table 33, and Table 35 will be met.

3.1 System Bus Clock (BCLK) Signal Quality Specifications

waveform for the system bus clock at the processor edge fingers.

1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. This is the Intel Celeron processor system bus clock overshoot and undershoot specification for 66 MHz
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute

specification is an absolute value. Table 28. BCLK Signal Quality Specifications for Simulation at the Processor Core

1. Unless otherwise noted, all specifications in this table apply to FC-PGA/FC-PGA2 processors frequencies
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute

voltage the BCLK/PICCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This specification is an absolute value. Table 29. BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins Figure 11. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins

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1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. This is the Intel Celeron processor system bus clock overshoot and undershoot measurement guideline.
3. The rising and falling edge ringback voltage guideline is the minimum (rising) or maximum (falling) absolute

guideline is an absolute value.

1. The BCLK at the processor edge fingers may have a dip or ledge midway on the rising or falling edge. The

midpoint voltage level of this ledge should be within the range of the guideline.

1. The ledge (V7) is allowed to have peak-to-peak oscillation as given in the guideline.

Table 30. BCLK Signal Quality Guidelines for Edge Finger Measurement Figure 12. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Edge Fingers

3.2 AGTL+ Signal Quality Specifications and Measurement

® II Processor Developer's Manual (Order Number 243502).

1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. All values specified by design characterization.
3. This specification applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor

REF + 20 mV is not supported.

1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. All values specified by design characterization.
3. See Table 36 for maximum allowable overshoot.

Developers Manual). Ringback below VREF + 100 mV or above VREF – 100 mV is not supported.

1. Intel recommends simulations not exceed a ringback value of VREF ±200 mV to allow margin for other
2. A negative value for ρ indicates that the amplitude of ringback is above VREF. (i.e., φ = –100 mV specifies the

signal cannot ringback below VREF + 100 mV).

1. φ and ρ: are measured relative to VREF. α : is measured relative to VREF + 200 mV.
2. All Ringback entering the Overdrive Region must have flight time correction.

10.Overshoot specifications for Ringback do not correspond to Overshoot specifications in Section 3.4. Table 31. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Core Table 32. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Pins

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1. Unless otherwise noted, all guidelines in this table apply to all Celeron processor frequencies.
2. All values specified by design characterization.
3. This guideline applies to Intel Celeron processors operating with a 66 MHz system bus only.

REF + 250 mV is not supported. Table 33. AGTL+ Signal Groups Ringback Tolerance Guidelines for Edge Finger Figure 13. Low to High AGTL+ Receiver Ringback Tolerance Note: High to Low case is analogous.

3.3 Non-AGTL+ Signal Quality Specifications and Measurement

1. For the FC-PGA/FC-PGA2 packages, VHI = 1.5 V for all non-AGTL+ signals except for BCLK, PICCLK, and

3.3.1 Overshoot/Undershoot Guidelines

and the FC-PGA/FC-PGA2 packages has 1.5 V or 2.5 V tolerant buffers. life of the components and make meeting the ringback specification very difficult. Figure 14. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback

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3.3.2 Ringback Specification

circumstances for non-AGTL+ signals. input buffer model. However, signals that reach the clamping voltage should be evaluated further. lists the ringback specifications for the FC-PGA/FC-PGA2 packages.

1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
3. Unless otherwise noted, all specifications in this table apply to all FC-PGA/FC-PGA2 processor frequencies

Table 34. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor Table 35. Signal Ringback Guidelines for Non-AGTL+ Signal Edge Finger Measurement Table 36. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor

Intel® Celeron® Processor up to 1.10 GHz

3.3.3 Settling Limit Guideline

Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach before its next transition. The amount allowed is 10 percent of the total signal swing (VHI – VLO) above and below its final value. A signal should be within the settling limits of its final value, when either in its high state or low state, before it transitions again. Signals that are not within their settling limit before transitioning are at risk of unwanted oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be done either with or without the input protection diodes present. Violation of the settling limit guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of the ringing increasing in the subsequent transitions.

3.4 AGTL+ Signal Quality Specifications and Measurement

Guidelines (FC-PGA/FC-PGA2 Packages)

3.4.1 Overshoot/Undershoot Guidelines (FC-PGA/FC-PGA2 Packages)

Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage or below VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast signal edge rates. The processor can be damaged by repeated overshoot events on 1.5 V or 2.5 V tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). Determining the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse direction and the activity factor (AF). Permanent damage to the processor is the likely result of excessive overshoot/undershoot. Violating the overshoot/undershoot guideline will also make satisfying the ringback specification difficult. When performing simulations to determine impact of overshoot and overshoot, ESD diodes must be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide overshoot or undershoot protection. ESD diodes modeled within Intel I/O Buffer models do not clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models are being used to characterize the FC-PGA/FC-PGA2 processor performance, care must be taken to ensure that ESD models do not clamp extreme voltage levels. Intel I/O Buffer models also contain I/O capacitance characterization. Therefore, removing the ESD diodes from an I/O Buffer model will impact results and may yield excessive overshoot/undershoot.

3.4.2 Overshoot/Undershoot Magnitude (FC-PGA/FC-PGA2 Packages)

Magnitude describes the maximum potential difference between a signal and its voltage reference level, VSS (overshoot) and VTT (undershoot). While overshoot can be measured relative to VSS using one probe (probe to signal and GND lead to VSS), undershoot must be measured relative to VTT. This can be accomplished by simultaneously measuring the VTT plane while measuring the signal undershoot. Today’s oscilloscopes can easily calculate the true undershoot waveform using a Math function where the Signal waveform is subtracted from the VTT waveform. The true undershoot waveform can also be obtained with the following oscilloscope data file analysis: Converted Undershoot Waveform = VTT– Signal_measured Note: The converted undershoot waveform appears as a positive (overshoot) signal. Note: Overshoot (rising edge) and undershoot (falling edge) conditions are separate and their impact must be determined independently.

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Intel® Celeron® Processor up to 1.10 GHz After the true waveform conversion, the undershoot/overshoot specifications shown in Table 38 and Table 39 can be applied to the converted undershoot waveform using the same magnitude and pulse duration specifications used with an overshoot waveform. Overshoot/undershoot magnitude levels must observe the Absolute Maximum Specifications listed in Table 38 and Table 39. These specifications must not be violated at any time regardless of bus activity or system state. Within these specifications are threshold levels that define different allowed pulse durations. Provided that the magnitude of the overshoot/undershoot is within the Absolute Maximum Specifications (2.18V), the pulse magnitude, duration and activity factor must all be used to determine if the overshoot/undershoot pulse is within specifications.

3.4.3 Overshoot/Undershoot Pulse Duration (FC-PGA/FC-PGA2 Packages)

Pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/ undershoot reference voltage (V os_ref = 1.635 V). The total time could encompass several oscillations above the reference voltage. Multiple overshoot/undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total pulse duration. Note: Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot pulse duration. Note: Multiple Overshoot/Undershoot events occurring within the same clock cycle must be considered together as one event. Using the worst case Overshoot/Undershoot Magnitude, sum together the individual Pulse Durations to determine the total Overshoot/Undershoot Pulse Duration for that total event.

3.4.4 Activity Factor (FC-PGA/FC-PGA2 Packages)

Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a clock. Since the highest frequency of assertion of an AGTL+ or a CMOS signal is every other clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs EVERY OTHER clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs one time in every 200 clock cycles. The specifications provided in Table 38 and Table 39 show the Maximum Pulse Duration allowed for a given Overshoot/Undershoot Magnitude at a specific Activity Factor. Each table entry is independent of all others, meaning that the Pulse Duration reflects the existence of overshoot/ undershoot events of that magnitude ONLY . A platform with an overshoot/undershoot that just meets the pulse duration for a specific magnitude where the AF < 1, means that there can be NO other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the event occurs at all times and no other events can occur). Note: Activity factor for AGTL+ signals is referenced to BCLK frequency. Note: Activity factor for CMOS signals is referenced to PICCLK frequency.

3.4.5 Reading Overshoot/Undershoot Specification Tables (FC-PGA/

1. Determine the signal group that particular signal falls into. If the signal is an AGTL+ signal

signal is a CMOS signal, use Table 39 (33 MHz CMOS signal group).

1. Determine the maximum junction temperature (Tj) for the range of processors that the system
2. Determine the Magnitude of the overshoot (relative to V SS)
3. Determine the Activity Factor (how often does this overshoot occur?)
4. From the appropriate Specification table, read off the Maximum Pulse Duration (in ns)
5. Compare the specified Maximum Pulse Duration to the signal being measured. If the Pulse

as they are mutually exclusive.

1. Corresponding Maximum Pulse Duration Specification – 3.2 ns
2. Pulse Duration (measured) – 2.0 ns

undershoot events meet the specifications. Table 37. Example Platform Information

62 Datasheet

these guidelines; otherwise, contact your Intel field representative.

1. Insure no signal (CMOS or AGTL+) ever exceed the 1.635 V; OR
2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot
3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse

(measured time < specifications) in the table (where AF=1), then the system passes. The following notes apply to Table 38 and Table 39.

1. Overshoot/Undershoot Magnitude = 2.18 V is an Absolute value and should never be exceeded
2. Overshoot is measured relative to V
3. Undershoot is measured relative to VTT
4. Overshoot/Undershoot Pulse Duration is measured relative to 1.635 V .

TT can not be subtracted from Overshoots/Undershoots.

1. Lesser Undershoot does not allocate longer or larger Overshoot.
2. Consult the appropriate layout guidelines provided in the specific platform design guide.
3. All values specified by design characterization.
4. Measurements taken at the processor socket pins on the solder-side of the motherboard.

Table 38. 66 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance at Processor Pins

1. Measurements taken at the processor socket pins on the solder-side of the motherboard.

Table 39. 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance at Processor Pins Figure 15. Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform

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3.5 Non-AGTL+ Signal Quality Specifications and Measurement

1. VHI = 1.5 V for all non-AGTL+ signals except for BCLK, PICCLK, and PWRGOOD. VHI = 2.5 V for BCLK,

PICCLK, and PWRGOOD. BCLK and PICCLK signal quality is detailed in Section 3.1. Figure 16. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback 1

Intel® Celeron® Processor up to 1.10 GHz

4.0 Thermal Specifications and Design Considerations

This section provides needed data for designing a thermal solution. However, for the correct thermal measuring processes, refer to AP-905, Intel® Pentium® III Processor Thermal Design Guidelines (Order Number 245087). For the FC-PGA/FC-PGA2 using flip chip pin grid array packaging technology, Intel specifies the junction temperature (Tjunction). For the S.E.P. package and PPGA package, Intel specifies the case temperature (Tcase).

4.1 Thermal Specifications

Table 40 provides both the Processor Power and Heatsink Design Target for Celeron processors. Processor Power is defined as the total power dissipated by the processor core and its package. Therefore, the S.E.P. Package’s Processor Power would also include power dissipated by the AGTL+ termination resistors. The overall system chassis thermal design must comprehend the entire Processor Power. The Heatsink Design Target consists of only the processor core, which dissipates the majority of the thermal power. Systems should design for the highest possible thermal power, even if a processor with a lower thermal dissipation is planned. The processor’s heatslug is the attach location for all thermal solutions. The maximum and minimum case temperatures are also specified in Table 40. A thermal solution should be designed to ensure the temperature of the case never exceeds these specifications. Refer to the Intel developer Web site at http://developer.intel.com for more information.

66 Datasheet

1. These values are specified at nominal VCCCORE for the processor core.
2. Thermal Design Power (TDP) represents the maximum amount of power the thermal solution is required to
3. The Thermal Design Power (TDP) Celeron® processors in production has been redefined. The updated TDP

processors in the platform environment while executing thermal validation type software.

1. Power density is the maximum power the processor die can dissipate (i.e., processor power) divided by the

measurement error. Diode kit measurement error must be added to the Tjunctionoffset value from the table.

1. For processors with a CPUID of 0683h, the TDP number is 11.2 W.
2. For processors with a CPUID of 0683h, the TDP number is 11.9 W.
3. For processors with a CPUID of 0683h, the TDP number is 12.6 W.

oC with a 3 oC– 5 oC margin error. Table 40. Processor Power for the PPGA and FC-PGA Packages

68 Datasheet

4.1.1 Thermal Diode

monitor the die temperature of the Intel Celeron processor for thermal management purposes. Table 42 to Table 44 provide the diode parameter and interface specifications. junction temperature can change.

1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. At room temperature with a forward bias of 630 mV.
3. n_ideality is the diode ideality factor parameter, as represented by the diode equation:
4. Not 100% tested. Specified by design characterization.
5. Intel does not support or recommend operation of the thermal diode under reverse bias.
6. Characterized at 100° C with a forward bias current of 5–300 µA.
7. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode

diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin).

1. Not 100% tested. Specified by design characterization.

Table 42. Thermal Diode Parameters (S.E.P. and PPGA Packages) Table 43. Thermal Diode Parameters (FC-PGA/FC-PGA2 Packages) Table 44. Thermal Diode Interface

Intel® Celeron® Processor up to 1.10 GHz

5.0 Mechanical Specifications

There are three package technologies which Celeron processors use. They are the S.E.P. Package, the PPGA package, and the FC-PGA/FC-PGA2 packages. The S.E.P. Package and FC-PGA/ FC-PGA2 packages contain the processor core and passive components, while the PPGA package does not have passive components. The processor edge connector defined in this document is referred to as the “SC242 connector.” See the SC242 Design Guidelines (Order Number 243397) for further details on the edge connector. The processor socket connector is defined in this document is referred to as the “370-pin socket.” See the 370-Pin Socket (PGA370) Design Guidelines (Order Number 244410) for further details on the socket. 5.1 S.E.P . Package This section defines the mechanical specifications and signal definitions for the Celeron processor in the S.E.P. Package.

5.1.1 Materials Information

The Celeron processor requires a retention mechanism. This retention mechanism may require motherboard holes to be 0.159" diameter if low cost plastic fasteners are used to secure the retention mechanisms. The larger diameter holes are necessary to provide a robust structural design that can shock and vibe testing. If captive nuts are used in place of the plastic fasteners, then either the 0.159" or the 0.140" diameter holes will suffice as long as the attach mount is used. Figure 19 with substrate dimensions is provided to aid in the design of a heatsink and clip. In Figure 20 all area on the secondary side of the substrate is zoned “keepout”, except for 25 mils around the tooling holes and the top and side edges of the substrate.

70 Datasheet

routing, simulation, and component placement on the motherboard. Figure 19. Processor Substrate Dimensions (S.E.P . Package) Figure 20. Processor Substrate Primary/Secondary Side Dimensions (S.E.P. Package)

Table 45. S.E.P. Package Signal Listing

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Table 45. S.E.P . Package Signal Listing

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Table 46. S.E.P. Package Signal Listing

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Table 46. S.E.P . Package Signal Listing

78 Datasheet

5.2 PPGA Package

5.2.1 PPGA Package Materials Information

Figure 21 and Table 47 are provided to aid in the design of a heatsink and clip. Figure 21. Package Dimensions (PPGA Package)

80 Datasheet

Table 47. Package Dimensions (PPGA Package) Table 48. Information Summary (PPGA Package)

5.2.2 PPGA Package Signal Listing

Figure 22. PPGA Package (Pin Side View)

82 Datasheet

Table 49. PPGA Package Signal Listing

84 Datasheet

86 Datasheet

Table 50. PPGA Package Signal Listing

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5.3 FC-PGA/FC-PGA2 Packages

processor in the FC-PGA and FC-PGA2 packages.

5.3.1 FC-PGA Mechanical Specifications

these dimensions in both inches and millimeters.

1. Unless otherwise specified, the following drawings are dimensioned in inches.
2. All dimensions provided with tolerances are guaranteed to be met for all normal production product.
3. Figures and drawings labeled as “Reference Dimensions” are provided for informational purposes only.

Figure 23. Package Dimensions (FC-PGA Package)

1. Capacitors and resistors may be placed on the pin-side of the FC-PGA package in the area defined by G1,

G2, and G3. This area is a keepout zone for motherboard designers. static loading parameters are listed in Table 52.

1. It is not recommended to use any portion of the processor substrate as a mechanical reference

or load bearing surface for thermal solutions.

1. Parameters assume uniformly applied loadsNOTES:
2. This specification applies to a uniform and a non-uniform load.
3. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and

Table 51. Package Dimensions (FC-PGA Package) Table 52. Processor Die Loading Parameters (FC-PGA Package)

94 Datasheet

5.3.2 Mechanical Specifications (FC-PGA2 Package)

these dimensions in both inches and millimeters. Figure 24. Package Dimensions (FC-PGA2 Package)

G3. This area is a keepout zone for motherboard designers.

1. It is not recommended to use any portion of the processor substrate as a mechanical reference

or load bearing surface for thermal solutions.

1. Parameters assume uniformly applied loads.
2. This specification applies to a uniform and a non-uniform load.
3. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and
4. See socket manufacturer’s force loading specification also to ensure compliance. Maximum static loading

listed here does not account for the maximum reaction forces on the socket tabs or pins. Table 53. Package Dimensions (FC-PGA2 Package) Table 54. Processor Case Loading Parameters (FC-PGA2 Package)

96 Datasheet

5.3.2.1 Recommended Mechanical Keep-Out Zones (FC-PGA2 Package)

Figure 25. Volumetric Keep-Out Figure 26. Component Keep-Out

5.3.3 FC-PGA/FC-PGA2 Package Signal List

socket are to be used for signal routing, simulation, and component placement on the baseboard. Figure 27 provides a pin-side view of the Intel Celeron FC-PGA/FC-PGA2 processor pin-out. Figure 27. Package Dimensions (FC-PGA/FC-PGA2 Packages)

98 Datasheet

Table 55. FC-PGA/FC-PGA2 Signal

5 AJ31 Power/Other

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3 AM2 Reserved for future use

1 AD36 Power/Other

102 Datasheet

1. VCC1.5 must be supplied by the same voltage

source supplying VTT on the motherboard.

1. Previously this pin functioned as the EDGCTRL
2. Previously, PGA370 designs defined this pin as a
3. Previously, PGA370 designs defined this pin as a
4. Intel Celeron processor in the FC-PGA/FC-PGA2

packages do not use this pin.

1. This pin is only reset for processors with a CPUID
2. This pin is reserved for Intel Celeron processors
3. For CPUID of 0681h, this is a V

068xh processors, this pin is a No Connect (NC).

Table 56. FC-PGA/FC-PGA2 Signal

1 Power/Other

6 Power/Other

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3 Reserved for future use

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1. VCC1.5 must be supplied by the same voltage

source supplying VTT on the motherboard.

1. Previously this pin functioned as the EDGCTRL
2. Previously, PGA370 designs defined this pin as a
3. Previously, PGA370 designs defined this pin as a
4. Celeron processor in the FC-PGA/FC-PGA2

packages does not make use of this pin.

1. This pin is only reset for processors with a CPUID
2. This pin is reserved for Celeron processors with a
3. For CPUID of 0681h, this is a V

068xh processors, this pin is a No Connect (NC).

4 Reserved for future use

2.5 Power/Other

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5.4 Processor Markings (PPGA/FC-PGA/FC-PGA2 Packages)

Figure 28. Top Side Processor Markings (PPGA Package) Figure 29. Top Side Processor Markings (FC-PGA Package) Figure 30. Top Side Processor Markings (FC-PGA2 Package)

Intel® Celeron® Processor up to 1.10 GHz

5.5 Heatsink Volumetric Keepout Zone Guidelines

When designing a system platform it is necessary to ensure sufficient space is left for a heatsink to be installed without mechanical interference. Due to the large number of proprietary heatsink designs, Intel cannot specify a keepout zone that covers all passive and active-fan heatsinks. It is the system designer’s responsibility to consider their own proprietary solution when designing the desired keepout zone in their system platform. Please refer to the Intel ® Celeron® Processor (PPGA) at 466 MHz Thermal Solutions Guidelines (Order Number 245156) for further guidance. Note: The heatsink keepout zones found in Section 6.0, “Boxed Processor Specifications” on page 110 refer specifically to the Boxed Processor’s active-fan heatsink. This does not reflect the worst-case dimensions that may exist with other third party passive or active-fan heatsinks. Contact your vendor of choice for their passive or active-fan heatsink dimensions to ensure that mechanical interference with system platform components does not occur.

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Intel® Celeron® Processor up to 1.10 GHz

6.0 Boxed Processor Specifications

The Celeron processor is also offered as an Intel boxed processor in the FC-PGA/FC-PGA2, PPGA, and S.E.P. Packages. Intel boxed processors are intended for system integrators who build systems from motherboards and standard components. The boxed Celeron processor in the S.E.P. Package is supplied with an attached fan heatsink. The boxed Celeron processors in FC-PGA/ FC-PGA2 and PPGA packages are supplied with unattached fan heatsinks. This section documents motherboard and system requirements for the fan heatsink that is supplied with the boxed Intel Celeron processor. This section is particularly important for OEMs that manufacture motherboards for system integrators. Unless otherwise noted, all figures in this section are dimensioned in inches. Note: Drawings in this section reflect only the specifications of the Intel boxed processor product. These dimensions should not be used as a generic keepout zone for all heatsinks. It is the system designer’s responsibility to consider their proprietary solution when designing to the required keepout zone on their system platform and chassis. Refer to the package specific Thermal / Mechanical Solution Functional Specifications for further guidance. Contact your local Intel Sales Representative for these documents.

6.1 Mechanical Specifications for the Boxed Intel ® Celeron®

This section documents the mechanical specifications of the boxed Celeron processor fan heatsink heatsink. Figure 31 shows a mechanical representation of the boxed Intel Celeron processor in a S.E.P. Package in the retention mechanism, which is not shipped with the boxed Intel Celeron processor. The space requirements and dimensions for the boxed processor in the S.E.P. Package are shown in Figure 32 and Figure 33. Also, a conceptual attachment interface to low profile retention mechanism is shown in Figure 38. Note: The heatsink airflow keepout zones found in Table 57 and Figure 38 refer specifically to the boxed processor’s active fan heatsink. This does not reflect the worst-case dimensions that may exist with other third party passive or active fan heatsinks.

112 Datasheet

6.1.1.1 Boxed Processor Heatsink Weight

6.1.1.2 Boxed Processor Retention Mechanism

retention mechanism and appropriate installation instructions. supports are not shipped with the boxed Intel Celeron processor. Processor at 233, 266, 300, and 333 MHz Datasheet (Order Number 243335). Figure 33. Front View Space Requirements for the Boxed Processor in the S.E.P. Package Table 57. Boxed Processor Fan Heatsink Spatial Dimensions for the S.E.P. Package

6.1.2 Mechanical Specifications for the PPGA Package

of the boxed Intel Celeron processor in the PPGA package. Note that the airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. shown in Figure 35. All dimensions are in inches. party passive or active fan heatsinks. Figure 34. Boxed Intel Figure 35. Side View Space Requirements for the Boxed Processor in the PPGA Package

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6.1.2.1 Boxed Processor Heatsink Weight

6.1.3 Mechanical Specifications for the FC-PGA/FC-PGA2 Packages

boxed fan heatsink orientation relative to the PGA-370 socket. interface with the processor in order to meet the processors thermal requirements. Figure 36. Conceptual Drawing of the Boxed Intel Figure 37. Dimensions of Mechanical Step Feature in Heatsink Base for the FC-PGA/

6.1.3.1 Boxed Processor Heatsink Weight

6.2 Thermal Specifications

6.2.1 Thermal Requirements for the Boxed Intel ® Celeron® Processor

6.2.1.1 Boxed Processor Cooling Requirements

heatsink. It is also recommended that the air temperature entering the fan be kept below 45 °C. integrator. The processor temperature specification is found in Section 4.0 of this document. Figure 38. Top View Airspace Requirements for the Boxed Processor in the S.E.P. Package

0.40 Min Air Space (F)

0.20 Min

116 Datasheet

Figure 39. Side View Airspace Requirements for the Boxed Intel® Celeron® Processor in the Figure 40. Volumetric Keepout Requirements for The Boxed Fan Heatsink

6.2.1.2 Boxed Processor Thermal Cooling Solution Clip

thermal cooling solution to the processor after it is installed in the 370-pin socket ZIF socket. (see Figure 41 for specifications).

6.3 Electrical Requirements for the Boxed Intel ® Celeron®

6.3.1 Electrical Requirements

Figure 41. Clip Keepout Requirements for the 370-Pin (Top View)

118 Datasheet

three wire fans DO support the motherboard-mounted fan speed monitor feature. fan power connector for the PPGA and FC-PGA/FC-PGA2 packages. Figure 42. Boxed Processor Fan Heatsink Power Cable Connector Description Table 58. Fan Heatsink Power and Signal Specifications polarizing ribs and friction locking ramp. 0.100" pin pitch, 0.025" square pin width. Waldom*/Molex* P/N 22-01-3037 or equivalent.

120 Datasheet

7.0 Processor Signal Description

this section summarize the signals by direction (output, input, and I/O). Note: Unless otherwise noted, the signals apply to S.E.P., PPGA, and FC-PGA/FC-PGA2 Packages. Table 59. Alphabetical Signal Reference (Sheet 1 of 7) The A[31:3]# (Address) signals define a 232-byte physical memory address space. A[23:3]# signals are parity-protected by the AP0# parity signal. Developer’s Manual (Order Number 243502) for details. A20M# emulates the 8086 processor's address wrap-around at the 1 MB boundary. Assertion of A20M# is only supported in real mode. the corresponding I/O Write bus transaction. snoop, or deferred reply ID match operations associated with the new transaction. their inputs on the BCLK rising edge. All external timing parameters are specified with respect to the BCLK signal. bus owner cannot issue any new transactions. specific clock edges and sampled on specific clock edges.

note: BSEL1 is not used by the Celeron processor. agent ID. The processor asserts BR0# to request the system bus. system that a processor is installed. the table below for states and values for determining the presence of a device. the appropriate pins on all Intel Celeron processor system bus agents. pins of all Intel Celeron processor system bus agents. pins of all Intel Celeron processor system bus agents. Table 59. Alphabetical Signal Reference (Sheet 2 of 7) Any value PGA370 socket not occupied.

122 Datasheet

VCCCORE with a 51 Ω ± 5% resistor. NOTE: This signal is NOT used on the FC-PGA/FC-PGA2 packages. DOS*-type floating-point error reporting. completion of this operation, the processor issues a Flush Acknowledge transaction. the corresponding I/O Write bus transaction. Manual, Volume 1: Specifications (Order Number 242690) for details. reasserting HIT# and HITM# together. optionally be converted to an external error signal (e.g., NMI) by system core logic. ignore a numeric error and continue to execute noncontrol floating-point instructions. floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 is set. the corresponding I/O Write bus transaction. processors without affecting their internal (L1) caches or floating-point registers. appropriate pins of all bus agents. processor executes its Built-in Self-Test (BIST). Table 59. Alphabetical Signal Reference (Sheet 3 of 7)

® processor. Both signals are asynchronous. The LOCK# signal indicates to the system that a transaction must occur atomically. transaction end of the last transaction. processor for proper initialization. platform design guide for implementation details. determine processor debug readiness. operation of the processors. specification. The signal must then transition monotonically to a high (2.5 V) state. Figure 43 illustrates the relationship of PWRGOOD to other system signals. throughout boundary scan operation. Table 59. Alphabetical Signal Reference (Sheet 4 of 7)

124 Datasheet

two clock cycles to define the currently active transaction type. their outputs within two clocks. appropriate pins of all processor system bus agents. of cartridge in the SC242 connector is shown below. clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Table 59. Alphabetical Signal Reference (Sheet 5 of 7) connector (i.e., no core present). Any value SC242 connector not occupied.

STPCLK# is an asynchronous input. provides the serial input needed for JTAG specification support. provides the serial output needed for JTAG specification support. THERMDN O Thermal Diode p-n junction. Used to calculate core temperature. See Section 4.1. THERMDP I Thermal Diode p-n junction. Used to calculate core temperature. See Section 4.1. THERMTRIP# is indeterminate. appropriate pins of all system bus agents. 680 ohm resistor is the suggested value for a pull down resistor on TRST#. must be provided to the VCC2.5 input and 1.5 V must be provided to the VCC1.5 input. supply for VCC1.5 must be the same one used to supply VTT. must be provided to the VCC2.5 input and 1.5 V must be provided to the VCC1.5 input. The processor re-routes the 2.5 V input to the VCCCMOS output via the package. must be provided to the VCC2.5 input and 1.5 V must be provided to the VCC1.5 input. Table 59. Alphabetical Signal Reference (Sheet 6 of 7)

126 Datasheet

7.1 Signal Summaries

Table 60 through Table 63 list attributes of the Celeron processor output, input, and I/O signals. Celeron® FC-PGA/FC-PGA2 processor with a 1.5V core voltage. by these pins, or disable itself. signal is a logic high or logic low. Table 59. Alphabetical Signal Reference (Sheet 7 of 7) Table 60. Output Signals

1. Synchronous assertion with active TRDY# ensures synchronization.

Table 61. Input Signals

128 Datasheet

Table 62. Input/Output Signals (Single Driver) Table 63. Input/Output Signals (Multiple Driver)