8XC196NU INTEL | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1.0 Product Overview
- 2.0 Nomenclature Overview
- 3.0 Pinout
- 4.0 Signals
- 5.0 Address Map
- 6.0 Electrical Characteristics
- 6.1 DC Characteristics
- 6.2 AC Characteristics
- 6.2.1 Relationship of XTAL1 to CLKOUT
- 6.2.2 Explanation of AC Symbols
- 6.2.3 AC Characteristics — Multiplexed Bus Mode
- 6.2.4 AC Characteristics — Demultiplexed Bus Mode
- 6.2.5 HOLD#, HLDA# Timings
- 6.2.6 AC Characteristics — Serial Port, Synchronous Mode
- 6.2.7 External Clock Drive
- 7.0 Thermal Characteristics
- 9.0 Datasheet Revision History
COPYRIGHT © INTEL CORPORATION, 1997 February 1997 Order Number: 272644-004 8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER The 8XC196NU is a member of Intel’s 16-bit MCS® 96 microcontroller family. The device features 1 Mbyte of linear address space, a demultiplexed bus, and a chip-select unit. The external bus can dynamically switch between multiplexed and demultiplexed operation. ■ 50 MHz Operation† ■ 1 Mbyte of Linear Address Space ■ Optional 48 Kbytes of ROM ■ 1 Kbyte of Register RAM ■ Register-register Architecture ■ Footprint and Functionally Compatible Upgrade for the 8XC196NP ■ 32 I/O Port Pins ■ 16 Prioritized Interrupt Sources ■ 4 External Interrupt Pins and NMI Pin ■ 2 Flexible 16-bit Timer/Counters with Quadrature Counting Capability ■ 3 Pulse-width Modulator (PWM) Outputs with High Drive Capability ■ Full-duplex Serial Port with Dedicated Baud-rate Generator ■ Peripheral Transaction Server † 40 MHz standard; 50 MHz is Speed Premium ■ Chip-select Unit — 6 Chip-select Pins — Dynamic Demultiplexed/Multiplexed Address/Data Bus for Each Chip Select — Programmable Wait States (0–3) for Each Chip Select — Programmable Bus Width (8- or 16-bit) for Each Chip Select — Programmable Address Range for Each Chip Select ■ Event Processor Array (EPA) with
4 High-speed Capture/Compare
■ Multiply and Accumulate Executes in 640 ns Using the 32-bit Hardware Accumulator ■ 960 ns 32/16 Unsigned Division ■ 100-pin SQFP or 100-pin QFP Package ■ Complete System Development Support ■ High-speed CHMOS Technology
Information in this document is provided in connection with Intel products. No license, express or implied, by es- toppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual prop- erty right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to specifications and product descriptions at any time, without notice. *Third-party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-548-4725
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER iv Tables 15. AC Characteristics the External Memory System Must Meet, Demultiplexed Bus Mode...30
1.0 PRODUCT OVERVIEW
between multiplexed and demultiplexed operation. Figure 1. 8XC196NU Block Diagram
24 Bytes
48 Kbytes
2 PRELIMINARY
2.0 NOMENCLATURE OVERVIEW
Figure 2. The 8XC196NU Family Nomenclature Table 1. Description of Product Nomenclature with Intel standard burn-in.
0 Without ROM
3.0 PINOUT
Figure 3. 80C196NU 100-pin SQFP Package
4 PRELIMINARY
Table 2. 80C196NU 100-pin SQFP Pin Assignment
11 A5 36 V
17 PLLEN1 42 V CC 67 V CC 92 V CC
Pin 16 = VCC , and Pin 3 = NC.
Table 3. 80C196NU 100-pin SQFP Pin Assignment Arranged by Functional Categories
6 PRELIMINARY
Figure 4. 80C196NU 100-pin QFP Package
Table 4. 80C196NU 100-pin QFP Pin Assignment
11 A3 36 V CC 61 A13 86 AD13
13 A5 38 V
8 PRELIMINARY
Table 5. 80C196NU 100-pin QFP Pin Assignment Arranged by Functional Categories
Figure 5. 83C196NU 100-pin QFP Package
10 PRELIMINARY
Table 6. 83C196NU 100-pin QFP Pin Assignment
5 EA# 30 V
Table 7. 83C196NU 100-pin QFP Pin Assignment Arranged by Functional Categories
12 PRELIMINARY
4.0 SIGNALS
Table 8. Signal Descriptions ory cycle during both multiplexed and demultiplexed bus modes. memory cycle, supporting extended addressing of the 1 Mbyte address space.
16 Mbytes (000000–FFFFFFH) and the external address space is
memory or F2080H in external memory. A19:16 are multiplexed with EPORT.3:0. access is not occurring, these pins revert to their I/O port function. receive data during the second half of the bus cycle. during the second half of the bus cycle. AD15:0 drive or receive data during the entire bus cycle. that is currently on the high byte of the internal bus. This active-high output signal is asserted only during external memory cycles. it does not remain active during the entire bus cycle. the address/data bus in multiplexed mode.
that valid data is being transferred over the upper half of the system data bus. BHE# is multiplexed with WRH#. is ignored until the bus-hold protocol is disabled (WSR.7 is cleared). BREQ# is multiplexed with P2.3. operating frequency (f). CLKOUT has a 50% duty cycle. CLKOUT is multiplexed with P2.7. FF2000–FF20FFH (F2000–F20FFH if external). CS5:0# is multiplexed with P3.5:0. access to any other memory location, the value of EA# is irrelevant. for internal and external memory, before using this dynamic switching capability. Table 8. Signal Descriptions (Continued)
14 PRELIMINARY
form on a shared output pin. EPA3:0 are multiplexed with P1.3:0. This is a standard, 4-bit, bidirectional I/O port. EPORT.3:0 are multiplexed with A19:16. imum high time is one state time. EXTINT x interrupt is enabled, the CPU executes the interrupt service routine. mand that invoked the power-saving mode. is multiplexed with P3.6, and EXTINT3 is multiplexed with P3.7. until the bus-hold protocol is disabled (WSR.7 is cleared). HLDA# is multiplexed with P2.6. An external device uses this active-low input signal to request control of the bus. HOLD# is multiplexed with P2.5. This active-high output signal is valid only during external memory bus cycles.
greater than one state time to guarantee that it is recognized. ance state, thereby isolating the device from other components in the system. device is in ONCE mode, you can debug the system using a clip-on emulator. able special-function signals. able special-function signals. This is an 8-bit, bidirectional, standard I/O port. This is a 4-bit, bidirectional, standard I/O port with high-current drive capability. Port 4 is multiplexed as follows: P4.0/PWM0, P4.1/PWM1, and P4.2/PWM2. 0 0 Standard mode; clock multiplier circuitry disabled. Internal clock equals the XTAL1 input frequency.
10 R e s e r v e d
0 1 Doubled mode; clock multiplier circuitry enabled. Internal clock is twice the XTAL1 input frequency. 1 1 Quadrupled mode; clock multiplier circuitry enabled.
16 PRELIMINARY
and frequency-pulse-widths are programmable. PWM2:0 are multiplexed with P4.2:0. PLL to stabilize before the internal CPU and peripheral clocks are enabled. (FF2000–FF2FFFH) reside in external memory. Timing pin for the return-from-powerdown circuit.
- the internal oscillator is the clock source
- the phase-locked loop (PLL) circuitry is enabled (see PLLEN2:1 signal description) The capacitor causes a delay that enables the oscillator and PLL circuitry to stabilize before the internal CPU and peripheral clocks are enabled. The capacitor is not required if your application uses powerdown mode and if both of the following conditions are true:
- an external clock input is the clock source
- the phase-locked loop circuitry is disabled If your application does not use powerdown mode, leave this pin unconnected. RXD I/O Receive Serial Data In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it func- tions as either an input or an open-drain output for data. RXD is multiplexed with P2.1.
External clock for the serial I/O baud-rate generator input (program selectable). T1CLK is multiplexed with P1.4. T2CLK is multiplexed with P1.6. T1DIR is multiplexed with P1.5. T2DIR is multiplexed with P1.7. 0, it is the serial clock output. TXD is multiplexed with P2.0. Connect each VCC pin to the digital supply voltage. Connect each VSS pin to ground through the lowest possible impedance path. asserted only during external memory writes. WR# is multiplexed with WRL#. tions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. asserted for all write operations. WRH# is multiplexed with BHE#.
18 PRELIMINARY
WRL# is multiplexed with WR#. tions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#. must meet the VIH specification for XTAL1 (see datasheet). uses a external clock source instead of the on-chip oscillator.
5.0 ADDRESS MAP
Table 9. 8XC196NU Address Map
00 FFFFH
00 E000H External device (memory or I/O) connected to address/data bus Indirect, indexed, extended
00 DFFFH
- For the 80C196NU, the program and special-purpose memory locations (FF2000–FFDFFFH) reside
xF0000–xF00FFH are reserved, write 0FFH to these locations.
- For the 80C196NU, this address range (FF2080–FFDFFFH) is always external memory. For the
EA# is at logic 1. Otherwise, they are mapped to external memory.
- Unless otherwise noted, write 0 to reserved SFR bits.
20 PRELIMINARY
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
6.0 ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS* OPERATING CONDITIONS* FXTAL 1 (Input frequency for VCC = 4.5 V – 5.5 V) NOTES: 1. This device is static and should operate below 1 Hz, but has been tested only down to 16 MHz. 2. The maximum crystal that can be used is 25 MHz. 3. The minimum XTAL1 frequency when using the PLL is 8 MHz. NOTICE : This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. *WARNING : Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability.
6.1 DC Characteristics
Table 10. DC Characteristics Over Specified Operating Conditions
- Typical values are based on a limited number of samples and are not guaranteed. The values listed
are at room temperature with VCC = 5.0 V.
- For temperatures below 100°C, typical is 10 µA.
- For all pins except P4.3:0, which have higher drive capability (see V
- During normal (non-transient) conditions, the following maximum current limits apply for pin groups
- For all pins that were weakly pulled high during RESET. This excludes ALE, INST, and NMI, which
OL 2) and ONCE, which was pulled medium low (see VOL 3).
- Pin capacitance is not tested. This value is based on design simulations.
22 PRELIMINARY
0.45 V I OL = 3 µA
0.45 V I OL = 30 µA
Table 10. DC Characteristics Over Specified Operating Conditions (Continued)
- Typical values are based on a limited number of samples and are not guaranteed. The values listed
are at room temperature with VCC = 5.0 V.
- For temperatures below 100°C, typical is 10 µA.
- For all pins except P4.3:0, which have higher drive capability (see V
- During normal (non-transient) conditions, the following maximum current limits apply for pin groups
- For all pins that were weakly pulled high during RESET. This excludes ALE, INST, and NMI, which
OL 2) and ONCE, which was pulled medium low (see VOL 3).
- Pin capacitance is not tested. This value is based on design simulations.
6.2 AC Characteristics
6.2.1 RELATIONSHIP OF XTAL1 TO CLKOUT
Figure 6. Effect of Clock Mode on CLKOUT
24 PRELIMINARY
6.2.2 EXPLANATION OF AC SYMBOLS
and its condition, respectively. Symbols represent the time between the two signal/condition points. Table 11. AC Timing Symbol Definitions
6.2.3 AC CHARACTERISTICS — MULTIPLEXED BUS MODE
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns. Table 12. AC Characteristics the 8XC196NU Will Meet, Multiplexed Bus Mode
- 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz
can be applied with an external clock source.
- When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8
MHz. The PLL cannot be run at frequencies lower than 16 MHz.
- If wait states are used, add 2t × n, where n = number of wait states.
- Assuming back-to-back bus cycles.
26 PRELIMINARY
Table 13. AC Characteristics the External Memory System Must Meet, Multiplexed Bus Mode
- If wait states are used, add 2t × n, where n = number of wait states.
- When forcing wait states using the BUSCON register, add 2t × n.
- Exceeding the maximum specification causes additional wait states.
Table 12. AC Characteristics the 8XC196NU Will Meet, Multiplexed Bus Mode (Continued)
- 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz
can be applied with an external clock source.
- When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8
MHz. The PLL cannot be run at frequencies lower than 16 MHz.
- If wait states are used, add 2t × n, where n = number of wait states.
- Assuming back-to-back bus cycles.
6.2.3.1 System Bus Timings, Multiplexed Bus
Figure 7. System Bus Timings, Multiplexed Bus Mode
28 PRELIMINARY
6.2.3.2 READY Timing, Multiplexed Bus
Figure 8. READY Timing, Multiplexed Bus Mode
6.2.4 AC CHARACTERISTICS — DEMULTIPLEXED BUS MODE
Test Conditions: Capacitive load on all pins = 50 pF, Rise and Fall Times = 3 ns. Table 14. AC Characteristics the 8XC196NU Will Meet, Demultiplexed Bus Mode
- 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz
can be applied with an external clock source.
- When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8
MHz. The PLL cannot be run at frequencies lower than 16 MHz.
- For deferred bus cycle, add 2t (1 state) if CSx# changes or if the write cycle follows a read cycle.
- If wait states are used, add 2t × n, where n = number of wait states.
- Assuming back-to-back bus cycles.
30 PRELIMINARY
Table 15. AC Characteristics the External Memory System Must Meet, Demultiplexed Bus Mode
- If wait states are used, add 2t × n, where n = number of wait states.
- For deferred bus cycle, add 2t (1 state) if CSx# changes or if the write cycle follows a read cycle.
- When forcing wait states using the BUSCON register, add 2t × n.
- Exceeding the maximum specification causes additional wait states.
Table 14. AC Characteristics the 8XC196NU Will Meet, Demultiplexed Bus Mode (Continued)
- 25 MHz is the maximum input frequency when using an external crystal oscillator; however, 50 MHz
can be applied with an external clock source.
- When the phase-locked loop (PLL) circuitry is enabled, the minimum input frequency on XTAL1 is 8
MHz. The PLL cannot be run at frequencies lower than 16 MHz.
- For deferred bus cycle, add 2t (1 state) if CSx# changes or if the write cycle follows a read cycle.
- If wait states are used, add 2t × n, where n = number of wait states.
- Assuming back-to-back bus cycles.
6.2.4.1 System Bus Timings, Demultiplexed Bus
Figure 9. System Bus Timings, Demultiplexed Bus Mode
32 PRELIMINARY
6.2.4.2 READY Timing, Demultiplexed Bus
Figure 10. READY Timing, Demultiplexed Bus Mode
to determine which control signals are affected. Figure 11. Deferred Bus Mode Timing Diagram
34 PRELIMINARY
6.2.5 HOLD#, HLDA# TIMINGS
Figure 12. HOLD#, HLDA# Timing Diagram Table 16. HOLD#, HLDA# Timings
6.2.6 AC CHARACTERISTICS — SERIAL PORT, SYNCHRONOUS MODE 0
Figure 13. Serial Port Waveform — Synchronous Mode 0 Table 17. Serial Port Timing — Synchronous Mode 0
- The minimum baud-rate (SP_BAUD) register value for receive is x002H and the minimum baud-rate
(SP_BAUD) register value for transmit is x001H.
36 PRELIMINARY
6.2.7 EXTERNAL CLOCK DRIVE
Figure 14. External Clock Drive Waveforms Figure 15. AC Testing Output Waveforms During 5.0 Volt Testing Table 18. External Clock Drive † Assumes an external clock; the maximum input frequency for an external crystal oscillator is 25 MHz.
Figure 16. Float Waveforms During 5.0 Volt Testing
38 PRELIMINARY
7.0 THERMAL CHARACTERISTICS
210997) provides quality and reliability information. 8XC196NU Specification Update (272864-001).
9.0 DATASHEET REVISION HISTORY
before finalizing a design or ordering devices.
- All references to “ADVANCE INFORMATION”
have been changed to “PRELIMINARY”.
- Table note added to Tables 4 and 6.
- Table 15, removed note (2) attachment from
- Table 15, specification change made to the fol-
lowing timings: TAVDV , TSLDV , TCLYX .
- A heading was added for Section 1.0, “Product
- List of features, the 8XC196NU has four
- The ROM SQFP (SB83C196NU) pinout and
pin assignment tables have been deleted.
- Figure 5, package designator in diagram
- Table 8, EA# signal description added.
- Table 8, signal descriptions for BREQ#,
- Table 9, redesigned and footnotes reordered.
- Figure 6, corrected to state PLLEN2:1=01 (not
- Tables 12 and 14, B-step timing added for
- Table 12, deleted notes 4 and 5, added note 2,
and reordered remaining notes.
- Table 13, deleted notes 1, 3, and 6 and reor-
- Table 14, deleted notes 4, 5, and 6, added note
2, and reordered remaining notes.
- Table 15, deleted notes 1, 3, and 6 and reor-
- Tables 13 and 15, the minimum timing for TRXDX
- Figures 7–11, updated to reflect both A- and B-
step timings on the BHE#, INST signal.
- Section 5.4.3, the second sentence of the first
paragraph, the word “and” replaced by “or”.
- Table 19, thermal characteristics specifications
have been changed and expanded.
- The errata list was replaced with a reference to
the specification update document.
- The input frequency on XTAL1, formerly called
denoted by (f) and (t), respectively.
- 25 MHz is the maximum input frequency when
50 MHz can be applied with an external clock
Table 19. Thermal Characteristics
8XC196NU COMMERCIAL CHMOS 16-BIT MICROCONTROLLER 3. The minimum frequency input with PLL in 4x mode has changed from 4 MHz to 8MHz. 4. The AC characteristics tables have been divided into the following: the timing specifica- tions met by the device, and the timing specifi- cations that must be met by the external memory system. 5. Electrical characteristics notes #2 and #3 added to section 3.0. 6. Maximum I OL and IOH specifications added to the DC characteristics tables. 7. AC timings TAVWL and TSLDV added to the AC characteristics–multiplexed bus mode tables. 8. Figure 7 added, and figures 8–12 have been revised. 9. Thermal characteristics for the 100-pin SQFP package have been added in section 1.0. 10. Specifications for the 83C196NU have been added. 11. Several AC timing specifications have changed.