21150

21150 INTEL | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1.0 Introduction
• 1.1 Architecture
• 1.2 Data Path
• 1.3 Posted Write Queue
• 1.4 Delayed Transaction Queue
• 1.5 Read Data Queue
• 2.0 Signal Pins
• 2.1 Primary PCI Bus Interface Signals
• 2.2 Secondary PCI Bus Interface Signals
• 2.3 Secondary Bus Arbitration Signals
• 2.4 General-Purpose I/O Interface Signals
• 2.5 Clock Signals
• 2.6 Reset Signals
• 2.7 Miscellaneous Signals
• 2.8 JTAG Signals
• 3.0 Pin Assignments
• 3.1 Numeric Pin Assignment
• 3.2 Alphabetic Pin Assignment
• 4.0 PCI Bus Operation
• 4.1 Types of Transactions
• 4.2 Address Phase
• 4.2.1 Single Address Phase
• 4.2.2 Dual Address Phase
• 4.3 Device Select (DEVSEL#) Generation
• 4.4 Data Phase
• 4.5 Write Transactions
• 4.5.1 Posted Write Transactions
• 4.5.2 Memory Write and Invalidate Transactions
• 4.5.3 Delayed Write Transactions
• 4.5.4 Write Transaction Address Boundaries
• 4.5.5 Buffering Multiple Write Transactions
• 4.5.6 Fast Back-to-Back Write Transactions
• 4.6 Read Transactions
• 4.6.1 Prefetchable Read Transactions
• 4.6.2 Nonprefetchable Read Transactions
• 4.6.3 Read Prefetch Address Boundaries
• 4.6.4 Delayed Read Requests
• 4.6.5 Delayed Read Completion with Target
• 4.6.6 Delayed Read Completion on Initiator Bus
• 4.7 Configuration Transactions
• 4.7.1 Type 0 Access to the
• 4.7.2 Type 1 to Type 0 Translation
• 4.7.3 Type 1 to Type 1 Forwarding
• 4.7.4 Special Cycles

21150 PCI-to-PCI Bridge

1.For 21150-AB and later revisions only. The 21150-AA does not implement this feature. n Complies fully with the PCI Local Bus Specification, Revision 2.1 n Complies fully with the Advanced Configuration Power Interface (ACPI) Specification n Complies fully with the PCI Power Management Specification, Revision 1.01 n Complies fully with Revision 1.0 of the PCI-to-PCI Bridge Architecture Specification n Implements delayed transactions for all PCI configuration, I/O, and memory read commands—up to three transactions simultaneously in each direction n Allows 88 bytes of buffering (data and address) for posted memory write commands in each direction—up to five posted write transactions simultaneously in each direction n Allows 72 bytes of read data buffering in each direction n Provides concurrent primary and secondary bus operation, to isolate traffic n Provides 10 secondary clock outputs with the following features: —Low skew permits direct drive of option slots —Individual clock disables, capable of automatic configuration during reset n Provides arbitration support for nine secondary bus devices: — A programmable 2-level arbiter — Hardware disable control, to permit use of an external arbiter n Provides a 4-pin general-purpose I/O interface, accessible through device- specific configuration space n Provides enhanced address decoding: —A 32-bit I/O address range — A 32-bit memory-mapped I/O address range — A 64-bit prefetchable memory address range — ISA-aware mode for legacy support in the first 64KB of I/O address range — VGA addressing and VGA palette snooping support n Includes live insertion support n Supports PCI transaction forwarding for the following commands: — All I/O and memory commands — Type 1 to Type 1 configuration commands — Type 1 to Type 0 configuration commands (downstream only) — All Type 1 to special cycle configuration commands n Includes downstream lock support n Supports both 5-V and 3.3-V signaling environments n Available in both 33 MHz and 66 MHz versions n Provides an IEEE standard 1149.1 JTAG interface. Order Number: 278106-002 July 1998 Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 21150 PCI-to-PCI Bridge may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners.

15.1.23 Prefetchable Memory Base Address Upper 32 Bits Register—

15.1.24 Prefetchable Memory Limit Address Upper 32 Bits Register—

8 Multiple Memory Write Transactions Posted and Initiated as Fast

viii Preliminary Datasheet

1.0 Introduction

The 21150 is a second-generation PCI-to-PCI bridge and is fully compliant with PCI Local Bus Specification, Revision 2.1. The 21150 provides full support for delayed transactions, which enables the buffering of memory read, I/O, and configuration transactions. The 21150 has separate posted write, read data, and delayed transaction queues with significantly more buffering capability than first-generation bridges. In addition, the 21150 supports buffering of simultaneous multiple posted write and delayed transactions in both directions. Among the features provided by the 21150 are a programmable 2-level secondary bus arbiter, an IEEE standard 1149.1 JTAG interface, live insertion support, a 4-pin general-purpose I/O interface, individual secondary clock disables, and enhanced address decoding. The 21150 has sufficient clock and arbitration pins to support nine PCI bus master devices directly on its secondary interface. The 21150 allows the two PCI buses to operate concurrently. This means that a master and a target on the same PCI bus can communicate while the other PCI bus is busy. This traffic isolation may increase system performance in applications such as multimedia. The 21150 makes it possible to extend a system’s load capability limit beyond that of a single PCI bus by allowing motherboard designers to add more PCI devices or more PCI option card slots than a single PCI bus can support. Figure 1 illustrates the use of two 21150 PCI-to-PCI bridges on a system board. Each 21150 that is added to the board creates a new PCI bus that provides support for the additional PCI slots or devices Option card designers can use the 21150 to implement multiple-device PCI option cards. Without a PCI-to-PCI bridge, PCI loading rules would limit option cards to one device. The PCI Local Bus Specification) loading rules limit PCI option cards to a single connection per PCI signal in the option card connector. The 21150 overcomes this restriction by providing, on the option card, an independent PCI bus to which up to nine devices can be attached. Figure 2 shows how the 21150 enables the design of a multicomponent option card.

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Figure 1. 21150 on the System Board

1.1 Architecture

• PCI interface control logic for the primary and secondary PCI interfaces
• Data path and data path control logic
• Configuration register and configuration control logic
• Secondary bus arbiter Figure 3 shows the major functional blocks of the 21150, and Table 1 describes these blocks.

Figure 2. 21150 with Option Cards

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Figure 3. 21150 on the System Board Table 1. 21150 Functional Blocks (Sheet 1 of 2) command and configuration address format translations.

1.2 Data Path

• Posted write queue
• Delayed transaction queue
• Read data queue To prevent deadlocks and to maintain data coherency, a set of ordering rules is imposed on the forwarding of posted and delayed transactions across the 21150. The queue structure, along with the order in which the transactions in the queues are initiated and completed, supports these ordering requirements. Section 6.0 describes the 21150 ordering rules in detail. See Section 4.0 for a detailed description of 21150 PCI bus operation. Figure 4 shows the 21150 data path for the downstream direction, and the following sections describe the data path queues. Secondary-to-Primary Data Path Data path for data received on the secondary interface and driven on the primary interface. This block is used for write transactions initiated on the secondary PCI bus and for returning read data for read transactions initiated on the primary PCI bus. This block contains logic to store and, for posted write transactions, to increment the address of the current transaction. This block also performs bus command and configuration address format translations Configuration Registers Configuration space registers and corresponding control logic. These registers are accessible from the primary interface only. Secondary Bus Arbiter Control Logic for secondary bus arbitration. This block receives s_req_l<8:0>, as well as the 21150 secondary bus request, and drives one of the s_gnt_l<8:0> lines or the 21150 secondary bus grant.

Table 1. 21150 Functional Blocks (Sheet 2 of 2) Figure 4. 21150 Downstream Data Path

6 Preliminary Datasheet

1.3 Posted Write Queue

The posted write queue contains the address and data of memory write transactions targeted for the opposite interface. The posted write transaction can consist of an arbitrary number of data phases, subject to the amount of space in the queue and disconnect boundaries. The posted write queue can contain multiple posted write transactions. The number of posted write transactions that can be queued at one time is dependent upon their burst size. The posted write queue consists of 88 bytes in each direction.

1.4 Delayed Transaction Queue

For a delayed write request transaction, the delayed transaction queue contains the address, bus command, 1 Dword of write data, byte enable bits, and parity. When the delayed write transaction is completed on the target bus, the write completion status is added to the corresponding entry. For a delayed read request transaction, the delayed transaction queue contains the address and bus command, and for nonprefetchable read transactions, the byte enable bits. When the delayed read transaction is completed on the target bus, the read completion status corresponding to that transaction is added to the delayed request entry. Read data is placed in the read data queue. The delayed transaction queue can hold up to three transactions (any combination of read and write transactions).

1.5 Read Data Queue

The read data queue contains read data transferred from the target during a delayed read completion. Read data travels in the opposite direction of the transaction. The primary-to- secondary read data queue contains read data corresponding to a delayed read transaction residing in the secondary-to-primary delayed transaction queue. The secondary-to-primary read data queue contains read data corresponding to a delayed read transaction in the primary-to-secondary delayed transaction queue. The amount of read data per transaction depends on the amount of space in the queue and disconnect boundaries. Read data for up to three transactions, subject to the burst size of the read transactions and available queue space, can be stored. The read data queue for the 21150 consists of 72 bytes in each direction.

2.0 Signal Pins

This chapter provides detailed descriptions of the 21150 signal pins, grouped by function. signal is asserted when it is at a high voltage level. Table 2. Signal Pins Nine request/grant pairs of pins for the secondary PCI bus. An arbiter enable control pin. interface signal pins Four general-purpose pins. Two clock inputs (one for each PCI interface). Reset signal pins A primary interface reset input. A secondary interface reset output. An input-only pin used to disable secondary clock outputs. Two input voltage signaling level pins. Three pins controlling 66 MHz operation. JTAG signal pins All JTAG pins required by IEEE standard 1149.1. Table 3. Signal Types

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2.1 Primary PCI Bus Interface Signals

Table 4 describes the primary PCI bus interface signals. Table 4. Primary PCI Bus Interface Signals (Sheet 1 of 3) p_cbe_l to a valid logic level when p_gnt_l is asserted. (one cycle after the p_ad bus is parked). complete the current data phase on the primary PCI bus. is sustained by an external pull-up resistor.

complete the current data phase on the primary PCI bus. cycle and then is sustained by an external pull-up resistor. target, indicating that the device is accepting the transaction. sustained by an external pull-up resistor.

• When p_stop_l is asserted in conjunction with p_trdy_l and p_devsel_l assertion, a disconnect with data transfer is being signaled.
• When p_stop_l and p_devsel_l are asserted, but p_trdy_l is deasserted, a target disconnect without data transfer is being signaled. When this occurs on the first data phase, that is, no data is transferred during the transaction, this is referred to as a target retry.
• When p_stop_l is asserted and p_devsel_l is deasserted, the target is signaling a target abort. When the primary bus is idle, p_stop_l is driven to a deasserted state for one cycle and then is sustained by an external pull-up resistor. p_lock_l I Primary PCI interface LOCK#. Signal p_lock_l is deasserted during the first address phase of a transaction and is asserted one clock cycle later by an initiator attempting to perform an atomic operation that may take more than one PCI transaction to complete. The 21150 samples p_lock_l as a target and can propagate the lock across to the secondary bus. The 21150 does not drive p_lock_l as an initiator; that is, the 21150 does not propagate locked transactions upstream. When released by an initiator, p_lock_l is driven to a deasserted state for one cycle and then is sustained by an external pull-up resistor. p_idsel I Primary PCI interface IDSEL#. Signal p_idsel is used as the chip select line for Type 0 configuration accesses to 21150 configuration space. When p_idsel is asserted during the address phase of a Type 0 configuration transaction, the 21150 responds to the transaction by asserting p_devsel_l.

Table 4. Primary PCI Bus Interface Signals (Sheet 2 of 3)

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• Address parity error
• Posted write data parity error on target bus
• Secondary bus s_serr_l assertion
• Master abort during posted write transaction
• Target abort during posted write transaction
• Posted write transaction discarded
• Delayed write request discarded
• Delayed read request discarded
• Delayed transaction master timeout Signal p_serr_l is pulled up through an external resistor. p_req_l TS Primary PCI bus REQ#. Signal p_req_l is asserted by the 21150 to indicate to the primary bus arbiter that it wants to start a transaction on the primary bus. When the 21150 receives a target retry or disconnect in response to initiating a transaction, the 21150 deasserts p_req_l for at least two PCI clock cycles before asserting it again. p_gnt_l I Primary PCI bus GNT#. When asserted, p_gnt_lindicates to the 21150 that access to the primary bus is granted. The 21150 can start a transaction on the primary bus when the bus is idle and p_gnt_l is asserted. When the 21150 has not requested use of the bus and p_gnt_l is asserted, the 21150 must drive p_ad, and p_par to valid logic levels.

Table 4. Primary PCI Bus Interface Signals (Sheet 3 of 3)

2.2 Secondary PCI Bus Interface Signals

Table 5 describes the secondary PCI bus interface signals. Table 5. Secondary PCI Bus Interface Signals (Sheet 1 of 3) secondary bus grant is asserted. signals are a multiplexed command field and byte enable field. secondary bus grant is asserted. bus grant is asserted (one cycle after the s_ad bus is parked).

12 Preliminary Datasheet

complete the current data phase on the secondary PCI bus. then is sustained by an external pull-up resistor. complete the current data phase on the secondary PCI bus. and then is sustained by an external pull-up resistor.

• When s_stop_l is asserted in conjunction with s_trdy_l and s_devsel_l assertion, a disconnect with data transfer is being signaled.
• When s_stop_l and s_devsel_l are asserted, but s_trdy_l is deasserted, a target disconnect without data transfer is being signaled. When this occurs on the first data phase, that is, no data is transferred during the transaction, this is referred to as a target retry.
• When s_stop_l is asserted and s_devsel_l is deasserted, the target is signaling a target abort. When the secondary bus is idle, s_stop_l is driven to a deasserted state for one cycle and then is sustained by an external pull-up resistor.

Table 5. Secondary PCI Bus Interface Signals (Sheet 2 of 3)

2.3 Secondary Bus Arbitration Signals

Table 6 describes the secondary bus arbitration signals. one cycle and then is sustained by an external pull-up resistor. transactions, and by the initiator during read transactions. s_serr_l is pulled up through an external resistor. Table 5. Secondary PCI Bus Interface Signals (Sheet 3 of 3) Table 6. Secondary PCI Bus Interface Signals (Sheet 1 of 2) request inputs, s_req_l<8:0>, into its secondary bus arbiter. The 21150 request input to the arbiter is an internal signal. transaction on the secondary PCI bus if the bus is idle. to start a transaction on the secondary bus.

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2.4 General-Purpose I/O Interface Signals

Table 7 describes the general-purpose I/O interface signals.

2.5 Clock Signals

Table 8 describes the clock signals. Table 6. Secondary PCI Bus Interface Signals (Sheet 2 of 2) Table 7. General-Purpose I/O Interface Signals Table 8. Clock Signals (Sheet 1 of 2)

2.6 Reset Signals

Table 9 describes the reset signals.

1. For 21150-AB and later revisions only

to 33 MHz, or 0 MHz to 66 MHz for a 66 MHz capable 21150. terminate them electrically. Table 8. Clock Signals (Sheet 2 of 2) Table 9. Reset Signals power state has no effect on the secondary bus clocks.

• Signal p_rst_l is asserted.
• The secondary reset bit in the bridge control register in configuration space is set.
• The chip reset bit in the diagnostic control register in configuration space is set. When the 21150 asserts s_rst_l, it tristates all secondary control signals and drives zeros on s_ad, s_cbe_l, and s_par. Signal s_rst_l remains asserted until p_rst_l is deasserted, the gpio serial clock mask has been shifted in, and the secondary reset bit is clear. Assertion of s_rst_l by itself does not clear register state, and configuration registers are still accessible from the primary PCI interface.

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2.7 Miscellaneous Signals

Table 10 describes the miscellaneous signals. Table 10. Miscellaneous Signals secondary clock outputs high.

3.3 V or 5 V, corresponding to the signaling environment of the

bus use 3.3-V signaling levels. secondary PCI bus uses 5-V signaling levels, tie s_vio to 5 V. secondary bus use 3.3-V signaling levels. should be pulled low for 33 MHz operation on the primary bus. operation on the primary bus, this signal should be pulled high.

2.8 JTAG Signals

Table 11 describes the JTAG signals. Table 11. JTAG Signals same result as if it were driven high. trst_l produces the same result as if it were driven high.

3.0 Pin Assignments

includes a diagram showing 21150 pin assignment. Figure 5 shows the 21150 pins. Table 13 and Table 14 list the pins in numeric and alphabetic order. Figure 5. 21150 Pin Assignment

20 Preliminary Datasheet

3.1 Numeric Pin Assignment

pin. Table 12 defines the signal type abbreviations. Table 12. Signal Types

Table 13. Numeric Pin Assignments (Sheet 1 of 3)

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Table 13. Numeric Pin Assignments (Sheet 2 of 3)

1. Pertains to the 21150-AB and later revisions only. For the 21150-AA, this pin was vss.
2. nc–Do not connect these pins on the board.

Table 13. Numeric Pin Assignments (Sheet 3 of 3)

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3.2 Alphabetic Pin Assignment

each pin. Table 12 defines the signal type abbreviations. Table 14. Alphabetic Pin Assignments. (Sheet 1 of 3)

Table 14. Alphabetic Pin Assignments. (Sheet 2 of 3)

26 Preliminary Datasheet

1. Pertains to the 21150-AB and later revisions only. For the 21150-AA, this pin was vss.
2. nc–Do not connect these pins on the board.

Table 14. Alphabetic Pin Assignments. (Sheet 3 of 3)

4.0 PCI Bus Operation

the 21150, and transaction termination.

4.1 Types of Transactions

This section provides a summary of PCI transactions performed by the 21150. as a target, on the primary bus and on the secondary bus.

• The 21150 never initiates a PCI transaction with a reserved command code and, as a target, the 21150 ignores reserved command codes.
• The 21150 never initiates an interrupt acknowledge transaction and, as a target, the 21150 ignores interrupt acknowledge transactions. Interrupt acknowledge transactions are expected to reside entirely on the primary PCI bus closest to the host bridge.
• The 21150 does not respond to special cycle transactions. The 21150 cannot guarantee delivery of a special cycle transaction to downstream buses because of the broadcast nature of the special cycle command and the inability to control the transaction as a target. To generate

Table 15. 21150 PCI Transactions

21150 Initiates as Master 21150 Initiates as Target

28 Preliminary Datasheet

special cycle transactions on other PCI buses, either upstream or downstream, a Type 1 configuration command must be used.

• The 21150 does not generate Type 0 configuration transactions on the primary interface, nor does it respond to Type 0 configuration transactions on the secondary PCI interface. The PCI-to-PCI Bridge Architecture Specification does not support configuration from the secondary bus.

4.2 Address Phase

The standard PCI transaction consists of one or two address phases, followed by one or more data phases. An address phase always lasts one PCI clock cycle. The first address phase is designated by an asserting (falling) edge on the FRAME# signal. The number of address phases depends on whether the address is 32 bits or 64 bits.

4.2.1 Single Address Phase

A 32-bit address uses a single address phase. This address is driven on AD<31:0>, and the bus command is driven on C/BE#<3:0>. The 21150 supports the linear increment address mode only, which is indicated when the low 2 address bits are equal to 0. If either of the low 2 address bits is nonzero, the 21150 automatically disconnects the transaction after the first data transfer.

4.2.2 Dual Address Phase

Dual address transactions are PCI transactions that contain two address phases specifying a 64-bit address. The first address phase is denoted by the asserting edge of FRAME#. The second address phase always follows on the next clock cycle. For a 32-bit interface, the first address phase contains the dual address command code on the C/BE#<3:0> lines, and the low 32 address bits on the AD<31:0> lines. The second address phase consists of the specific memory transaction command code on the C/BE#<3:0> lines, and the high 32 address bits on the AD<31:0>lines. In this way, 64-bit addressing can be supported on 32-bit PCI buses. The PCI-to-PCI Bridge Architecture Specification supports the use of dual address transactions in the prefetchable memory range only. See Section 5.3 for a discussion of prefetchable address space. The 21150 supports dual address transactions in both the upstream and the downstream direction. The 21150 supports a programmable 64-bit address range in prefetchable memory for downstream forwarding of dual address transactions. Dual address transactions falling outside the prefetchable address range are forwarded upstream, but not downstream. Prefetching and posting are performed in a manner consistent with the guidelines given in this specification for each type of memory transaction in prefetchable memory space.

• Memory write
• Memory write and invalidate
• Memory read
• Memory read line
• Memory read multiple Use of other transaction codes may result in a master abort. Any memory transactions addressing the first 4GB space should use a single address phase; that is, the high 32 bits of a dual address transaction should never be 0.

4.3 Device Select (DEVSEL#) Generation

4.4 Data Phase

4.5 Write Transactions

the method of forwarding used for each type of write operation. Table 16. Write Transaction Forwarding

30 Preliminary Datasheet

4.5.1 Posted Write Transactions

Posted write forwarding is used for memory write and for memory write and invalidate transactions. When the 21150 determines that a memory write transaction is to be forwarded across the bridge, the 21150 asserts DEVSEL# with medium timing and TRDY# in the same cycle, provided that enough buffer space is available in the posted data queue for the address and at least 8 Dwords of data. This enables the 21150 to accept write data without obtaining access to the target bus. The 21150 can accept 1 Dword of write data every PCI clock cycle; that is, no target wait states are inserted. This write data is stored in internal posted write buffers and is subsequently delivered to the target. The 21150 continues to accept write data until one of the following events occurs:

• The initiator terminates the transaction by deasserting FRAME# and IRDY#.
• An internal write address boundary is reached, such as a cache line boundary or an aligned 4KB boundary, depending on the transaction type.
• The posted write data buffer fills up. When one of the last two events occurs, the 21150 returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. Once the posted write data moves to the head of the posted data queue, the 21150 asserts its request on the target bus. This can occur while the 21150 is still receiving data on the initiator bus. When the grant for the target bus is received and the target bus is detected in the idle condition, the 21150 asserts FRAME# and drives the stored write address out on the target bus. On the following cycle, the 21150 drives the first Dword of write data and continues to transfer write data until all write data corresponding to that transaction is delivered, or until a target termination is received. As long as write data exists in the queue, the 21150 can drive 1 Dword of write data each PCI clock cycle; that is, no master wait states are inserted. If write data is flowing through the 21150 and the initiator stalls, the 21150 may have to insert wait states on the target bus if the queue empties. Figure 6 shows a memory write transaction in flow-through mode, where data is being removed from buffers on the target interface while more data is being transferred into the buffers on the master interface.

• All posted write data has been delivered to the target.
• The target returns a target disconnect or target retry (the 21150 starts another transaction to deliver the rest of the write data).
• The target returns a target abort (the 21150 discards remaining write data).
• The master latency timer expires, and the 21150 no longer has the target bus grant (the 21150 starts another transaction to deliver remaining write data). Section 4.8.3.2 provides detailed information about how the 21150 responds to target termination during posted write transactions.

Figure 6. Flow-Through Posted Memory Write Transaction

7 Byte Enables

32 Preliminary Datasheet

4.5.2 Memory Write and Invalidate Transactions

Posted write forwarding is used for memory write and invalidate transactions. Memory write and invalidate transactions guarantee transfer of entire cache lines. If the write buffer fills before an entire cache line is transferred, the 21150 disconnects the transaction and converts it to a memory write transaction. The 21150 disconnects memory write and invalidate commands at aligned cache line boundaries. The cache line size value in the 21150 cache line size register gives the number of Dwords in a cache line. For the 21150 to generate memory write and invalidate transactions, this cache line size value must be written to a value that is a nonzero power of 2 and less than or equal to 16 (that is, 1, 2, 4, 8, or 16 Dwords). If the cache line size does not meet the memory write and invalidate conditions, that is, the value is 0, or is not a power of 2, or is greater than 16 Dwords, the 21150 treats the memory write and invalidate command as a memory write command. In this case, when the 21150 forwards the memory write and invalidate transaction to the target bus, it converts the command code to a memory write code and does not observe cache line boundaries. If the value in the cache line size register does meet the memory write and invalidate conditions, that is, the value is a nonzero power of 2 less than or equal to 16 Dwords, the 21150 returns a target disconnect to the initiator either on a cache line boundary or when the posted write buffer fills. For a cache line size of 16 Dwords, the 21150 disconnects a memory write and invalidate transaction on every cache line boundary. When the cache line size is 1, 2, 4, or 8 Dwords, the 21150 accepts another cache line if at least 8 Dwords of empty space remains in the posted write buffer. If less than 8 Dwords of empty space remains, the 21150 disconnects on that cache line boundary. When the memory write and invalidate transaction is disconnected before a cache line boundary is reached, typically because the posted write buffer fills, the transaction is converted to a memory write transaction.

4.5.3 Delayed Write Transactions

Delayed write forwarding is used for I/O write transactions and for Type 1 configuration write transactions. A delayed write transaction guarantees that the actual target response is returned back to the initiator without holding the initiating bus in wait states. A delayed write transaction is limited to a single Dword data transfer. When a write transaction is first detected on the initiator bus, and the 21150 forwards it as a delayed transaction, the 21150 claims the access by asserting DEVSEL# and returns a target retry to the initiator. During the address phase, the 21150 samples the bus command, address, and address parity one cycle later. After IRDY# is asserted, the 21150 also samples the first data Dword, byte enable bits, and data parity. This information is placed into the delayed transaction queue. The transaction is queued only if no other existing delayed transactions have the same address and command, and if the delayed transaction queue is not full. When the delayed write transaction moves to the head of the delayed transaction queue and all ordering constraints with posted data are satisfied (see Section 6.0), the 21150 initiates the transaction on the target bus. The 21150 transfers the write data to the target. If the 21150 receives a target retry in response to the write transaction on the target bus, it continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered.

If the 21150 is unable to deliver write data after 224 attempts, the 21150 ceases further write attempts and returns a target abort to the initiator. The delayed transaction is removed from the delayed transaction queue. The 21150 also asserts p_serr_l if the primary SERR# enable bit is set in the command register. See Section 7.4 for information on the assertion of p_serr_l. When the initiator repeats the same write transaction (same command, address, byte enable bits, and data), and the completed delayed transaction is at the head of the queue, the 21150 claims the access by asserting DEVSEL# and returns TRDY# to the initiator, to indicate that the write data was transferred. If the initiator requests multiple Dwords, the 21150 also asserts STOP# in conjunction with TRDY# to signal a target disconnect. Note that only those bytes of write data with valid byte enable bits are compared. If any of the byte enable bits are turned off (driven high), the corresponding byte of write data is not compared. If the initiator repeats the write transaction before the data has been transferred to the target, the 21150 returns a target retry to the initiator. The 21150 continues to return a target retry to the initiator until write data is delivered to the target, or until an error condition is encountered. When the write transaction is repeated, the 21150 does not make a new entry into the delayed transaction queue. Section 4.8.3.1 provides detailed information about how the 21150 responds to target termination during delayed write transactions. Figure 7 shows a delayed write transaction forwarded downstream across the 21150.

34 Preliminary Datasheet

21150 also conditionally asserts p_serr_l (see Section 7.4).

4.5.4 Write Transaction Address Boundaries

Figure 7. Downstream Delayed Write Transaction

4.5.5 Buffering Multiple Write Transactions

1. The memory write disconnect control bit is located in the chip control register at offset 40h in configuration space.

initiator terminates the write transaction, the 21150 returns a target disconnect to the initiator.

4.5.6 Fast Back-to-Back Write Transactions

not perform write combining or merging. back-to-back transactions on the target bus. Table 17. Write Transaction Disconnect Address Boundaries

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4.6 Read Transactions

Delayed read forwarding is used for all read transactions crossing the 21150. Delayed read transactions are treated as either prefetchable or nonprefetchable. Table 18 shows the read behavior, prefetchable or nonprefetchable, for each type of read operation. Figure 8. Multiple Memory Write Transactions Posted and Initiated as Fast Back-to-Back Table 18. Read Transaction Prefetching (Sheet 1 of 2)

See Section 5.3 for detailed information about prefetchable and nonprefetchable address spaces.

4.6.1 Prefetchable Read Transactions

turned on for all data phases. as for memory read transactions that fall into prefetchable memory space. any read address boundaries encountered. registers indicate if a memory address region is prefetchable.

4.6.2 Nonprefetchable Read Transactions

1–Dword from the target and disconnects the initiator after delivery of the first Dword of read data. memory read transactions that fall into nonprefetchable memory space. nonprefetchable (memory-mapped I/O) memory space to utilize nonprefetching behavior. Table 18. Read Transaction Prefetching (Sheet 2 of 2)

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4.6.3 Read Prefetch Address Boundaries

leftover prefetched data is discarded.

4.6.4 Delayed Read Requests

initiator when the initiator repeats the read transaction. Table 19. Read Prefetch Address Boundaries

4.6.5 Delayed Read Completion with Target

When the delayed read request reaches the head of the delayed transaction queue, and all previously queued posted write transactions have been delivered, the 21150 arbitrates for the target bus and initiates the read transaction, using the exact read address and read command captured from the initiator during the initial delayed read request. If the read transaction is a nonprefetchable read, the 21150 drives the captured byte enable bits during the next cycle. If the transaction is a prefetchable read transaction, it drives all byte enable bits to 0 for all data phases. If the 21150 receives a target retry in response to the read transaction on the target bus, it continues to repeat the read transaction until at least one data transfer is completed, or until an error condition is encountered. If the transaction is terminated via normal master termination or target disconnect after at least one data transfer has been completed, the 21150 does not initiate any further attempts to read more data. If the 21150 is unable to obtain read data from the target after 2 24 attempts, the 21150 ceases further read attempts and returns a target abort to the initiator. The delayed transaction is removed from the delayed transaction queue. The 21150 also asserts p_serr_l if the primary SERR# enable bit is set in the command register. See Section 7.4 for information on the assertion of p_serr_l. Once the 21150 receives DEVSEL# and TRDY# from the target, it transfers the data read to the opposite direction read data queue, pointing toward the opposite interface, before terminating the transaction. For example, read data in response to a downstream read transaction initiated on the primary bus is placed in the upstream read data queue. The 21150 can accept 1 Dword of read data each PCI clock cycle; that is, no master wait states are inserted. The number of Dwords transferred during a delayed read transaction depends on the conditions given in Table 19 (assuming no disconnect is received from the target).

4.6.6 Delayed Read Completion on Initiator Bus

When the transaction has been completed on the target bus, and the delayed read data is at the head of the read data queue, and all ordering constraints with posted write transactions have been satisfied, the 21150 transfers the data to the initiator when the initiator repeats the transaction. For memory read transactions, the 21150 aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction to the bus command in the delayed transaction queue.The 21150 returns a target disconnect along with the transfer of the last Dword of read data to the initiator. If the initiator terminates the transaction before all read data has been transferred, the remaining read data left in data buffers is discarded. Figure 9 shows a nonprefetchable delayed read transaction.

40 Preliminary Datasheet

Figure 10 shows a prefetchable delayed read transaction. Figure 9. Nonprefetchable Delayed Read Transaction

42 Preliminary Datasheet

the head of the delayed transaction queue, and the read data is at the head of the read data queue. and the read data from its queues. The 21150 also conditionally asserts p_serr_l (see Section 7.4). contained in the delayed transaction queue.

4.7 Configuration Transactions

in configuration space only. Figure 11. Flow-Through Prefetchable Read Transaction

systems, as well as for special cycle generation. the lowest 2 bits of the address set to 00b. identified by the configuration command and the lowest 2 address bits set to 01b. Figure 12 shows the address formats for Type 0 and Type 1 configuration transactions.

4.7.1 Type 0 Access to the 21150

• The bus command is a configuration read or configuration write transaction.
• Low 2 address bits p_ad<1:0> must be 00b.
• Signal p_idsel must be asserted. The function code is ignored because the 21150 is a single-function device.

Figure 12. Configuration Transaction Address Formats

44 Preliminary Datasheet

The 21150 limits all configuration accesses to a single Dword data transfer and returns a target disconnect with the first data transfer if additional data phases are requested. Because read transactions to 21150 configuration space do not have side effects, all bytes in the requested Dword are returned, regardless of the value of the byte enable bits. Type 0 configuration write and read transactions do not use 21150 data buffers; that is, these transactions are completed immediately, regardless of the state of the data buffers. The 21150 ignores all Type 0 transactions initiated on the secondary interface.

4.7.2 Type 1 to Type 0 Translation

Type 1 configuration transactions are used specifically for device configuration in a hierarchical PCI bus system. A PCI-to-PCI bridge is the only type of device that should respond to a Type 1 configuration command. Type 1 configuration commands are used when the configuration access is intended for a PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated. The 21150 performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. The 21150 must convert the configuration command to a Type 0 format so that the secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in the downstream direction; that is, the 21150 generates a Type 0 transaction only on the secondary bus, and never on the primary bus.

• The 21150 responds to a Type 1 configuration transaction and translates it into a Type 0 transaction on the secondary bus when the following conditions are met during the address phase:
• The low 2 address bits on p_ad<1:0> are 01b.
• The bus number in address field p_ad<23:16> is equal to the value in the secondary bus number register in 21150 configuration space.
• The bus command on p_cbe_l<3:0> is a configuration read or configuration write transaction. When the 21150 translates the Type 1 transaction to a Type 0 transaction on the secondary interface, it performs the following translations to the address:
• Sets the low 2 address bits on s_ad<1:0> to 00b.
• Decodes the device number and drives the bit pattern specified in Table 20 on s_ad<31:1> for the purpose of asserting the device’s IDSEL signal.
• Sets s_ad<15:11>to 0.
• Leaves unchanged the function number and register number fields. The 21150 asserts a unique address line based on the device number. These address lines may be used as secondary bus IDSEL signals. The mapping of the address lines depends on the device number in the Type 1 address bits p_ad<15:11>. Table 20 presents the mapping that the 21150 uses.

device, the transaction ends in a master abort.

4.7.3 Type 1 to Type 1 Forwarding

two or more levels of PCI-to-PCI bridges are used. from the secondary bus, the 21150 forwards the transaction unchanged to the secondary bus.

• The low 2 address bits are equal to 01b.

Table 20. Device Number to IDSEL s_ad Pin Mapping

46 Preliminary Datasheet

• The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register.
• The bus command is a configuration read or write transaction. The 21150 also supports Type 1 to Type 1 forwarding of configuration write transactions upstream to support upstream special cycle generation. A Type 1 configuration command is forwarded upstream when the following conditions are met:
• The low 2 address bits are equal to 01b.
• The bus number falls outside the range defined by the lower limit (inclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register.
• The device number in address bits AD<15:11> is equal to 11111b.
• The function number in address bits AD<10:8> is equal to 111b.
• The bus command is a configuration write transaction. The 21150 forwards Type 1 to Type 1 configuration write transactions as delayed transactions. Type 1 to Type 1 configuration write transactions are limited to a single data transfer.

4.7.4 Special Cycles

The Type 1 configuration mechanism is used to generate special cycle transactions in hierarchical PCI systems. Special cycle transactions are ignored by a PCI-to-PCI bridge acting as a target and are not forwarded across the bridge. Special cycle transactions can be generated from Type 1 configuration write transactions in either the upstream or the downstream direction. The 21150 initiates a special cycle on the target bus when a Type 1 configuration write transaction is detected on the initiating bus and the following conditions are met during the address phase:

• The low 2 address bits on AD<1:0> are equal to 01b.
• The device number in address bits AD<15:11> is equal to 11111b.
• The function number in address bits AD<10:8> is equal to 111b.
• The register number in address bits AD<7:2> is equal to 000000b.
• The bus number is equal to the value in the secondary bus number register in configuration space for downstream forwarding or equal to the value in the primary bus number register in configuration space for upstream forwarding.
• The bus command on C/BE# is a configuration write command. When the 21150 initiates the transaction on the target interface, the bus command is changed from configuration write to special cycle. The address and data are forwarded unchanged. Devices that use special cycles ignore the address and decode only the bus command. The data phase contains the special cycle message. The transaction is forwarded as a delayed transaction, but in this case the target response is not forwarded back (because special cycles result in a master abort). Once the transaction is completed on the target bus, through detection of the master abort condition, the 21150 responds with TRDY# to the next attempt of the configuration transaction from the initiator. If more than one data transfer is requested, the 21150 responds with a target disconnect operation during the first data phase.

4.8 Transaction Termination

This section describes how the 21150 returns transaction termination conditions back to the initiator. The initiator can terminate transactions with one of the following types of termination:

• Normal termination Normal termination occurs when the initiator deasserts FRAME# at the beginning of the last data phase, and deasserts IRDY# at the end of the last data phase in conjunction with either TRDY# or STOP# assertion from the target.
• Master abort A master abort occurs when no target response is detected. When the initiator does not detect a DEVSEL# from the target within five clock cycles after asserting FRAME#, the initiator terminates the transaction with a master abort. If FRAME# is still asserted, the initiator deasserts FRAME# on the next cycle, and then deasserts IRDY# on the following cycle. IRDY# must be asserted in the same cycle in which FRAME# deasserts. If FRAME# is already deasserted, IRDY# can be deasserted on the next clock cycle following detection of the master abort condition. The target can terminate transactions with one of the following types of termination:
• Normal termination—TRDY# and DEVSEL# asserted in conjunction with FRAME# deasserted and IRDY# asserted.
• Target retry—STOP# and DEVSEL# asserted without TRDY# during the first data phase. No data transfers occur during the transaction. This transaction must be repeated.
• Target disconnect with data transfer—STOP# and DEVSEL# asserted with TRDY#. Signals that this is the last data transfer of the transaction.
• Target disconnect without data transfer—STOP# and DEVSEL# asserted without TRDY# after previous data transfers have been made. Indicates that no more data transfers will be made during this transaction.
• Target abort—STOP# asserted without DEVSEL# and without TRDY#. Indicates that the target will never be able to complete this transaction. DEVSEL# must be asserted for at least one cycle during the transaction before the target abort is signaled.

4.8.1 Master Termination Initiated by the 21150

The 21150, as an initiator, uses normal termination if DEVSEL# is returned by the target within five clock cycles of the 21150’s assertion of FRAME# on the target bus. As an initiator, the 21150 terminates a transaction when the following conditions are met:

• During a delayed write transaction, a single Dword is delivered.
• During a nonprefetchable read transaction, a single Dword is transferred from the target.
• During a prefetchable read transaction, a prefetch boundary is reached.
• For a posted write transaction, all write data for the transaction is transferred from 21150 data buffers to the target.
• For a burst transfer, with the exception of memory write and invalidate transactions, the master latency timer expires and the 21150’s bus grant is deasserted.
• The target terminates the transaction with a retry, disconnect, or target abort.

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If the 21150 is delivering posted write data when it terminates the transaction because the master latency timer expires, it initiates another transaction to deliver the remaining write data. The address of the transaction is updated to reflect the address of the current Dword to be delivered. If the 21150 is prefetching read data when it terminates the transaction because the master latency timer expires, it does not repeat the transaction to obtain more data.

4.8.2 Master Abort Received by the 21150

If the 21150 initiates a transaction on the target bus and does not detect DEVSEL# returned by the target within five clock cycles of the 21150’s assertion of FRAME#, the 21150 terminates the transaction with a master abort. The 21150 sets the received master abort bit in the status register corresponding to the target bus. For delayed read and write transactions, when the master abort mode bit in the bridge control register is 0, the 21150returns TRDY# on the initiator bus and, for read transactions, returns FFFF FFFFh as data. When the master abort mode bit is 1, the 21150 returns target abort on the initiator bus. The 21150 also sets the signaled target abort bit in the register corresponding to the initiator bus. Figure 13 shows a delayed write transaction that is terminated with a master abort.

set, and the Type 1 configuration transaction is disconnected after the first data phase. Figure 13. Delayed Write Transaction Terminated with Master Abort

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4.8.3 Target Termination Received by the 21150

• Normal termination (upon deassertion of FRAME#)
• Target retry
• Target disconnect
• Target abort The 21150 handles these terminations in different ways, depending on the type of transaction being performed.

4.8.3.1 Delayed Write Target Termination Response

target termination that occurs during a delayed write transaction.

• The 21150 completes at least one data transfer.
• The 21150 receives a master abort.
• The 21150 receives a target abort.
• The 21150 makes 224 write attempts resulting in a response of target retry. After the 21150 makes 224 attempts of the same delayed write transaction on the target bus, the 21150 asserts p_serr_l if the primary SERR# enable bit is set in the command register and the implementation-specific p_serr_l disable bit for this condition is not set in the p_serr_l event disable register. The 21150 stops initiating transactions in response to that delayed write transaction. The delayed write request is discarded. Upon a subsequent write transaction attempt by the initiator, the 21150 returns a target abort. See Section 7.4 for a description of system error conditions.

Table 21. 21150 Response to Delayed Write Target Termination only if multiple data phases requested. only if multiple data phases requested. Return target abort to initiator.

4.8.3.2 Posted Write Target Termination Response

during a posted write transaction. will be transferred in the subsequent write transaction attempt.

4.8.3.3 Delayed Read Target Termination Response

back to the initiator. Other target responses depend on how much data the initiator requests. Table 22. 21150 Response to Posted Write Target Termination Normal No additional action. Target retry Repeat write transaction to target. Table 23. 21150 Response to Delayed Read Target Termination (Sheet 1 of 2) Target retry Reinitiate read transaction to target. return target disconnect to initiator.

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Figure 14 shows a delayed read transaction that is terminated with a target abort.

• The 21150 completes at least one data transfer.
• The 21150 receives a master abort.
• The 21150 receives a target abort.
• The 21150 makes 224 read attempts resulting in a response of target retry. Target abort Return target abort to initiator. Set received target abort bit in the target interface status register. Set signaled target abort bit in the initiator interface status register.

Table 23. 21150 Response to Delayed Read Target Termination (Sheet 2 of 2) Figure 14. Delayed Read Transaction Terminated with Target Abort

After the 21150 makes 224 attempts of the same delayed read transaction on the target bus, the 21150 asserts p_serr_l if the primary SERR# enable bit is set in the command register and the implementation-specific p_serr_l disable bit for this condition is not set in the p_serr_l event disable register. The 21150 stops initiating transactions in response to that delayed read transaction. The delayed read request is discarded. Upon a subsequent read transaction attempt by the initiator, the 21150 returns a target abort. See Section 7.4 for a description of system error conditions.

4.8.4 Target Termination Initiated by the 21150

The 21150 can return a target retry, target disconnect, or target abort to an initiator for reasons other than detection of that condition at the target interface.

4.8.4.1 Target Retry

The 21150 returns a target retry to the initiator when it cannot accept write data or return read data as a result of internal conditions. The 21150 returns a target retry to an initiator when any of the following conditions is met:

• For delayed write transactions: — The transaction is being entered into the delayed transaction queue. — The transaction has already been entered into the delayed transaction queue, but target response has not yet been received. — Target response has been received but has not progressed to the head of the return queue. — The delayed transaction queue is full, and the transaction cannot be queued. — A transaction with the same address and command has been queued. — A locked sequence is being propagated across the 21150, and the write transaction is not a locked transaction.
• For delayed read transactions: — The transaction is being entered into the delayed transaction queue. — The read request has already been queued, but read data is not yet available. — Data has been read from the target, but it is not yet at the head of the read data queue, or a posted write transaction precedes it. — The delayed transaction queue is full, and the transaction cannot be queued. — A delayed read request with the same address and bus command has already been queued. — A locked sequence is being propagated across the 21150, and the read transaction is not a locked transaction. — The 21150 is currently discarding previously prefetched read data.
• For posted write transactions: — The posted write data buffer does not have enough space for address and at least 8 Dwords of write data. — A locked sequence is being propagated across the 21150, and the write transaction is not a locked transaction.

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When a target retry is returned to the initiator of a delayed transaction, the initiator must repeat the transaction with the same address and bus command as well as the data if this is a write transaction, within the time frame specified by the master timeout value; otherwise, the transaction is discarded from the 21150 buffers.

4.8.4.2 Target Disconnect

The 21150 returns a target disconnect to an initiator when one of the following conditions is met:

• The 21150 hits an internal address boundary
• The 21150 cannot accept any more write data
• The 21150 has no more read data to deliver See Section 4.5.4 for a description of write address boundaries, and Section 4.6.3 for a description of read address boundaries.

4.8.4.3 Target Abort

The 21150 returns a target abort to an initiator when one of the following conditions is met:

• The 21150 is returning a target abort from the intended target.
• The 21150 is unable to obtain delayed read data from the target or to deliver delayed write data to the target after 2 24attempts. When the 21150 returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface.

5.0 Address Decoding

The 21150 uses three address ranges that control I/O and memory transaction forwarding. These address ranges are defined by base and limit address registers in the 21150 configuration space. This chapter describes these address ranges, as well as ISA-mode and VGA-addressing support.

5.1 Address Ranges

The 21150 uses the following address ranges that determine which I/O and memory transactions are forwarded from the primary PCI bus to the secondary PCI bus, and from the secondary bus to the primary bus:

• One 32-bit I/O address range
• One 32-bit memory-mapped I/O (nonprefetchable memory)
• One 64-bit prefetchable memory address range Transactions falling within these ranges are forwarded downstream from the primary PCI bus to the secondary PCI bus. Transactions falling outside these ranges are forwarded upstream from the secondary PCI bus to the primary PCI bus. The 21150 uses a flat address space; that is, it does not perform any address translations. The address space has no “gaps”—addresses that are not marked for downstream forwarding are always forwarded upstream.

5.2 I/O Address Decoding

The 21150 uses the following mechanisms that are defined in the 21150 configuration space to specify the I/O address space for downstream and upstream forwarding:

• I/O base and limit address registers
• The ISA enable bit
• The VGA mode bit
• The VGA snoop bit This section provides information on the I/O address registers and ISA mode.Section 5.4 provides information on the VGA modes. To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the command register in 21150 configuration space. If the I/O enable bit is not set, all I/O transactions initiated on the primary bus are ignored. To enable upstream forwarding of I/O transactions, the master enable bit must be set in the command register. If the master enable bit is not set, the 21150 ignores all I/O and memory transactions initiated on the secondary bus. Setting the master enable bit also allows upstream forwarding of memory transactions.

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secondary bus, the 21150 response to the secondary bus I/O transactions is not predictable. the primary and secondary PCI buses are idle.

5.2.1 I/O Base and Limit Address Registers

and no I/O transactions are forwarded downstream. Figure 15 illustrates transaction forwarding within and outside the I/O address range. maximum I/O range is 4GB in size. of the base address are assumed to be 0, which naturally aligns the base address to a 4KB boundary. Figure 15. I/O Transaction Forwarding Using Base and Limit Addresses

The 16 bits contained in the I/O base upper 16 bits register at configuration offset 30h define AD<31:16> of the I/O base address. All 16 bits are read/write. After primary bus reset or chip reset, the value of the I/O base address is initialized to 0000 0000h. The I/O limit register consists of an 8-bit field at configuration offset 1Dh and a 16-bit field at offset 32h. The top 4 bits of the 8-bit field define bits <15:12> of the I/O limit address. The bottom 4 bits read only as 1h to indicate that 32-bit I/O addressing is supported. Bits <11:0> of the limit address are assumed to be FFFh, which naturally aligns the limit address to the top of a 4KB I/O address block. The 16 bits contained in the I/O limit upper 16 bits register at configuration offset 32h define AD<31:16> of the I/O limit address. All 16 bits are read/write. After primary bus reset or chip reset, the value of the I/O limit address is reset to 0000 0FFFh. Note: The initial states of the I/O base and I/O limit address registers define an I/O range of 0000 0000h to 0000 0FFFh, which is the bottom 4KB of I/O space. Write these registers with their appropriate values before setting either the I/O enable bit or the master enable bit in the command register in configuration space.

5.2.2 ISA Mode

The 21150 supports ISA mode by providing an ISA enable bit in the bridge control register in configuration space. ISA mode modifies the response of the 21150 inside the I/O address range in order to support mapping of I/O space in the presence of an ISA bus in the system. This bit only affects the response of the 21150 when the transaction falls inside the address range defined by the I/O base and limit address registers, and only when this address also falls inside the first 64KB of I/O space (address bits <31:16> are 0000h). When the ISA enable bit is set, the 21150 does not forward downstream any I/O transactions addressing the top 768 bytes of each aligned 1KB block. Only those transactions addressing the bottom 256 bytes of an aligned 1KB block inside the base and limit I/O address range are forwarded downstream. Transactions above the 64KB I/O address boundary are forwarded as defined by the address range defined by the I/O base and limit registers. Accordingly, if the ISA enable bit is set, the 21150 forwards upstream those I/O transactions addressing the top 768 bytes of each aligned 1KB block within the first 64KB of I/O space. The master enable bit in the command configuration register must also be set to enable upstream forwarding. All other I/O transactions initiated on the secondary bus are forwarded upstream only if they fall outside the I/O address range. When the ISA enable bit is set, devices downstream of the 21150 can have I/O space mapped into the first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere in I/O space above the 64KB boundary. Figure 16 illustrates I/O forwarding when the ISA enable bit is set.

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5.3 Memory Address Decoding

• Memory-mapped I/O base and limit address registers
• Prefetchable memory base and limit address registers
• VGA mode This section describes the first two mechanisms. Section 5.4.1 describes VGA mode. To enable downstream forwarding of memory transactions, the memory enable bit must be set in the command register in 21150 configuration space. To enable upstream forwarding of memory transactions, the master enable bit must be set in the command register. Setting the master enable bit also allows upstream forwarding of I/O transactions. Caution: If any 21150 configuration state affecting memory transaction forwarding is changed by a configuration write operation on the primary bus at the same time that memory transactions are ongoing on the secondary bus, 21150 response to the secondary bus memory transactions is not predictable. Configure the memory-mapped I/O base and limit address registers, prefetchable memory base and limit address registers, and VGA mode bit before setting the memory enable and

Figure 16. I/O Transaction Forwarding in ISA Mode LJ-04637.AI5

master enable bits, and change them subsequently only when the primary and secondary PCI buses are idle.

5.3.1 Memory-Mapped I/O Base and Limit Address Registers

Memory-mapped I/O is also referred to as nonprefetchable memory. Memory addresses that cannot automatically be prefetched but that can conditionally prefetch based on command type should be mapped into this space. Read transactions to nonprefetchable space may exhibit side effects; this space may have non-memory-like behavior. The 21150 prefetches in this space only if the memory read line or memory read multiple commands are used; transactions using the memory read command are limited to a single data transfer. The memory-mapped I/O base address and memory-mapped I/O limit address registers define an address range that the 21150 uses to determine when to forward memory commands. The 21150 forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the memory-mapped I/O address range. The 21150 ignores memory transactions initiated on the secondary interface that fall into this address range. Any transactions that fall outside this address range are ignored on the primary interface and are forwarded upstream from the secondary interface (provided that they do not fall into the prefetchable memory range or are not forwarded downstream by the VGA mechanism). The memory-mapped I/O range supports 32-bit addressing only. The PCI-to-PCI Bridge Architecture Specification does not provide for 64-bit addressing in the memory-mapped I/O space. The memory-mapped I/O address range has a granularity and alignment of 1MB. The maximum memory-mapped I/O address range is 4GB. The memory-mapped I/O address range is defined by a 16-bit memory-mapped I/O base address register at configuration offset 20h and by a 16-bit memory-mapped I/O limit address register at offset 22h. The top 12 bits of each of these registers correspond to bits <31:20> of the memory address. The low 4 bits are hardwired to 0. The low 20 bits of the memory-mapped I/O base address are assumed to be 0 0000h, which results in a natural alignment to a 1MB boundary. The low 20 bits of the memory-mapped I/O limit address are assumed to be F FFFFh, which results in an alignment to the top of a 1MB block. Note: The initial state of the memory-mapped I/O base address register is 0000 0000h.The initial state of the memory-mapped I/O limit address register is 000F FFFFh. Note that the initial states of these registers define a memory-mapped I/O range at the bottom 1MB block of memory. Write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. To turn off the memory-mapped I/O address range, write the memory-mapped I/O base address register with a value greater than that of the memory-mapped I/O limit address register. Figure 17 shows how transactions are forwarded using both the memory-mapped I/O range and the prefetchable memory range.

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5.3.2 Prefetchable Memory Base and Limit Address Registers

commands in this address space. into the memory-mapped I/O range or are not forwarded by the VGA mechanism). upper 32 bits register must be 0 in order to pass any single address cycle transactions downstream. Section 5.3.3 further describes 64-bit addressing support. Figure 17. Memory Transaction Forwarding Using Base and Limit Registers

The prefetchable memory address range has a granularity and alignment of 1MB. The maximum memory address range is 4GB when 32-bit addressing is used, and 264 bytes when 64-bit addressing is used. The prefetchable memory address range is defined by a 16-bit prefetchable memory base address register at configuration offset 24h and by a 16-bit prefetchable memory limit address register at offset 28h. The top 12 bits of each of these registers correspond to bits <31:20> of the memory address. The low 4 bits are hardwired to 1h, indicating 64-bit address support. The low 20 bits of the prefetchable memory base address are assumed to be 0 0000h, which results in a natural alignment to a 1MB boundary. The low 20 bits of the prefetchable memory limit address are assumed to be F FFFFh, which results in an alignment to the top of a 1MB block. Note: The initial state of the prefetchable memory base address register is 0000 0000h. The initial state of the prefetchable memory limit address register is 000F FFFFh. Note that the initial states of these registers define a prefetchable memory range at the bottom 1MB block of memory. Write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. To turn off the prefetchable memory address range, write the prefetchable memory base address register with a value greater than that of the prefetchable memory limit address register. The entire base value must be greater than the entire limit value, meaning that the upper 32 bits must be considered. Therefore, to disable the address range, the upper 32 bits registers can both be set to the same value, while the lower base register is set greater than the lower limit register; otherwise, the upper 32-bit base must be greater than the upper 32-bit limit.

5.3.3 Prefetchable Memory 64-Bit Addressing Registers

The 21150 supports 64-bit memory address decoding for forwarding of dual address memory transactions. The dual address cycle is used to support 64-bit addressing. The first address phase of a dual address transaction contains the low 32 address bits, and the second address phase contains the high 32 address bits. During a dual address cycle transaction, the upper 32 bits must never be 0—use the single address cycle commands for transactions addressing the first 4GB of memory space. The 21150 implements the prefetchable memory base address upper 32 bits register and the prefetchable memory limit address upper 32 bits register to define a prefetchable memory address range greater than 4GB. The prefetchable address space can then be defined in three different ways:

• Residing entirely in the first 4GB of memory
• Residing entirely above the first 4GB of memory
• Crossing the first 4GB memory boundary If the prefetchable memory space on the secondary interface resides entirely in the first 4GB of memory, both upper 32 bits registers must be set to 0. The 21150 ignores all dual address cycle transactions initiated on the primary interface and forwards all dual address transactions initiated on the secondary interface upstream. If the secondary interface prefetchable memory space resides entirely above the first 4GB of memory, both the prefetchable memory base address upper 32 bits register and the prefetchable memory limit address upper 32 bits register must be initialized to nonzero values. The 21150 ignores all single address memory transactions initiated on the primary interface and forwards all single address memory transactions initiated on the secondary interface upstream (unless they fall

62 Preliminary Datasheet

within the memory-mapped I/O or VGA memory range). A dual address memory transaction is forwarded downstream from the primary interface if it falls within the address range defined by the prefetchable memory base address, prefetchable memory base address upper 32 bits, prefetchable memory limit address, and prefetchable memory limit address upper 32 bits registers. If the dual address transaction initiated on the secondary interface falls outside this address range, it is forwarded upstream to the primary interface. The 21150 does not respond to a dual address transaction initiated on the primary interface that falls outside this address range, or to a dual address transaction initiated on the secondary interface that falls within the address range. If the secondary interface prefetchable memory space straddles the first 4GB address boundary, the prefetchable memory base address upper 32 bits register is set to 0, while the prefetchable memory limit address upper 32 bits register is initialized to a nonzero value. Single address cycle memory transactions are compared to the prefetchable memory base address register only. A transaction initiated on the primary interface is forwarded downstream if the address is greater than or equal to the base address. A transaction initiated on the secondary interface is forwarded upstream if the address is less than the base address. Dual address transactions are compared to the prefetchable memory limit address and the prefetchable memory limit address upper 32 bits registers. If the address of the dual address transaction is less than or equal to the limit, the transaction is forwarded downstream from the primary interface and is ignored on the secondary interface. If the address of the dual address transaction is greater than this limit, the transaction is ignored on the primary interface and is forwarded upstream from the secondary interface. The prefetchable memory base address upper 32 bits register is located at configuration Dword offset 28h, and the prefetchable memory limit address upper 32 bits register is located at configuration Dword offset 2Ch. Both registers are reset to 0. See Figure 17 for an illustration of how transactions are forwarded using both the memory-mapped I/O range and the prefetchable memory range.

5.4 VGA Support

The 21150 provides two modes for VGA support:

• VGA mode, supporting VGA-compatible addressing
• VGA snoop mode, supporting VGA palette forwarding

5.4.1 VGA Mode

When a VGA-compatible device exists downstream from the 21150, set the VGA mode bit in the bridge control register in configuration space to enable VGA mode. When the 21150 is operating in VGA mode, it forwards downstream those transactions addressing the VGA frame buffer memory and VGA I/O registers, regardless of the values of the 21150 base and limit address registers. The 21150 ignores transactions initiated on the secondary interface addressing these locations. The VGA frame buffer consists of the following memory address range: 000A 0000h—000B FFFFh Read transactions to frame buffer memory are treated as nonprefetchable. The 21150 requests only a single data transfer from the target, and read byte enable bits are forwarded to the target bus.

The VGA I/O addresses consist of the following I/O addresses:

• 3B0h–3BBh
• 3C0h–3DFh These I/O addresses are aliased every 1KB throughout the first 64KB of I/O space. This means that address bits <15:10> are not decoded and can be any value, while address bits <31:16> must be all 0s. VGA BIOS addresses starting at C0000h are not decoded in VGA mode.

5.4.2 VGA Snoop Mode

The 21150 provides VGA snoop mode, allowing for VGA palette write transactions to be forwarded downstream. This mode is used when a graphics device downstream from the 21150 needs to snoop or respond to VGA palette write transactions. To enable the mode, set the VGA snoop bit in the command register in configuration space. Note that the 21150 claims VGA palette write transactions by asserting DEVSEL# in VGA snoop mode. When the VGA snoop bit is set, the 21150 forwards downstream transactions with the following I/O addresses:

• 3C6h
• 3C8h
• 3C9h Note that these addresses are also forwarded as part of the VGA compatibility mode previously described. Again, address bits <15:10> are not decoded, while address bits <31:16> must be equal to 0, which means that these addresses are aliased every 1KB throughout the first 64KB of I/O space. Note: If both the VGA mode bit and the VGA snoop bit are set, the 21150 behaves in the same way as if only the VGA mode bit were set.

6.0 Transaction Ordering

To maintain data coherency and consistency, the 21150 complies with the ordering rules set forth in the PCI Local Bus Specification, Revision 2.1, for transactions crossing the bridge. This chapter describes the ordering rules that control transaction forwarding across the 21150. For a more detailed discussion of transaction ordering, see Appendix E of the PCI Local Bus Specification, Revision 2.1.

6.1 Transactions Governed by Ordering Rules

Ordering relationships are established for the following classes of transactions crossing the 21150:

• Posted write transactions, comprised of memory write and memory write and invalidate transactions Posted write transactions complete at the source before they complete at the destination; that is, data is written into intermediate data buffers before it reaches the target.
• Delayed write request transactions, comprised of I/O write and configuration write transactions Delayed write requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. A delayed write transaction must complete on the target bus before it completes on the initiator bus.
• Delayed write completion transactions, also comprised of I/O write and configuration write transactions Delayed write completion transactions have been completed on the target bus, and the target response is queued in the 21150 buffers. A delayed write completion transaction proceeds in the direction opposite that of the original delayed write request; that is, a delayed write completion transaction proceeds from the target bus to the initiator bus.
• Delayed read request transactions, comprised of all memory read, I/O read, and configuration read transactions Delayed read requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue.
• Delayed read completion transactions, comprised of all memory read, I/O read, and configuration read transactions Delayed read completion transactions have been completed on the target bus, and the read data has been queued in the 21150 read data buffers. A delayed read completion transaction proceeds in the direction opposite that of the original delayed read request; that is, a delayed read completion transaction proceeds from the target bus to the initiator bus. The 21150 does not combine or merge write transactions:
• The 21150 does not combine separate write transactions into a single write transaction—this optimization is best implemented in the originating master.
• The 21150 does not merge bytes on separate masked write transactions to the same Dword address—this optimization is also best implemented in the originating master.
• The 21150 does not collapse sequential write transactions to the same address into asingle write transaction—the PCI Local Bus Specification does not permit this combining of transactions.

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6.2 General Ordering Guidelines

transactions cross the 21150.

• The ordering relationship of a transaction with respect to other transactions is determined when the transaction completes, that is, when a transaction ends with a termination other than target retry.
• Requests terminated with target retry can be accepted and completed in any order with respect to other transactions that have been terminated with target retry. If the order of completion of delayed requests is important, the initiator should not start a second delayed transaction until the first one has been completed. If more than one delayed transaction is initiated, the initiator should repeat all the delayed transaction requests, using some fairness algorithm. Repeating a delayed transaction cannot be contingent on completion of another delayed transaction; otherwise, a deadlock can occur.
• Write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other direction. The 21150 can accept posted write transactions on both interfaces at the same time, as well as initiate posted write transactions on both interfaces at the same time.
• The acceptance of a posted memory write transaction as a target can never be contingent on the completion of a nonlocked, nonposted transaction as a master. This is true of the 21150 and must also be true of other bus agents; otherwise, a deadlock can occur.
• The 21150 accepts posted write transactions, regardless of the state of completion of any delayed transactions being forwarded across the 21150.

6.3 Ordering Rules

implementation can choose whether or not the transactions pass each other. The entries without superscripts reflect the 21150’s implementation choices. Table 24. Summary of Transaction Ordering (Sheet 1 of 2)

1. Posted write transactions must complete on the target bus in the order in which they were

received on the initiator bus. a device checking the flag could subsequently consume stale data.

1. A delayed read request traveling in the same direction as a previously queued posted write

complete on the target bus before the delayed read request can be attempted on the target bus. were to pass the write transaction, it would return stale data.

1. A delayed read completion must “pull” ahead of previously queued posted write data traveling

data is returned to the initiator. therefore should not complete until the write transaction is complete.

1. Delayed write requests cannot pass previously queued posted write data.

subsequently consume stale data.

1. Posted write transactions must be given opportunities to pass delayed read and write requests

used to arbitrate between the posted write queue and the delayed transaction queue. Table 24. Summary of Transaction Ordering (Sheet 2 of 2)

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6.4 Data Synchronization

Data synchronization refers to the relationship between interrupt signaling and data delivery. The PCI Local Bus Specification, Revision 2.1, provides the following alternative methods for synchronizing data and interrupts:

• The device signaling the interrupt performs a read of the data just written (software).
• The device driver performs a read operation to any register in the interrupting device before accessing data written by the device (software).
• System hardware guarantees that write buffers are flushed before interrupts are forwarded. The 21150 does not have a hardware mechanism to guarantee data synchronization for posted write transactions. Therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written (or some other location along the same path), or from the device driver to one of the device registers.

7.0 Error Handling

The 21150 checks, forwards, and generates parity on both the primary and secondary interfaces. To maintain transparency, the 21150 always tries to forward the existing parity condition on one bus to the other bus, along with address and data. The 21150 always attempts to be transparent when reporting errors, but this is not always possible, given the presence of posted data and delayed transactions. To support error reporting on the PCI bus, the 21150 implements the following:

• PERR# and SERR# signals on both the primary and secondary interfaces
• Primary status and secondary status registers
• The device-specific p_serr_l event disable register
• The device-specific p_serr_l status register This chapter provides detailed information about how the 21150 handles errors. It also describes error status reporting and error operation disabling.

7.1 Address Parity Errors

The 21150 checks address parity for all transactions on both buses, for all address and all bus commands. When the 21150 detects an address parity error on the primary interface, the following events occur:

• If the parity error response bit is set in the command register, the 21150 does not claim the transaction with p_devsel_l; this may allow the transaction to terminate in a master abort. If the parity error response bit is not set, the 21150 proceeds normally and accepts the transaction if it is directed to or across the 21150.
• The 21150 sets the detected parity error bit in the status register.
• The 21150 asserts p_serr_l and sets the signaled system error bit in the status register, if both of the following conditions are met: — The SERR# enable bit is set in the command register. — The parity error response bit is set in the command register. When the 21150 detects an address parity error on the secondary interface, the following events occur:
• If the parity error response bit is set in the bridge control register, the 21150 does not claim the transaction with s_devsel_l; this may allow the transaction to terminate in a master abort. If the parity error response bit is not set, the 21150 proceeds normally and accepts the transaction if it is directed to or across the 21150.
• The 21150 sets the detected parity error bit in the secondary status register.

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• The 21150 asserts p_serr_l and sets the signaled system error bit in the status register, if both of the following conditions are met: — The SERR# enable bit is set in the command register. — The parity error response bit is set in the bridge control register.

7.2 Data Parity Errors

When forwarding transactions, the 21150 attempts to pass the data parity condition from one interface to the other unchanged, whenever possible, to allow the master and target devices to handle the error condition. The following sections describe, for each type of transaction, the sequence of events that occurs when a parity error is detected and the way in which the parity condition is forwarded across the 21150.

7.2.1 Configuration Write Transactions to 21150 Configuration Space

When the 21150 detects a data parity error during a Type 0 configuration write transaction to 21150 configuration space, the following events occur:

• If the parity error response bit is set in the command register, the 21150 asserts p_trdy_l and writes the data to the configuration register. The 21150 also asserts p_perr_l. If the parity error response bit is not set, the 21150 does not assert p_perr_l.
• The 21150 sets the detected parity error bit in the status register, regardless of the state of the parity error response bit.

7.2.2 Read Transactions

When the 21150 detects a parity error during a read transaction, the target drives data and data parity, and the initiator checks parity and conditionally asserts PERR#. For downstream transactions, when the 21150 detects a read data parity error on the secondary bus, the following events occur:

• The 21150 asserts s_perr_l two cycles following the data transfer, if the secondary interface parity error response bit is set in the bridge control register.
• The 21150 sets the detected parity error bit in the secondary status register.
• The 21150 sets the data parity detected bit in the secondary status register, if the secondary interface parity error response bit is set in the bridge control register.
• The 21150 forwards the bad parity with the data back to the initiator on the primary bus. If the data with the bad parity is prefetched and is not read by the initiator on the primary bus, the data is discarded and the data with bad parity is not returned to the initiator.
• The 21150 completes the transaction normally. For upstream transactions, when the 21150 detects a read data parity error on the primary bus, the following events occur:

• The 21150 asserts p_perr_l two cycles following the data transfer, if the primary interface parity error response bit is set in the command register
• The 21150 sets the detected parity error bit in the primary status register.
• The 21150 sets the data parity detected bit in the primary status register, if the primary interface parity error response bit is set in the command register.
• The 21150 forwards the bad parity with the data back to the initiator on the secondary bus. If the data with the bad parity is prefetched and is not read by the initiator on the secondary bus, the data is discarded and the data with bad parity is not returned to the initiator.
• The 21150 completes the transaction normally. The 21150 returns to the initiator the data and parity that was received from the target. When the initiator detects a parity error on this read data and is enabled to report it, the initiator asserts PERR# two cycles after the data transfer occurs. It is assumed that the initiator takes responsibility for handling a parity error condition; therefore, when the 21150 detects PERR# asserted while returning read data to the initiator, the 21150 does not take any further action and completes the transaction normally.

7.2.3 Delayed Write Transactions

When the 21150 detects a data parity error during a delayed write transaction, the initiator drives data and data parity, and the target checks parity and conditionally asserts PERR#. For delayed write transactions, a parity error can occur at the following times:

• During the original delayed write request transaction
• When the initiator repeats the delayed write request transaction
• When the 21150 completes the delayed write transaction to the target When a delayed write transaction is normally queued, the address, command, address parity, data, byte enable bits, and data parity are all captured and a target retry is returned to the initiator. When the 21150 detects a parity error on the write data for the initial delayed write request transaction, the following events occur:
• If the parity error response bit corresponding to the initiator bus is set, the 21150 asserts TRDY# to the initiator and the transaction is not queued. If multiple data phases are requested, STOP# is also asserted to cause a target disconnect. Two cycles after the data transfer, the 21150 also asserts PERR#. If the parity error response bit is not set, the 21150 returns a target retry and queues the transaction as usual. Signal PERR# is not asserted. In this case, the initiator repeats the transaction.
• The 21150 sets the detected parity error bit in the status register corresponding to the initiator bus, regardless of the state of the parity error response bit. Note: If parity checking is turned off and data parity errors have occurred for queued or subsequent delayed write transactions on the initiator bus, it is possible that the initiator’s reattempts of the write transaction may not match the original queued delayed write information contained in the delayed transaction queue. In this case, a master timeout condition may occur, possibly resulting in a system error (p_serr_l asserted). For downstream transactions, when the 21150 is delivering data to the target on the secondary bus and s_perr_l is asserted by the target, the following events occur:

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• The 21150 sets the secondary interface data parity detected bit in the secondary status register, if the secondary parity error response bit is set in the bridge control register.
• The 21150 captures the parity error condition to forward it back to the initiator on the primary bus. Similarly, for upstream transactions, when the 21150 is delivering data to the target on the primary bus and p_perr_l is asserted by the target, the following events occur:
• The 21150 sets the primary interface data parity detected bit in the status register, if the primary parity error response bit is set in the command register.
• The 21150 captures the parity error condition to forward it back to the initiator on the secondary bus. A delayed write transaction is completed on the initiator bus when the initiator repeats the write transaction with the same address, command, data, and byte enable bits as the delayed write command that is at the head of the posted data queue. Note that the parity bit is not compared when determining whether the transaction matches those in the delayed transaction queues. Two cases must be considered:
• When parity error is detected on the initiator bus on a subsequent reattempt of the transaction and was not detected on the target bus.
• When parity error is forwarded back from the target bus. For downstream delayed write transactions, when the parity error is detected on the initiator bus and the 21150 has write status to return, the following events occur:
• The 21150 first asserts p_trdy_l and then asserts p_perr_l two cycles later, if the primary interface parity error response bit is set in the command register.
• The 21150 sets the primary interface parity error detected bit in the status register.
• Because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue. Similarly, for upstream delayed write transactions, when the parity error is detected on the initiator bus and the 21150 has write status to return, the following events occur:
• The 21150 first asserts s_trdy_l and then asserts s_perr_l two cycles later, if the secondary interface parity error response bit is set in the bridge control register.
• The 21150 sets the secondary interface parity error detected bit in the secondary status register.
• Because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue. For downstream transactions, in the case where the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur:
• The 21150 asserts p_perr_l two cycles after the data transfer, if both of the following are true: — The primary interface parity error response bit is set in the command register. — The secondary interface parity error response bit is set in the bridge control register.
• The 21150 completes the transaction normally.

For upstream transactions, in the case where the parity error is being passed back from the target bus and the initiator bus, the following events occur:

• The 21150 asserts s_perr_l two cycles after the data transfer, if both of the following are true: — The primary interface parity error response bit is set in the command register. — The secondary interface parity error response bit is set in the bridge control register.
• The 21150 completes the transaction normally.

7.2.4 Posted Write Transactions

During downstream posted write transactions, when the 21150, responding as a target, detects a data parity error on the initiator (primary) bus, the following events occur:

• The 21150 asserts p_perr_l two cycles after the data transfer, if the primary interface parity error response bit is set in the command register.
• The 21150 sets the primary interface parity error detected bit in the status register.
• The 21150 captures and forwards the bad parity condition to the secondary bus.
• The 21150 completes the transaction normally. Similarly, during upstream posted write transactions, when the 21150, responding as a target, detects a data parity error on the initiator (secondary) bus, the following events occur:
• The 21150 asserts s_perr_l two cycles after the data transfer, if the secondary interface parity error response bit is set in the bridge control register.
• The 21150 sets the secondary interface parity error detected bit in the secondary status register.
• The 21150 captures and forwards the bad parity condition to the primary bus.
• The 21150 completes the transaction normally. During downstream write transactions, when a data parity error is reported on the target (secondary) bus by the target’s assertion of s_perr_l, the following events occur:
• The 21150 sets the data parity detected bit in the secondary status register, if the secondary interface parity error response bit is set in the bridge control register.
• The 21150 asserts p_serr_l and sets the signaled system error bit in the status register, if all of the following conditions are met: — The SERR# enable bit is set in the command register. — The device-specific p_serr_l disable bit for posted write parity errors is not set. — The secondary interface parity error response bit is set in the bridge control register. — The primary interface parity error response bit is set in the command register. — The 21150 did not detect the parity error on the primary (initiator) bus; that is, the parity error was not forwarded from the primary bus. During upstream write transactions, when a data parity error is reported on the target (primary) bus by the target’s assertion of p_perr_l, the following events occur:
• The 21150 sets the data parity detected bit in the status register, if the primary interface parity error response bit is set in the command register.

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• The 21150 asserts p_serr_l and sets the signaled system error bit in the status register, if all of the following conditions are met: — The SERR# enable bit is set in the command register. — The secondary interface parity error response bit is set in the bridge control register. — The primary interface parity error response bit is set in the command register. — The 21150 did not detect the parity error on the secondary (initiator) bus; that is, the parity error was not forwarded from the secondary bus. The assertion of p_serr_l is used to signal the parity error condition in the case where the initiator does not know that the error occurred. Because the data has already been delivered with no errors, there is no other way to signal this information back to the initiator. If the parity error was forwarded from the initiating bus to the target bus, p_serr_l is not asserted.

7.3 Data Parity Error Reporting Summary

according to the status bits that the 21150 sets and the signals that it asserts. primary interface. This bit is set when the 21150 detects a parity error on the primary interface. Table 25. Setting the Primary Interface Detected Parity Error Bit

0 Read Downstream Primary x/x 1

0 Read Downstream Secondary x/x

1 Read Upstream Primary x/x

0 Read Upstream Secondary x/x

1 Posted write Downstream Primary x/x

0 Posted write Downstream Secondary x/x

0 Posted write Upstream Primary x/x

0 Posted write Upstream Secondary x/x

1 Delayed write Downstream Primary x/x

0 Delayed write Downstream Secondary x/x

0 Delayed write Upstream Primary x/x

0 Delayed write Upstream Secondary x/x

• The 21150 must be a master on the primary bus.
• The parity error response bit in the command register, corresponding to the primary interface, must be set.
• The p_perr_l signal is detected asserted or a parity error is detected on the primary bus. 1. x = don’t care

Table 26. Setting the Secondary Interface Detected Parity Error Bit

1 Read Downstream Secondary x/x

0 Read Upstream Primary x/x

0 Posted write Downstream Primary x/x

1 Posted write Upstream Secondary x/x

0 Delayed write Downstream Primary x/x

1 Delayed write Upstream Secondary x/x

Table 27. Setting the Primary Interface Data Parity Detected Bit

1 Read Upstream Primary 1/x

1 Posted write Upstream Primary 1/x

1 Delayed write Upstream Primary 1/x

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• The 21150 must be a master on the secondary bus.
• The parity error response bit in the bridge control register, corresponding
• to the secondary interface, must be set.
• The s_perr_l signal is detected asserted or a parity error is detected on the secondary bus. 1. x = don’t care Table 29 shows assertion of p_perr_l. This signal is set under the following conditions:
• The 21150 is either the target of a write transaction or the initiator of a read transaction on the primary bus.
• The parity error response bit in the command register, corresponding to the primary interface, must be set.
• The 21150 detects a data parity error on the primary bus or detects s_perr_l asserted during the completion phase of a downstream delayed write transaction on the target (secondary) bus.

Table 28. Setting the Secondary Interface Data Parity Detected Bit

1 Read Downstream Secondary x/1

1 Posted write Downstream Secondary x/1

1 Delayed write Downstream Secondary x/1

Table 29. Assertion of p_perr_l (Sheet 1 of 2)

1 Read Upstream Secondary x/x

0 Posted write Downstream Primary 1/x

• The 21150 is either the target of a write transaction or the initiator of a read transaction on the secondary bus.
• The parity error response bit in the bridge control register, corresponding to the secondary interface, must be set.
• The 21150 detects a data parity error on the secondary bus or detects p_perr_l asserted during the completion phase of an upstream delayed write transaction on the target (primary) bus. 1. x = don’t care Table 31 shows assertion of p_serr_l. This signal is set under the following conditions:
• The 21150 has detected p_perr_l asserted on an upstream posted write transaction or s_perr_l asserted on a downstream posted write transaction.
• The 21150 did not detect the parity error as a target of the posted write transaction.

1 Posted write Upstream Primary x/x

0 Delayed write Downstream Primary 1/x

01 Delayed write Downstream Secondary 1/1

1 Delayed write Upstream Primary x/x

Table 29. Assertion of p_perr_l (Sheet 2 of 2) Table 30. Assertion of s_perr_l

1 Posted write Downstream Secondary x/x

0 Posted write Upstream Secondary x/1

1 Delayed write Downstream Primary 1/x

1 Delayed write Downstream Secondary x/x

01 Delayed write Upstream Primary 1/1

0 Delayed write Upstream Secondary x/1

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• The parity error response bit on the command register and the parity error response bit on the bridge control register must both be set.
• The SERR# enable bit must be set in the command register.

7.4 System Error (SERR#) Reporting

1. The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
2. The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.

addition to the special case parity error conditions described in Section 7.2.3.

• For the 21150 to assert p_serr_l for any reason, the SERR# enable bit must be set in the command register.
• Whenever the 21150 asserts p_serr_l, the 21150 must also set the signaled system error bit in the status register. In compliance with the PCI-to-PCI Bridge Architecture Specification, the 21150 asserts p_serr_l when it detects the secondary SERR# input, s_serr_l, asserted and the SERR# forward enable bit is set in the bridge control register. In addition, the 21150 also sets the received system error bit in the secondary status register. The 21150 also conditionally asserts p_serr_l for any of the following reasons:
• Target abort detected during posted write transaction
• Master abort detected during posted write transaction
• Posted write data discarded after 224 attempts to deliver (224 target retries received)

Table 31. Assertion of p_serr_l for Data Parity Errors

02 Posted write Downstream Secondary 1/1

03 Posted write Upstream Primary 1/1

• Parity error reported on target bus during posted write transaction (see previous section)
• Delayed write data discarded after 224 attempts to deliver (224 target retries received)
• Delayed read data cannot be transferred from target after 224 attempts (224 target retries received)
• Master timeout on delayed transaction The device-specific p_serr_l status register reports the reason for the 21150’s assertion of p_serr_l. Most of these events have additional device-specific disable bits in the p_serr_l event disable register that make it possible to mask out p_serr_l assertion for specific events. The master timeout condition has a SERR# enable bit for that event in the bridge control register and therefore does not have a device-specific disable bit.

8.0 Exclusive Access

This chapter describes the use of the LOCK# signal to implement exclusive access to a target for transactions that cross the 21150.

8.1 Concurrent Locks

The primary and secondary bus lock mechanisms operate concurrently except when a locked transaction crosses the 21150. A primary master can lock a primary target without affecting the status of the lock on the secondary bus, and vice versa. This means that a primary master can lock a primary target at the same time that a secondary master locks a secondary target.

8.2 Acquiring Exclusive Access Across the 21150

For any PCI bus, before acquiring access to the LOCK# signal and starting a series of locked transactions, the initiator must first check that both of the following conditions are met:

• The PCI bus must be idle.
• The LOCK# signal must be deasserted. The initiator leaves the LOCK# signal deasserted during the address phase (only the first address phase of a dual address transaction) and asserts LOCK# one clock cycle later. Once a data transfer is completed from the target, the target lock has been achieved. Locked transactions can cross the 21150 only in the downstream direction, from the primary bus to the secondary bus. When the target resides on another PCI bus, the master must acquire not only the lock on its own PCI bus but also the lock on every bus between its bus and the target’s bus. When the 21150 detects, on the primary bus, an initial locked transaction intended for a target on the secondary bus, the 21150 samples the address, transaction type, byte enable bits, and parity, as described in Section 4.6.4. It also samples the lock signal. Because a target retry is signaled to the initiator, the initiator must relinquish the lock on the primary bus, and therefore the lock is not yet established. The first locked transaction must be a read transaction. Subsequent locked transactions can be read or write transactions. Posted memory write transactions that are a part of the locked transaction sequence are still posted. Memory read transactions that are a part of the locked transaction sequence are not prefetched. When the locked delayed read request is queued, the 21150 does not queue any more transactions until the locked sequence is finished. The 21150 signals a target retry to all transactions initiated subsequent to the locked read transaction that are intended for targets on the other side of the 21150. The 21150 allows any transactions queued before the locked transaction to complete before initiating the locked transaction. When the locked delayed read request transaction moves to the head of the delayed transaction queue, the 21150 initiates the transaction as a locked read transaction by deasserting s_lock_l on the secondary bus during the first address phase, and by asserting s_lock_l one cycle later. If

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s_lock_l is already asserted (used by another initiator), the 21150 waits to request access to the secondary bus until s_lock_l is sampled deasserted when the secondary bus is idle. Note that the existing lock on the secondary bus could not have crossed the 21150; otherwise, the pending queued locked transaction would not have been queued. When the 21150 is able to complete a data transfer with the locked read transaction, the lock is established on the secondary bus. When the initiator repeats the locked read transaction on the primary bus with the same address, transaction type, and byte enable bits, the 21150 transfers the read data back to the initiator, and the lock is then also established on the primary bus. For the 21150 to recognize and respond to the initiator, the initiator’s subsequent attempts of the read transaction must use the locked transaction sequence (deassert p_lock_l during address phase, and assert p_lock_l one cycle later). If the LOCK# sequence is not used in subsequent attempts, a master timeout condition may result. When a master timeout condition occurs, p_serr_l is conditionally asserted (see Section 7.4), the read data and queued read transaction are discarded, and the s_lock_l signal is deasserted on the secondary bus. Once the intended target has been locked, any subsequent locked transactions initiated on the primary bus that are forwarded by the 21150 are driven as locked transactions on the secondary bus. When the 21150 receives a target abort or a master abort in response to the delayed locked read transaction, a target abort is returned to the initiator, and no locks are established on either the target or the initiator bus. The 21150 resumes forwarding unlocked transactions in both directions. When the 21150 detects, on the secondary bus, a locked delayed transaction request intended for a target on the primary bus, the 21150 queues and forwards the transaction as an unlocked transaction. The 21150 ignores s_lock_l for upstream transactions and initiates all upstream transactions as unlocked transactions.

8.3 Ending Exclusive Access

After the lock has been acquired on both the primary and secondary buses, the 21150 must maintain the lock on the secondary (target) bus for any subsequent locked transactions until the initiator relinquishes the lock. The only time a target retry causes the lock to be relinquished is on the first transaction of a locked sequence. On subsequent transactions in the sequence, the target retry has no effect on the status of the lock signal. An established target lock is maintained until the initiator relinquishes the lock. The 21150 does not know whether the current transaction is the last one in a sequence of locked transactions until the initiator deasserts the p_lock_l signal at the end of the transaction. When the last locked transaction is a delayed transaction, the 21150 has already completed the transaction on the secondary bus. In this case, as soon as the 21150 detects that the initiator has relinquished the p_lock_l signal by sampling it in the deasserted state while p_frame_l is deasserted, the 21150 deasserts the s_lock_l signal on the secondary bus as soon as possible. Because of this behavior, s_lock_l may not be deasserted until several cycles after the last locked transaction has been completed on the secondary bus. As soon as the 21150 has deasserted s_lock_l to indicate the end of a sequence of locked transactions, it resumes forwarding unlocked transactions.

When the last locked transaction is a posted write transaction, the 21150 deasserts s_lock_l on the secondary bus at the end of the transaction because the lock was relinquished at the end of the write transaction on the primary bus. When the 21150 receives a target abort or a master abort in response to a locked delayed transaction, the 21150 returns a target abort when the initiator repeats the locked transaction. The initiator must then deassert p_lock_l at the end of the transaction. The 21150 sets the appropriate status bits, flagging the abnormal target termination condition (see Section 4.8). Normal forwarding of unlocked posted and delayed transactions is resumed. When the 21150 receives a target abort or a master abort in response to a locked posted write transaction, the 21150 cannot pass back that status to the initiator. The 21150 asserts p_serr_l when a target abort or a master abort is received during a locked posted write transaction, if the SERR# enable bit is set in the command register. Signal p_serr_l is asserted for the master abort condition if the master abort mode bit is set in the bridge control register (see Section 7.4).

9.0 PCI Bus Arbitration

The 21150 must arbitrate for use of the primary bus when forwarding upstream transactions, and for use of the secondary bus when forwarding downstream transactions. The arbiter for the primary bus resides external to the 21150, typically on the motherboard. For the secondary PCI bus, the 21150 implements an internal arbiter. This arbiter can be disabled, and an external arbiter can be used instead. This chapter describes primary and secondary bus arbitration.

9.1 Primary PCI Bus Arbitration

The 21150 implements a request output pin, p_req_l, and a grant input pin, p_gnt_l, for primary PCI bus arbitration. The 21150 asserts p_req_l when forwarding transactions upstream; that is, it acts as initiator on the primary PCI bus. As long as at least one pending transaction resides in the queues in the upstream direction, either posted write data or delayed transaction requests, the 21150 keeps p_req_l asserted. However, if a target retry, target disconnect, or a target abort is received in response to a transaction initiated by the 21150 on the primary PCI bus, the 21150 deasserts p_req_l for two PCI clock cycles. For posted write transactions (see Section 4.5.1), p_req_l is asserted one cycle after s_devsel_l is asserted. For delayed read and write requests, p_req_l is not asserted until the transaction request has been completely queued in the delayed transaction queue (target retry has been returned to the initiator) and is at the head of the delayed transaction queue. When p_gnt_l is asserted low by the primary bus arbiter after the 21150 has asserted p_req_l, the 21150 initiates a transaction on the primary bus during the next PCI clock cycle. When p_gnt_l is asserted to the 21150 when p_req_l is not asserted, the 21150 parks p_ad, p_cbe_l, and p_par by driving them to valid logic levels. When the primary bus is parked at the 21150 and the 21150 then has a transaction to initiate on the primary bus, the 21150 starts the transaction if p_gnt_l was asserted during the previous cycle.

9.2 Secondary PCI Bus Arbitration

The 21150 implements an internal secondary PCI bus arbiter. This arbiter supports nine external masters in addition to the 21150. The internal arbiter can be disabled, and an external arbiter can be used instead for secondary bus arbitration.

9.2.1 Secondary Bus Arbitration Using the Internal Arbiter

To use the internal arbiter, the secondary bus arbiter enable pin, s_cfn_l, must be tied low. The 21150 has nine secondary bus request input pins, s_req_l<8:0>, and nine secondary bus output grant pins, s_gnt_l<8:0>, to support external secondary bus masters. The 21150 secondary bus request and grant signals are connected internally to the arbiter and are not brought out to external pins when s_cfn_l is low.

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transaction. The master that initiated the last transaction now has the lowest priority in its group. receive any more grants until it deasserts its request for at least one PCI clock cycle. Figure 18. Secondary Arbiter Example

To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one grant signal in the same PCI cycle in which it deasserts another. It deasserts one grant, and then asserts the next grant, no earlier than one PCI clock cycle later. If the secondary PCI bus is busy, that is, either s_frame_l or s_irdy_l is asserted, the arbiter can deassert one grant and assert another grant during the same PCI clock cycle.

9.2.2 Secondary Bus Arbitration Using an External Arbiter

The internal arbiter is disabled when the secondary bus central function control pin, s_cfn_l, is pulled high. An external arbiter must then be used. When s_cfn_l is tied high, the 21150 reconfigures two pins to be external request and grant pins. The s_gnt_l<0> pin is reconfigured to be the 21150’s external request pin because it is an output. The s_req_l<0> pin is reconfigured to be the external grant pin because it is an input. When an external arbiter is used, the 21150 uses the s_gnt_l<0> pin to request the secondary bus. When the reconfigured s_req_l<0> pin is asserted low after the 21150 has asserted s_gnt_l<0>, the 21150 initiates a transaction on the secondary bus one cycle later. If s_req_l<0> is asserted and the 21150 has not asserted s_gnt_l<0>, the 21150 parks the s_ad, s_cbe_l, and s_par pins by driving them to valid logic levels. The unused secondary bus grant outputs, s_gnt_l<8:1>, are driven high. Unused secondary bus request inputs, s_req_l<8:1>, should be pulled high.

9.2.3 Bus Parking

Bus parking refers to driving the AD, C/BE#, and PAR lines to a known value while the bus is idle. In general, the device implementing the bus arbiter is responsible for parking the bus or assigning another device to park the bus. A device parks the bus when the bus is idle, its bus grant is asserted, and the device’s request is not asserted. The AD and C/BE# signals should be driven first, with the PAR signal driven one cycle later. The 21150 parks the primary bus only when p_gnt_l is asserted, p_req_l is deasserted, and the primary PCI bus is idle. When p_gnt_l is deasserted, the 21150 tristates the p_ad, p_cbe_l, and p_par signals on the next PCI clock cycle. If the 21150 is parking the primary PCI bus and wants to initiate a transaction on that bus, then the 21150 can start the transaction on the next PCI clock cycle by asserting p_frame_l if p_gnt_l is still asserted. If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last master that used the PCI bus. That is, the 21150 keeps the secondary bus grant asserted to a particular master until a new secondary bus request comes along. After reset, the 21150 parks the secondary bus at itself until transactions start occurring on the secondary bus. If the internal arbiter is disabled, the 21150 parks the secondary bus only when the reconfigured grant signal, s_req_l<0>, is asserted and the secondary bus is idle.

10.0 General-Purpose I/O Interface

The 21150 implements a 4-pin general-purpose I/O gpio interface. During normal operation, the gpio interface is controlled by device-specific configuration registers. In addition, the gpio interface can be used for the following functions:

• During secondary interface reset, the gpio interface can be used to shift in a 16-bit serial stream that serves as a secondary bus clock disable mask.
• A live insertion bit can be used, along with the gpio<3> pin, to bring the 21150 gracefully to a halt through hardware, permitting live insertion of option cards behind the 21150. 10.1 gpio Control Registers During normal operation, the gpio interface is controlled by the following device-specific configuration registers:
• The gpio output data register
• The gpio output enable control register
• The gpio input data register These registers consist of five 8-bit fields:
• Write-1-to-set output data field
• Write-1-to-clear output data field
• Write-1-to-set signal output enable control field
• Write-1-to-clear signal output enable control field
• Input data field The bottom 4 bits of the output enable fields control whether each gpio signal is input only or bidirectional. Each signal is controlled independently by a bit in each output enable control field. If a 1 is written to the write-1-to-set field, the corresponding pin is activated as an output. If a 1 is written to the write-1-to-clear field, the output driver is tristated, and the pin is then input only. Writing zeros to these registers has no effect. The reset state for these signals is input only. The input data field is read only and reflects the current value of the gpio pins. A type 0 configuration read operation to this address is used to obtain the values of these pins. All pins can be read at any time, whether configured as input only or as bidirectional. The output data fields also use the write-1-to-set and write-1-to-clear method. If a 1 is written to the write-1-to-set field and the pin is enabled as an output, the corresponding gpio output is driven high. If a 1 is written to the write-1-to-clear field and the pin is enabled as an output, the corresponding gpio output is driven low. Writing zeros to these registers has no effect. The value written to the output register will be driven only when the gpio signal is configured as bidirectional. A type 0 configuration write operation is used to program these fields. The reset value for the output is 0.

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10.2 Secondary Clock Control

register control and serial data input. Table 32 shows the operation of the gpio pins. The data is input through the dedicated input signal, msk_in. force all secondary clock outputs high. Table 33 shows the format of the serial stream. Table 32. gpio Operation Table 33. gpio Serial Data Format

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least significant bit is shifted in last. Figure 20 shows a timing diagram for the load and for the beginning of the shift operation.

10.3 Live Insertion

21150 completes any posted write or delayed request transactions that have already been queued. not responding to any I/O or memory transactions during this time. Note that the 21150 continues to accept configuration transactions in live insertion mode. Figure 20. Clock Mask Load and Shift Timing

Once live insertion mode brings the 21150 to a halt and queued transactions are completed, the secondary reset bit in the bridge control register can be used to assert s_rst_l, if desired, to reset and tristate secondary bus devices, and to enable any live insertion hardware.

11.0 Clocks

This chapter provides information about the 21150 clocks.

11.1 Primary and Secondary Clock Inputs

secondary clock input, s_clk. capable. s_clk operates either at the same frequency or at half the frequency as p_clk. primary and the secondary clock inputs.

11.2 Secondary Clock Outputs

nine external secondary bus devices and for the 21150 secondary clock input. minimum of 0 ns and a maximum of 5 ns. The maximum skew between s_clk_o edges is 500 ps. delay is allowed for secondary clock etch returning to the device secondary clock inputs.

• Each secondary clock output is limited to one load.
• One of the secondary clock outputs must be used for the 21150 s_clk input.

Figure 21. p_clk and s_clk Relative Timing

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• DIGITAL recommends using an equivalent amount of etch on the board for all secondary clocks, to minimize skew between them, and a maximum delay of the etch of 2 ns.
• DIGITAL recommends terminating or disabling unused secondary clock outputs to reduce power dissipation and noise in the system.

11.3 Disabling Unused Secondary Clock Outputs

When secondary clock outputs are not used, both gpio<3:0> and msk_in can be used to clock in a serial mask that selectively tristates secondary clock outputs. Section 10.2 describes how the 21150 uses the gpio pins and the msk_in signal to input this data stream. After the serial mask has been shifted into the 21150, the value of the mask is readable and modifiable in the secondary clock disable mask register. When the mask is modified by a configuration write operation to this register, the new clock mask disables the appropriate secondary clock outputs within a few cycles. This feature allows software to disable or enable secondary clock outputs based on the presence of option cards, and so on. The 21150 delays deasserting the secondary reset signal, s_rst_l, until the serial clock mask has been completely shifted in and the secondary clocks have been disabled or enabled, according to the mask. The delay between p_rst_l deassertion and s_rst_l deassertion is approximately 23 cycles (46 cycles if s_clk is operating at 66 MHz).

12.0 66-Mhz Operation Some versions of the 21150 support 66 MHz operation. All 21150 versions marked 21150-Bx are 66MHz capable. V ersions of the 21150 marked 21150-Ax are not capable of operation at 66 MHz. Signal config66 must be tied high on the board to enable 66 MHz operation and to set the 66 MHz Capable bit in the Status register and Secondary Status register in configuration space. If the 21150 version is not 66MHz capable, then config66 should be tied low. Signals p_m66ena and s_m66ena should never be pulled high unless config66 is also high. Signals p_m66ena and s_m66ena indicate whether the primary and secondary interfaces, respectively, are operating at 66 MHz 1. This information is needed to control the frequency of the secondary bus. Note that the PCI Local Bus Specification, Revision 2.1 restricts clock frequency changes above 33 MHz to during PCI reset only. The 66Mhz capable 21150 supports the following primary and secondary bus frequency combinations:

• 66 MHz primary bus, 66 MHz secondary bus
• 66 MHz primary bus, 33 MHz secondary bus
• 33 MHz primary bus, 33 MHz secondary bus The 21150 does not support 33 MHz primary/66 MHz secondary bus operation, where the secondary bus is operating at twice the frequency of the primary bus. If config66 is high and p_m66ena is low (66 MHz capable, primary bus at 33MHz), then the 21150 pulls down s_m66ena to indicate that the secondary bus is operating at 33 MHz. The 21150 generates the clock signals (s_clk_o<9:0>) for the secondary bus devices and its own secondary interface. The 21150 divides the primary bus clock p_clk by two to generate the secondary bus clock outputs whenever the primary bus is operating at 66 MHz and the secondary bus is operating at 33 MHz. The bridge detects this condition when p_m66ena is high and s_m66ena is low. 1. In general, 66-MHz operation means operation ranging from 33 MHz up to 66 MHz.

13.0 PCI Power Management

• PCI Power Management registers using the Enhanced Capabilities Port (ECP) address mechanism
• Support for D0, D3hot and D3cold power management states
• Support for D0, D1, D2, D3hot, and D3cold power management states for devices behind the bridge
• Support of the B2 secondary bus power state when in the D3hot power management state Table 34 shows the states and related actions that the 21150 performs during power management transitions. (No other transactions are permitted.) 1. The 21150-AA does not include these features. PME# signals are routed from downstream devices around PCI-to-PCI bridges. PME# signals do not pass through PCI-to-PCI bridges.

Table 34. Power Management Transitions be performed to bring the 21150 to D0. secondary clocks and drive them low. power state bits (power state remains at D0). power state bits (power state remains at D0). will be returned to the reset values and buffers will be cleared. be performed to bring the 21150 to D0. functions as described in Chapter 13.

14.0 Reset

This chapter describes the primary interface, secondary interface, and chip reset mechanisms.

14.1 Primary Interface Reset

The 21150 has one reset input, p_rst_l. When p_rst_l is asserted, the following events occur:

• The 21150 immediately tristates all primary and secondary PCI interface signals.
• The 21150 performs a chip reset.
• Registers that have default values are reset. Appendix A lists the values of all configuration space registers after reset. The p_rst_l asserting and deasserting edges can be asynchronous to p_clk and s_clk.

14.2 Secondary Interface Reset

The 21150 is responsible for driving the secondary bus reset signal, s_rst_l. The 21150 asserts s_rst_l when any of the following conditions is met:

• Signal p_rst_l is asserted. Signal s_rst_l remains asserted as long as p_rst_l is asserted and does not deassert until p_rst_l is deasserted and the secondary clock serial disable mask has been shifted in (23 or 46 clock cycles after p_rst_l deassertion).
• The secondary reset bit in the bridge control register is set. Signal s_rst_l remains asserted until a configuration write operation clears the secondary reset bit and the secondary clock serial mask has been shifted in.
• The chip reset bit in the diagnostic control register is set. Signal s_rst_l remains asserted until a configuration write operation clears the secondary reset bit and the secondary clock serial mask has been shifted in. When s_rst_l is asserted, all secondary PCI interface control signals, including the secondary grant outputs, are immediately tristated. Signals s_ad, s_cbe_l, and s_par are driven low for the duration of s_rst_l assertion. All posted write and delayed transaction data buffers are reset; therefore, any transactions residing in 21150 buffers at the time of secondary reset are discarded. When s_rst_l is asserted by means of the secondary reset bit, the 21150 remains accessible during secondary interface reset and continues to respond to accesses to its configuration space from the primary interface.

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14.3 Chip Reset

The chip reset bit in the diagnostic control register can be used to reset the 21150 and the secondary bus. When the chip reset bit is set, all registers and chip state are reset and all signals are tristated.In addition, s_rst_l is asserted, and the secondary reset bit is automatically set. Signal s_rst_l remains asserted until a configuration write operation clears the secondary reset bit and the serial clock mask has been shifted in. As soon as chip reset completes, within 20 PCI clock cycles after completion of the configuration write operation that sets the chip reset bit, the chip reset bit automatically clears and the chip is ready for configuration. During chip reset, the 21150 is inaccessible.

15.0 Configuration Space Registers

This chapter provides a detailed description of the 21150 configuration space registers. The chapter is divided into three sections: Section 15.1 describes the standard 21150 PCI-to-PCI bridge configuration registers, Section 15.2 describes the 21150 device-specific configuration registers, and Section 15.3 describes the configuration register values after reset. The 21150 configuration space uses the PCI-to-PCI bridge standard format specified in the PCI-to- PCI Bridge Architecture Specification. The header type at configuration address 0Eh reads as 01h, indicating that this device uses the PCI-to-PCI bridge format. The 21150 also contains device-specific registers, starting at address 40h. Use of these registers is not required for standard PCI-to-PCI bridge implementations. The configuration space registers can be accessed only from the primary PCI bus. To access a register, perform a Type 0 format configuration read or write operation to that register. During the Type 0 address phase, p_ad<7:2> indicates the Dword offset of the register. During the data phase, p_cbe_l<3:0> selects the bytes in the Dword that is being accessed. Caution: Software changes the configuration register values that affect 21150 behavior only during initialization. Change these values subsequently only when both the primary and secondary PCI buses are idle, and the data buffers are empty; otherwise, the behavior of the 21150 is unpredictable. Figure 22 shows a summary of the configuration space.

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Figure 22. 21150 Configuration Space

• In the 21150-AA only, these registers are R/W: Subsystem ID and Subsystem Vendor ID.

** These are reserved for the 21150-AA.

15.1 PCI-to-PCI Bridge Standard Configuration Registers

This section provides a detailed description of the PCI-to-PCI bridge standard configuration registers. Each field has a separate description. Fields that have the same configuration Dword address are selectable by turning on (driving low) the appropriate byte enable bits on p_cbe_l during the data phase. To select all fields of a configuration address, drive all byte enable bits low. All reserved fields and registers are read only and always return 0.

15.1.1 Vendor ID Register—Offset 00h

This section describes the vendor ID register. Dword address = 00h Byte enable p_cbe_l<3:0> = xx00b

15.1.2 Device ID Register—Offset 02h

This section describes the device ID register. Dword address = 00h Byte enablep_cbe_l<3:0> = 00xxb

15.1.3 Primary Command Register—Offset 04h

This section describes the primary command register. These bits affect the behavior of the 21150 primary interface, except where noted. Some of the bits are repeated in the bridge control register, to act on the secondary interface. This register must be initialized by configuration software. Dword address = 04h Byte enable p_cbe_l<3:0> = xx00b Dword Bit Name R/W Description 15:0 Vendor ID R Identifies the vendor of this device. Internally hardwired to be 1011h Dword Bit Name R/W Description 31:16 Device ID R Identifies this device as the 21150. Internally hardwired to be 22h.

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Dword Bit Name R/W Description

0 I/O space enable R/W

Controls the 21150’s response to I/O transactions on the primary interface. When 0—The 21150 does not respond to I/O transactions initiated on the primary bus. \\When 1—The 21150 response to I/O transactions initiated on the secondary bus is enabled. Reset value: 0.

1 Memory space enable R/W

Controls the 21150’s response to memory transactions on the 21150 primary interface. When 0—The 21150 does not respond to memory transactions initiated on the primary bus. When 1—The 21150 response to memory transactions initiated on the primary bus is enabled. Reset value: 0.

2 Master enable R/W

Controls the 21150’s ability to initiate memory and I/O transactions on the primary bus on behalf of an initiator on the secondary bus. Forwarding of configuration transactions is not affected. When 0—The 21150 does not respond to I/O or memory transactions on the secondary interface and does not initiate I/O or memory transactions on the primary interface. When 1—The 21150 is enabled to operate as an initiator on the primary bus and responds to I/O and memory transactions initiated on the secondary bus. Reset value: 0.

3 Special cycle enable R The 21150 ignores special cycle transactions,

so this bit is read only and returns 0.

4 Memory write and

The 21150 generates memory write and invalidate transactions only when operating on behalf of another master whose memory write and invalidate transaction is crossing the 21150. This bit is read only and returns 0.

5 VGA snoop enable R/W

Controls the 21150’s response to VGA- compatible palette write transactions. VGA palette write transactions correspond to I/O transactions whose address bits are as follows:

• p_ad<9:0> are equal to 3C6h, 3C8h, and 3C9h.
• p_ad<15:10> are not decoded.
• p_ad<31:16> must be 0. When 0—VGA palette write transactions on the primary interface are ignored unless they fall inside the 21150’s I/O address range. When 1—VGA palette write transactions on the primary interface are positively decoded and forwarded to the secondary interface. Reset value: 0.

15.1.4 Primary Status Register—Offset 06h

This section describes the primary status register. These bits affect the status of the 21150 primary interface. Bits reflecting the status of the secondary interface are found in the secondary status register. W1TC indicates that writing 1 to a bit sets that bit to 0. Writing 0 has no effect. Dword address = 04h Byte enable p_cbe_l<3:0> = 00xxb

6 Parity error response R/W

Controls the 21150’s response when a parity error is detected on the primary interface. When 0—The 21150 does not assert p_perr_l, nor does it set the data parity reported bit in the status register. The 21150 does not report address parity errors by asserting p_serr_l. When 1—The 21150 drives p_perr_l and conditionally sets the data parity reported bit in the status register when a data parity error is detected (see Section 7.0). The 21150 allows p_serr_l assertion when address parity errors are detected on the primary interface. Reset value: 0.

7 Wait cycle control R Reads as 0 to indicate that the 21150 does not

perform address or data stepping.

8 SERR# enable R/W

Controls the enable for p_serr_l on the primary interface. When 0—Signal p_serr_l cannot be driven by the 21150. When 1—Signal p_serr_l can be driven low by the 21150 under the conditions described in Section 7.4. Reset value: 0.

9 Fast back-to-back enable R/W

Controls the ability of the 21150 to generate fast back-to-back transactions on the primary bus. When 0—The 21150 does not generate back- to-back transactions on the primary bus. When 1—The 21150 is enabled to generate back-to-back transactions on the primary bus. Reset value: 0. 15;10 Reserved R Reserved. Returns 0 when read. Dword Bit Name R/W Description

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Dword Bit Name R/W Description 19:16 Reserved R Reserved. Returns 0 when read.

20 ECP R

Enhanced Capabilities Port (ECP) enable. Reads as 1 in the 21150-AB and later revisions to indicate that the 21150-AB supports an enhanced capabilities list. The 21150-AA reads as 0 to show that this capability is not supported. 21 66-MHz capable R Indicates whether the primary interface is 66- MHz capable. Reads as 0 when pin config66 is tied low to indicate that the 21150 is not 66 MHz capable. Reads as 1 when pin config66 is tied high to indicate that the primary bus is 66 MHz capable. 22 Reserved R Reserved. Returns 0 when read.

23 Fast back-to-back

Reads as 1 to indicate that the 21150 is able to respond to fast back-to-back transactions on the primary interface.

24 Data parity detected R/W1TC

This bit is set to 1 when all of the following are true:

• The 21150 is a master on the primary bus.
• Signal p_perr_l is detected asserted, or a parity error is detected on the primary bus.
• The parity error response bit is set in the command register. Reset value: 0. 26:25 DEVSEL# timing R Indicates slowest response to a nonconfiguration command on the primary interface. Reads as 01b to indicate that the 21150 responds no slower than with medium timing.

27 Signaled target abort R/W1TC

This bit is set to 1 when the 21150 is acting as a target on the primary bus and returns a target abort to the primary master. Reset value: 0.

28 Received target abort R/W1TC

This bit is set to 1 when the 21150 is acting as a master on the primary bus and receives a target abort from the primary target. Reset value: 0.

29 Received master abort R/W1TC

This bit is set to 1 when the 21150 is acting as a master on the primary bus and receives a master abort. Reset value: 0.

30 Signaled system error R/W1TC

This bit is set to 1 when the 21150 has asserted p_serr_l. Reset value: 0.

31 Detected parity error R/W1TC

This bit is set to 1 when the 21150 detects an address or data parity error on the primary interface. Reset value: 0.

15.1.5 Revision ID Register—Offset 08h

This section describes the revision ID register. Dword address = 08h Byte enable p_cbe_l<3:0> = xxx0b

15.1.6 Programming Interface Register—Offset 09h

This section describes the programming interface register. Dword address = 08h Byte enable p_cbe_l<3:0> = xx0xb

15.1.7 Subclass Code Register—Offset 0Ah

This section describes the subclass code register. Dword address = 08h Byte enable p_cbe_l<:0> = x0xxb

15.1.8 Base Class Code Register—Offset 0Bh

This section describes the base class code register. Dword address = 08h Byte enable p_cbe_l<3> = 0xxxb Dword Bit Name R/W Description 7:0 Revision ID R Indicates the revision number of this device. The initial revision reads as 0. Subsequent revisions increment by 1. Dword Bit Name R/W Description 15:8 Programming interface R No programming interfaces have been defined for PCI-to-PCI bridges. Reads as 0. Dword Bit Name R/W Description 23:16 Subclass code R Reads as 04h to indicate that this bridge device is a PCI-to-PCI bridge. Dword Bit Name R/W Description 31:24 Base class code R Reads as 06h to indicate that this device is a bridge device.

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15.1.9 Cache Line Size Register—Offset 0Ch

This section describes the cache line size register. Dword address = 0Ch Byte enable p_cbe_l<3:0> = xxx0b

15.1.10 Primary Latency Timer Register—Offset 0Dh

This section describes the primary latency timer register. Dword address = 0Ch Byte enable p_cbe_l<3:0> = xx0xb

15.1.11 Header Type Register—Offset 0Eh

This section describes the header type register. Dword address = 0Ch Byte enable p_cbe_l<3:0> = x0xxb Dword Bit Name R/W Description 7:0 Cache line size R/W Designates the cache line size for the system in units of 32-bit Dwords. Used for prefetching memory read transactions and for terminating memory write and invalidate transactions. The cache line size should be written as a power of 2. If the value is not a power of 2 or is greater than 16, the 21150 behaves as if the cache line size were 0. Reset value: 0. Dword Bit Name R/W Description 15:8 Master latency timer R/W Master latency timer for the primary interface. Indicates the number of PCI clock cycles from the assertion of p_frame_l to the expiration of the timer when the 21150 is acting as a master on the primary interface. All bits are writable, resulting in a granularity of one PCI clock cycle. When 0—The 21150 relinquishes the bus after the first data transfer when the 21150’s primary bus grant has been deasserted, with the exception of memory write and invalidate transactions. Reset value: 0. Dword Bit Name R/W Description 23:16 Header type R Defines the layout of addresses 10h through 3Fh in configuration space. Reads as 01h to indicate that the register layout conforms to the standard PCI-to-PCI bridge layout.

15.1.12 Primary Bus Number Register—Offset 18h

This section describes the primary bus number register. This register must be initialized by configuration software. Dword address = 18h Byte enable p_cbe_l<3:0> = xxx0b

15.1.13 Secondary Bus Number Register—Offset 19h

This section describes the secondary bus number register. This register must be initialized by configuration software. Dword address = 18h Byte enable p_cbe_l<3:0>= xx0xb

15.1.14 Subordinate Bus Number Register—Offset 1Ah

This section describes the subordinate bus number register. This register must be initialized by configuration software. Dword address = 18h Byte enable p_cbe_l<3:0>= x0xxb Dword Bit Name R/W Description 7:0 Primary bus number R/W Indicates the number of the PCI bus to which the primary interface is connected. The 21150 uses this register to decode Type 1 configuration transactions on the secondary interface that should either be converted to special cycle transactions on the primary interface or passed upstream unaltered. Reset value: 0. Dword Bit Name R/W Description 15:8 Secondary bus number R/W Indicates the number of the PCI bus to which the secondary interface is connected. The 21150 uses this register to determine when to respond to and forward Type 1 configuration transactions on the primary interface, and to determine when to convert them to Type 0 or special cycle transactions on the secondary interface. Reset value: 0.

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15.1.15 Secondary Latency Timer Register—Offset 1Bh

This section describes the secondary latency timer register. Dword address = 18h Byte enable p_cbe_l<3:0> = 0xxxb

15.1.16 I/O Base Address Register—Offset 1Ch

This section describes the I/O base address register. This register must be initialized by configuration software. Dword address = 1Ch Byte enable p_cbe_l<3:0> = xxx0b Dword Bit Name R/W Description 23:16 Subordinate bus number R/W Indicates the number of the highest numbered PCI bus that is behind (or subordinate to) the 21150. Used in conjunction with the secondary bus number to determine when to respond to Type 1 configuration transactions on the primary interface and pass them to the secondary interface as a Type 1 configuration transaction. Reset value: 0. Dword Bit Name R/W Description 31:24 Secondary latency timer R/W Master latency timer for the secondary interface. Indicates the number of PCI clock cycles from the assertion of s_frame_l to the expiration of the timer when the 21150 is acting as a master on the secondary interface. All bits are writable, resulting in a granularity of one PCI clock cycle. When 0—The 21150 ends the transaction after the first data transfer when the 21150’s secondary bus grant has been deasserted, with the exception of memory write and invalidate transactions. Reset value: 0.

15.1.17 I/O Limit Address Register—Offset 1Dh

This section describes the I/O limit address register. This register must be initialized by configuration software. Dword address = 1Ch Byte enable p_cbe_l<3:0> = xx0xb

15.1.18 Secondary Status Register—Offset 1Eh

This section describes the secondary status register. These bits reflect the status of the 21150 secondary interface. W1 TC indicates that writing 1 to that bit sets the bit to 0. Writing 0 has no effect. Dword address = 1Ch Byte enable p_cbe_l<3:0> = 00xxb Dword Bit Name R/W Description 3:0 32-bit indicator R The low 4 bits of this register read as 1h to indicate that the 21150 supports 32-bit I/O address decoding. 7:4 I/O base address <15:12> R/W Defines the bottom address of an address range used by the 21150 to determine when to forward I/O transactions from one interface to the other. The upper 4 bits are writable and correspond to address bits <15:12>. The lower 12 bits of the address are assumed to be 0. The upper 16 bits corresponding to address bits <31:16> are defined in the I/O base address upper 16 bits register. The I/O address range adheres to 4 KB alignment and granularity. Reset value: 0. Dword Bit Name R/W Description 11:8 32-bit indicator R/W The low 4 bits of this register read as 1h to indicate that the 21150 supports 32-bit I/O address decoding. 15:12 I/O limit address <15:12> R/W Defines the top address of an address range used by the 21150 to determine when to forward I/O transactions from one interface to the other. The upper 4 bits are writable and correspond to address bits <15:12>. The lower 12 bits of the address are assumed to be FFFh. The upper 16 bits corresponding to address bits <31:16> are defined in the I/O limit address upper 16 bits register. The I/O address range adheres to 4KB alignment and granularity. Reset value: 0.

114 Preliminary Datasheet

Dword Bit Name R/W Description 20:16 Reserved R Reserved. Returns 0 when read. 21 66-MHz capable R Indicates whether the secondary interface is 66-MHz capable. Reads as 0 when pin config66 is tied low to indicate that the 21150 is not 66 MHz capable. Reads as 1 when pin config66 is tied high to indicate that the secondary bus is 66 MHz capable. 22 Reserved R Reserved. Returns 0 when read. Reads as 1 to indicate that the 21150 is able to respond to fast back-to-back transactions on the secondary interface. This bit is set to 1 when all of the following are true:

• The 21150 is a master on the secondary bus.
• Signal s_perr_l is detected asserted, or a parity error is detected on the secondary bus.
• The parity error response bit is set in the bridge control register. Reset value: 0. 26:25 DEVSEL# timing R Indicates slowest response to a command on the secondary interface. Reads as 01b to indicate that the 21150 responds no slower than with medium timing.

This bit is set to 1 when the 21150 is acting as a target on the secondary bus and returns a target abort to the secondary bus master. Reset value: 0. This bit is set to 1 when the 21150 is acting as a master on the secondary bus and receives a target abort from the secondary bus target. Reset value: 0. This bit is set to 1 when the 21150 is acting as an initiator on the secondary bus and receives a master abort. Reset value: 0.

30 Received system error R/W1TC

This bit is set to 1 when the 21150 detects the assertion of s_serr_l on the secondary interface. Reset value: 0. This bit is set to 1 when the 21150 detects an address or data parity error on the secondary interface. Reset value: 0.

15.1.19 Memory Base Address Register—Offset 20h

This section describes the memory base address register. This register must be initialized by configuration software. Dword address = 20h Byte enable p_cbe_l<3:0> = xx00b

15.1.20 Memory Limit Address Register—Offset 22h

This section describes the memory limit address register. This register must be initialized by configuration software. Dword address = 20h Byte enable p_cbe_l<3:0> = 00xxb

15.1.21 Prefetchable Memory Base Address Register—Offset 24h

This section describes the prefetchable memory base address register. This register must be initialized by configuration software. Dword address = 24h Byte enable p_cbe_l<3:0> = xx00b Dword Bit Name R/W Description 3:0 Reserved R The low 4 bits of this register are read only and return 0. 15:4 Memory base address <31:20> R/W Defines the bottom address of an address range used by the 21150 to determine when to forward memory transactions from one interface to the other. The upper 12 bits are writable and correspond to address bits <31:20>. The lower 20 bits of the address are assumed to be 0. The memory address range adheres to 1MB alignment and granularity. Reset value: 0. Dword Bit Name R/W Description 19:16 Reserved R The low 4 bits of this register are read only and return 0. 31:20 Memory limit address <31:20> R/W Defines the top address of an address range used by the 21150 to determine when to forward memory transactions from one interface to the other. The upper 12 bits are writable and correspond to address bits <31:20>. The lower 20 bits of the address are assumed to be FFFFFh. The memory address range adheres to 1MB alignment and granularity. Reset value: 0.

116 Preliminary Datasheet

15.1.22 Prefetchable Memory Limit Address Register—Offset 26h

This section describes the prefetchable memory limit address register. This register must be initialized by configuration software. Dword address = 24h Byte enable p_cbe_l<3:0> = 00xxb

15.1.23 Prefetchable Memory Base Address Upper 32 Bits Register—Offset

This section describes the prefetchable memory base address upper 32 bits register. This register must be initialized by configuration software. Dword address = 28h Byte enable p_cbe_l<3:0>= 0000b Dword Bit Name R/W Description 3:0 64-bit indicator R The low 4 bits of this register are read only and return 1h to indicate that this range supports 64-bit addressing. 15:4 Prefetchable memory base address <31:20> R/W Defines the bottom address of an address range used by the 21150 to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits are writable and correspond to address bits <31:20>. The lower 20 bits of the address are assumed to be 0. The memory base register upper 32 bits contains the upper half of the base address. The memory address range adheres to 1MB alignment and granularity. Reset value: 0. Dword Bit Name R/W Description 19:16 64-bit indicator R The low 4 bits of this register are read only and return 1h to indicate that this range supports 64-bit addressing. 31:20 Prefetchable memory limit address <31:20> R/W Defines the top address of an address range used by the 21150 to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits are writable and correspond to address bits <31:20>. The lower 20 bits of the address are assumed to be FFFFFh. The memory limit upper 32 bits register contains the upper half of the limit address. The memory address range adheres to 1MB alignment and granularity. Reset value: 0.

15.1.24 Prefetchable Memory Limit Address Upper 32 Bits Register—Offset

This section describes the prefetchable memory limit address upper 32 bits register. This register must be initialized by configuration software. Dword address = 2Ch Byte enable p_cbe_l<3:0> = 0000b

15.1.25 I/O Base Address Upper 16 Bits Register—Offset 30h

This section describes the I/O base address upper 16 bits register. This register must be initialized by configuration software. Dword address = 30h Byte enable p_cbe_l<3:0> = xx00b Dword Bit Name R/W Description 31:0 Upper 32 prefetchable memory base address <63:32> R/W Defines the upper 32 bits of a 64-bit bottom address of an address range used by the 21150 to determine when to forward memory read and write transactions from one interface to the other. The memory address range adheres to 1MB alignment and granularity. Reset value: 0. Dword Bit Name R/W Description 31:0 Upper 32 prefetchable memory limit address <63:32> R/W Defines the upper 32 bits of a 64-bit top address of an address range used by the 21150 to determine when to forward memory read and write transactions from one interface to the other. Extra read transactions should have no side effects. The memory address range adheres to 1MB alignment and granularity. Reset value: 0. Dword Bit Name R/W Description 15:0 I/O base address upper 16 bits <31:16> R/W Defines the upper 16 bits of a 32-bit bottom address of an address range used by the 21150 to determine when to forward I/O transactions from one interface to the other. The I/O address range adheres to 4KB alignment and granularity. Reset value: 0.

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15.1.26 I/O Limit Address Upper 16 Bits Register—Offset 32h

This section describes the I/O limit address upper 16 bits register. This register must be initialized by configuration software. Dword address = 30h Byte enable p_cbe_l<3:0> = 00xxb

15.1.27 Subsystem Vendor ID Register—Offset 34h

This section describes the subsystem vendor ID register. Dword address = 34h Byte enable p_cbe_l<3:0> = xx00b15.1.28 ECP Pointer Register—Offset 34h This section describes the ECP pointer register. Dword address = 34h Byte enable p_cbe_l<3:0> = 0000b Dword Bit Name R/W Description 31:16 I/O limit address upper 16 bits <31:16> R/W Defines the upper 16 bits of a 32-bit top address of an address range used by the 21150 to determine when to forward I/O transactions from one interface to the other. The I/O address range adheres to 4KB alignment and granularity. Reset value: 0. Dword Bit Name R/W Description 15:0 Subsystem vendor ID R/W Provides a mechanism allowing add-in cards to distinguish their cards from one another. The 21150 provides a writable subsystem vendor ID that can be initialized during POST. This register is only implemented in the 21150-AA. Reset to 0. Dword Bit Name R/W Description 7:0 ECP_PTR R Enhanced Capabilities Port (ECP) offset pointer. Reads as DCh in the 21150-AB and later revisions to indicate that the first item, which corresponds to the power management registers, resides at that configuration offset. This is a R/W register with no side effects in the 21150-AA. 31:8 Reserved R Reserved. The 21150-AB and later revisions return 0 when read. This is a R/W register with no side effects in the 21150-AA.

15.1.29 Subsystem ID Register—Offset 36h

This section describes the subsystem ID register. Dword address = 34h Byte enable p_cbe_l<3:0> = 00xxb

15.1.30 Interrupt Pin Register—Offset 3Dh

This section describes the interrupt pin register. Dword address = 3Ch Byte enable p_cbe_l<3:0> = xx0xb

15.1.31 Bridge Control Register—Offset 3Eh

This section describes the bridge control register. This register must be initialized by configuration software. Dword address = 3Ch Byte enable p_cbe_l<3:0>= 00xxb Dword Bit Name R/W Description 31:16 Subsystem ID R/W Provides a mechanism allowing add-in cards to distinguish their cards from one another. The 21150 provides a writable subsystem ID that can be initialized during POST. This register is only implemented in the 21150-AA. Reset to 0. Dword Bit Name R/W Description 15:8 Interrupt pin R Reads as 0 to indicate that the 21150 does not have an interrupt pin. Dword Bit Name R/W Description

16 Parity error response R/W

Controls the 21150’s response when a parity error is detected on the secondary interface. When 0—The 21150 does not assert s_perr_l, nor does it set the data parity reported bit in the secondary status register. The 21150 does not report address parity errors by asserting p_serr_l. When 1—The 21150 drives s_perr_l and conditionally sets the data parity reported bit in the secondary status register when a data parity error is detected on the secondary interface (see Section 7.0). Also must be set to 1 to allow p_serr_l assertion when address parity errors are detected on the secondary interface. Reset value: 0.

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17 SERR# forward enable R/W

Controls whether the 21150 asserts p_serr_l when it detects s_serr_l asserted. When 0—The 21150 does not drive p_serr_l in response to s_serr_l assertion. When 1—The 21150 asserts p_serr_l when s_serr_l is detected asserted (the primary SERR# driver enable bit must also be set). Reset value 0.

18 ISA enable R/W

Modifies the 21150’s response to ISA I/O addresses. Applies only to those addresses falling within the I/O base and limit address registers and within the first 64KB of PCI I/O space. When 0—The 21150 forwards all I/O transactions downstream that fall within the I/O base and limit address registers. When 1—The 21150 ignores primary bus I/O transactions within the I/O base and limit address registers and within the first 64KB of PCI I/O space that address the last 768 bytes in each 1KB block. Secondary bus I/O transactions are forwarded upstream if the address falls within the last 768 bytes in each 1KB block. Reset value: 0.

19 VGA enable R/W

Modifies the 21150’s response to VGA- compatible addresses. When 0—VGA transactions are ignored on the primary bus unless they fall within the I/O base and limit address registers and the ISA mode is When 1—The 21150 positively decodes and forwards the following transactions downstream, regardless of the values of the I/ O base and limit registers, ISA mode bit, or VGA snoop bit:

• Memory transactions addressing 000A0000h–000BFFFFh
• I/O transactions addressing: — p_ad<9:0> = 3B0h–3BBh and 3C0h–3DFh — p_ad<15:10> are not decoded. I/O and memory space enable bits must be set in the command register. The transactions listed here are ignored by the 21150 on the secondary bus. Reset value: 0. 20 Reserved R Reserved. Returns 0 when read. Dword Bit Name R/W Description

21 Master abort mode R/W

Controls the 21150’s behavior when a master abort termination occurs in response to a transaction initiated by the 21150 on either the primary or secondary PCI interface. When 0—The 21150 asserts TRDY# on the initiator bus for delayed transactions, and FFFF FFFFh for read transactions. For posted write transactions, p_serr_l is not asserted. When 1—The 21150 returns a target abort on the initiator bus for delayed transactions. For posted write transactions, the 21150 asserts p_serr_l if the SERR# enable bit is set in the command register. Reset value: 0.

22 Secondary bus reset R/W

Controls s_rst_l on the secondary interface. When 0—The 21150 deasserts s_rst_l. When 1—The 21150 asserts s_rst_l. When s_rst_l is asserted, the data buffers and the secondary interface are initialized back to reset conditions. The primary interface and configuration registers are not affected by the assertion of s_rst_l. Reset value: 0.

23 Fast back-to-back enable

Controls the ability of the 21150 to generate fast back-to-back transactions on the secondary interface. When 0—The 21150 does not generate fast back-to-back transactions on the secondary PCI bus. When 1—The 21150 is enabled to generate fast back-to-back transactions on the secondary PCI bus. Reset value: 0.

24 Primary master timeout R/W

Sets the maximum number of PCI clock cycles that the 21150 waits for an initiator on the primary bus to repeat a delayed transaction request. The counter starts once the delayed transaction completion is at the head of the queue. If the master has not repeated the transaction at least once before the counter expires, the 21150 discards the transaction from its queues. When 0—The primary master timeout value is 15 PCI clock cycles, or 0.983 ms for a 33-MHz bus. When 1—The value is 210 PCI clock cycles, or 30.7 ms for a 33-MHz bus. Reset value: 0. Dword Bit Name R/W Description

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15.1.32 Capability ID Register—Offset DCh

This section describes the capability ID register. (Implemented in the 21150-AB and later revisions only. In the 21150-AA, these registers are reserved.) Dword address = DCh Byte enable p_cbe_l<3:0> = xxx0b

25 Secondary master

Sets the maximum number of PCI clock cycles that the 21150 waits for an initiator on the secondary bus to repeat a delayed transaction request. The counter starts once the delayed transaction completion is at the head of the queue. If the master has not repeated the transaction at least once before the counter expires, the 21150 discards the transaction from its queues. When 0—The primary master timeout value is 215 PCI clock cycles, or 0.983 ms for a 33-MHz bus. When 1—The value is 210 PCI clock cycles, or 30.7 ms for a 33-MHz bus. Reset value: 0.

26 Master timeout status R/W1TC

This bit is set to 1 when either the primary master timeout counter or the secondary master timeout counter expires and a delayed transaction is discarded from the 21150’s queues. Write 1 to clear. Reset value: 0.

27 Master timeout SERR#

Controls assertion of p_serr_ during a master timeout. When 0—Signal p_serr_l is not asserted as a result of a master timeout. When 1—Signal p_serr_l is asserted when either the primary master timeout counter or the secondary master timeout counter expires and a delayed transaction is discarded from the 21150’s queues. The SERR# enable bit in the command register must also be set. Reset value: 0. 31:28 Reserved R Reserved. Returns 0 when read. Dword Bit Name R/W Description Dword Bit Name R/W Description 7:0 CAP_ID R/W Enhanced capabilities ID. Reads only as 01h to indicate that these are power management enhanced capability registers.

15.1.33 Next Item Ptr Register—Offset DDh

This section describes the next item ptr register. (Implemented in the 21150-AB and later revisions only. In the 21150-AA, these registers are reserved.) Dword address = DCh Byte enable p_cbe_l<3:0> = xx0xb

15.1.34 Power Management Capabilities Register—Offset DEh

This section describes the power management capabilities register. (Implemented in the 21150-AB and later revisions only. In the 21150-AA, these registers are reserved.) Dword address = DCh Byte enable p_cbe_l<3:0> = 00xxb Dword Bit Name R/W Description 15:8 NEXT_ITEM R Next item pointer. Reads as 0 to indicate that there are no other ECP registers. Dword Bit Name R/W Description 18:16 PM_VER R Power Management Revision. Reads as 001 to indicate that this device is compliant with Revision 1.0 of the PCI Power Management Interface Specification.

19 PME#Clock R

PME# Clock Required. Reads as 0 to indicate that this device does not support the PME# pin.

20 AUX R

Auxiliary Power Support. Reads as 0 to indicate that this device does not have PME# support or an auxiliary power source.

21 DSI R

Device Specific Initialization. Reads as 0 to indicate that this device does not have device- specific initialization requirements. 24:22 Reserved R Reserved. Read as 000b.

25 D1 R

D1 Power State Support. Reads as 0 to indicate that this device does not support the D1 power management state.

26 D2 R

D2 Power State Support. Reads as 0 to indicate that this device does not support the D2 power management state. 31:27 PME_SUP R PME# Support. Reads as 0 to indicate that this device does not support the PME# pin.

124 Preliminary Datasheet

15.1.35 Power Management Control and Status Register—Offset E0h

This section describes the power management control and status register. (Implemented in the 21150-AB and later revisions only. In the 21150-AA, these registers are reserved.) Dword address = E0h Byte enable p_cbe_l<3:0> = xx00b

15.1.36 PPB Support Extensions Registers—Offset E2h

This section describes the PPB support extensions registers. (Implemented in the 21150-AB and later revisions only. In the 21150-AA, these registers are reserved.) Dword address = E0h Byte enable p_cbe_l<3:0> = x0xxb Dword Bit Name R/W Description 1:0 PWR_STATE R Power State. Reflects the current power state of this device. If an unimplemented power state is written to this register, the 21150 completes the write transaction, ignores the write data, and does not change the value of this field. Writing a value of D0 when the previous state was D3 causes a chip reset to occur (without asserting s_rst_l).

• 0 0 b : D 0
• 01b: D1 (not implemented)
• 10b: D2 (not implemented)
• 11b: D3 Reset value: 00b. 7:2 Reserved R Reserved. Reads as 000000b. 8P M E _ E N R PME# Enable. Reads as 0 because the PME# pin is not implemented. 12:9 DATA_SEL R Data Select. Reads as 0000b because the data register is not implemented. 14:13 DATA_SCALE Data Scale. Reads as 00b because the data register is not implemented. 15 PME_STAT R PME Status. Reads as 0 because the PME# pin is not implemented. Dword Bit Name R/W Description 21:16 Reserved R Reserved. Read only as 000000b.

22 B2_B3 R

B2_B3 Support for D3hot. When the BPCC_En bit (bit 23) reads as 1, this bit reads as 1 to indicate that the secondary bus clock outputs will be stopped and driven low when this device is placed in D3hot. This bit is not defined when the BPCC_En bit reads as 0.

15.1.37 Data Register—Offset E3h

This section describes the data register. Dword address = E0h Byte enable p_cbe_l<3:0> = 0xxxb

15.2 Device-Specific Configuration Registers

This section provides a detailed description of the 21150 device-specific configuration registers. Each field has a separate description. Fields that have the same configuration address are selectable by turning on (driving low) the appropriate byte enable bits on p_cbe_l during the data phase. To select all fields of a configuration address, drive all byte enable bits low. All reserved fields and registers are read only and always return 0.

15.2.1 Chip Control Register—Offset 40h

This section describes the chip control register. Dword address = 40h Byte enable p_cbe_l<3:0> = xxx0b

23 BPCC_EN R

Bus Power/Clock Control Enable. When the bpcce pin is tied high, this bit reads as a 1 to indicate that the bus power/clock control mechanism is enabled, as described in B2_B3 (bit 22). When the bpcce pin is tied low, this bit reads as a 0 to indicate that the bus power/ clock control mechanism is disabled (secondary clocks are not disabled when this device is placed in D3hot.) Dword Bit Name R/W Description Dword Bit Name R/W Description 31:24 Data R Data register. This register is not implemented and reads 00h.

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15.2.2 Diagnostic Control Register—Offset 41h

This section describes the diagnostic control register. W1 TR indicates that writing 1 in this bit position causes a chip reset to occur. Writing 0 has no effect. Dword address = 40h Byte enable p_cbe_l<3:0> = xx0xb Dword Bit Name R/W Description 0 Reserved R Reserved. Returns 0 when read.

1 Memory write disconnect

Controls when the 21150, as a target, disconnects memory write transactions. When 0—The 21150 disconnects on queue full or on a 4KB boundary. When 1—The 21150 disconnects on a cache line boundary, as well as when the queue fills or on a 4KB boundary. Reset value: 0. 3:2 Reserved R Reserved. Returns 0 when read.

4 Secondary bus prefetch

Controls the 21150’s ability to prefetch during upstream memory read transactions. When 0—The 21150 prefetches and does not forward byte enable bits during memory read transactions. When 1—The 21150 requests only one Dword from the target during memory read transactions and forwards read byte enable bits. The 21150 returns a target disconnect to the requesting master on the first data transfer. Memory read line and memory read multiple transactions are still prefetchable. Reset value: 0.

5 Live insertion mode R/W

Enables hardware control of transaction forwarding in the 21150. When 0—Pin gpio<3> has no effect on the I/O, memory, and master enable bits. When 1—If the output enable control for gpio<3> is set to input only in the gpio output enable control register, this bit enables gpio<3> to mask the I/O enable, memory enable, and master enable bits to 0. These enable bits are masked when gpio<3> is driven high. When this occurs, the 21150 stops accepting I/O and memory transactions. Reset value: 0. 7:6 Reserved R Reserved. Returns 0 when read.

15.2.3 Arbiter Control Register—Offset 42h

This section describes the arbiter control register. Dword address = 40h Byte enablep_cbe_l<3:0> = 00xxb Dword Bit Name R/W Description

8 Chip reset R/W1TR

Chip and secondary bus reset control. When 1—Causes the 21150 to perform a chip reset. Data buffers, configuration registers, and both the primary and secondary interfaces are reset to their initial state. The 21150 clears this bit once chip reset is complete. The 21150 can then be reconfigured. Secondary bus reset s_rst_l is asserted and the secondary reset bit in the bridge control register is set when this bit is set. The secondary reset bit in the bridge control register must be cleared in order to deassert s_rst_l. 10:9 Test mode R/W Controls the testability of the 21150’s internal counters. These bits are used for chip test only. The value of these bits controls which bytes of the counters are exercised:

• 00b = Normal functionality—all bits are exercised.
• 01b = Byte 1 is exercised.
• 10b = Byte 2 is exercised.
• 11b = Byte 0 is exercised. Reset value: 00b. 15:11 Reserved R Reserved. Returns 0 when read. Dword Bit Name R/W Description 25:16 Arbiter control R/W Each bit controls whether a secondary bus master is assigned to the high priority arbiter group or the low priority arbiter group. Bits <24:16> correspond to request inputs s_req_l<8:0>, respectively. Bit <25> corresponds to the 21150 as a secondary bus master. When 0—Indicates that the master belongs to the low priority group. When 1—Indicates that the master belongs to the high priority group. Reset value: 10 0000 0000b. 31:26 Reserved R Reserved. Returns 0 when read.

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15.2.4 p_serr_l Event Disable Register—Offset 64h This section describes the p_serr_l event disable register. Dword address = 64h Byte enable p_cbe_l<3:0> = xxx0b Dword Bit Name R/W Description 0 Reserved R Reserved. Returns 0 when read.

1 Posted write parity error R/W

Controls the 21150’s ability to assert p_serr_l when a data parity error is detected on the target bus during a posted write transaction. When 0—Signal p_serr_l is asserted if this event occurs and the SERR# enable bit in the command register is set. When 1—Signal p_serr_l is not asserted if this event occurs. Reset value: 0.

2 Posted write nondelivery R/W

Controls the 21150’s ability to assert p_serr_l when it is unable to deliver posted write data after 224 attempts. When 0—Signal p_serr_l is asserted if this event occurs and the SERR# enable bit in the command register is set. When 1—Signal p_serr_l is not asserted if this event occurs. Reset value: 0.

3 Target abort during

Controls the 21150’s ability to assert p_serr_l when it receives a target abort when attempting to deliver posted write data. When 0—Signal p_serr_l is asserted if this event occurs and the SERR# enable bit in the command register is set. When 1—Signal p_serr_l is not asserted if this event occurs. Reset value: 0.

4 Master abort on posted

Controls the 21150’s ability to assert p_serr_l when it receives a master abort when attempting to deliver posted write data. When 0—Signal p_serr_l is asserted if this event occurs and the SERR# enable bit in the command register is set. When 1—Signal p_serr_l is not asserted if this event occurs. Reset value: 0.

15.2.5 gpio Output Data Register—Offset 65h This section describes the gpio output data register. Dword address = 64h Byte enable p_cbe_l<3:0> = xx0xb

5 Delayed write nondelivery R/W

Controls the 21150’s ability to assert p_serr_l when it is unable to deliver delayed write data after 224 attempts. When 0—Signal p_serr_l is asserted if this event occurs and the SERR# enable bit in the command register is set. When 1—Signal p_serr_l is not asserted if this event occurs. Reset value: 0.

6 Delayed read—no data

Controls the 21150’s ability to assert p_serr_l when it is unable to transfer any read data from the target after 224 attempts. When 0—Signal p_serr_l is asserted if this event occurs and the SERR# enable bit in the command register is set. When 1—Signal p_serr_l is not asserted if this event occurs. Reset value: 0. 7 Reserved R Reserved. Returns 0 when read. Dword Bit Name R/W Description Dword Bit Name R/W Description 11:8 GPIO output write-1-to- clear R/W1TC The gpio<3:0> pin output data write-1-to-clear. Writing 1 to any of these bits drives the corresponding bit low on the gpio<3:0> bus if it is programmed as bidirectional. Data is driven on the PCI clock cycle following completion of the configuration write to this register. Bit positions corresponding to gpio pins that are programmed as input only are not driven. Writing 0 to these bits has no effect. When read, reflects the last value written. Reset value: 0. 15:12 GPIO output write-1-to- set R/W1TC The gpio<3:0> pin output data write-1-to-set. Writing 1 to any of these bits drives the corresponding bit high on the gpio<3:0> bus if it is programmed as bidirectional. Data is driven on the PCI clock cycle following completion of the configuration write to this register. Bit positions corresponding to gpio pins that are programmed as input only are not driven. Writing 0 to these bits has no effect. When read, reflects the last value written. Reset value: 0.

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15.2.6 gpio Output Enable Control Register—Offset 66h This section describes the gpio output enable control register. Dword address = 64h Byte enable p_cbe_l<3:0> = x0xxb 15.2.7 gpio Input Data Register—Offset 67h This section describes the gpio input data register. Dword address = 64h Byte enable p_cbe_l<3:0> = 0xxxb

15.2.8 Secondary Clock Control Register—Offset 68h

This section describes the secondary clock control register. Dword address = 68h Byte enable p_cbe_l<3:0> = xx00b Dword Bit Name R/W Description 19:16 GPIO output enable write- 1-to-clear R/W1TC The gpio<3:0>output enable control write-1-to- clear. Writing 1 to any of these bits configures the corresponding gpio<3:0> pin as an input only; that is, the output driver is tristated. Writing 0 to this register has no effect. When read, reflects the last value written. Reset value: 0 (all pins are input only). 23:20 GPIO output enable write- 1-to-set R/W1TS The gpio<3:0> output enable control write-1-to- set. Writing 1 to any of these bits configures the corresponding gpio<3:0> pin as bidirectional, that is, enables the output driver and drives the value set in the output data register (65h). Writing 0 to this register has no effect. When read, reflects the last value written. Reset value: 0 (all pins are input only). Dword Bit Name R/W Description 27:24 Reserved R Reserved. Returns 0 when read. 31:28 GPIO input R This read-only register reads the state of the gpio<3:0> pins. This state is updated on the PCI clock cycle following a change in the gpio pins.

Dword Bit Name R/W Description 1:0 Slot 0 clock disable R/W If either bit is 0: Signal s_clk_o<0> is enabled. When both bits are 1—Signal s_clk_o<0> is disabled and driven low. Upon secondary bus reset, this bit is initialized by shifting in a serial data stream. These bits are assigned to correspond to the PRSNT# pins for slot 0. 3:2 Slot 1 clock disable R/W If either bit is 0—Signal s_clk_o<1> is enabled. When both bits are 1—Signal s_clk_o<1> is disabled and driven low. Upon secondary bus reset, this bit is initialized by shifting in a serial data stream. These bits are assigned to correspond to the PRSNT# pins for slot 1. 5:4 Slot 2 clock disable R/W If either bit is 0—Signal s_clk_o<2> is enabled. When both bits are 1—Signal s_clk_o<2> is disabled and driven low. Upon secondary bus reset, this bit is initialized by shifting in a serial data stream. These bits are assigned to correspond to the PRSNT# pins for slot 2. 7:6 Slot 3 clock disable R/W If either bit is 0—Signal s_clk_o<3> is enabled. When both bits are 1—Signal s_clk_o<3> is disabled and driven low. Upon secondary bus reset, this bit is initialized by shifting in a serial data stream. These bits are assigned to correspond to the PRSNT# pins for slot 3.

8 Device 1 clock disable R/W

When 0—Signal s_clk_o<4> is enabled. When 1—Signal s_clk_o<4> is disabled and driven low. Upon secondary bus reset, this bit is initialized by shifting in a serial data stream.

9 Device 2 clock disable R/W

When 0—Signal s_clk_o<5> is enabled. When 1—Signal s_clk_o<5> is disabled and driven low. Upon secondary bus reset, this bit is initialized by shifting in a serial data stream.

10 Device 3 clock disable R/W

When 0—Signal s_clk_o<6> is enabled. When 1—Signal s_clk_o<6> is disabled and driven low. Upon secondary bus reset, this bit is initialized by shifting in a serial data stream.

11 Device 4 clock disable R/W

When 0—Signal s_clk_o<7> is enabled. When 1—Signal s_clk_o<7> is disabled and driven low. Upon secondary bus reset, this bit is initialized by shifting in a serial data stream.

12 Device 5 clock disable R/W

When 0—Signal s_clk_o<8> is enabled. When 1—Signal s_clk_o<8> is disabled and driven low. Upon secondary bus reset, this bit is initialized by shifting in a serial data stream.

132 Preliminary Datasheet

15.2.9 p_serr_l Status Register—Offset 6Ah This section describes the p_serr_l status register. This status register indicates the reason for the 21150’s assertion of p_serr_l. Dword address = 68h Byte enable p_cbe_l<3:0> = x0xxb

13 The 21150 clock disable R/W

When 1—Signal s_clk_o<9> is disabled and driven low. When 0—Signal s_clk_o<9> is enabled. Upon secondary bus reset, this bit is initialized by shifting in a serial data stream. This bit is assigned to correspond to the 21150 secondary clock input, s_clk. 15:14 Reserved R Reserved. Returns 0 when read. Dword Bit Name R/W Description Dword Bit Name R/W Description

16 Address parity error R/W1TC

When 1—Signal p_serr_l was asserted because an address parity error was detected on either the primary or secondary PCI bus. Reset value: 0.

17 Posted write data parity

When 1—Signal p_serr_l was asserted because a posted write data parity error was detected on the target bus. Reset value: 0.

18 Posted write nondelivery R/W1TC

When 1—Signal p_serr_l was asserted because the 21150 was unable to deliver posted write data to the target after 224 attempts. Reset value: 0.

19 Target abort during

When 1—Signal p_serr_l was asserted because the 21150 received a target abort when delivering posted write data. Reset value: 0.

20 Master abort during

When 1—Signal p_serr_l was asserted because the 21150 received a master abort when attempting to deliver posted write data. Reset value: 0.

15.3 Configuration Register Values After Reset

listed and are always read as 0.

21 Delayed write nondelivery R/W1TC

delayed write data after 224attempts.

22 Delayed read—no data

data from the target after 224 attempts.

23 Delayed transaction

expired on the initiator’s PCI bus. Table 35. Configuration Register Values After Reset (Sheet 1 of 2)

134 Preliminary Datasheet

1. Dependent on revision of device.
2. The value of this register is dependent upon the serial clock disable shift function that occurs during
3. Reserved in the 21150-AA.

Table 35. Configuration Register Values After Reset (Sheet 2 of 2)

16.0 JTAG Test Port

16.1 Overview

• A 5-wire test access port
• A test access port controller
• An instruction register
• A bypass register
• A boundary-scan register Note: The JTAG test access port is to be used only while the 21150 is not operating.

16.2 JTAG Signal Pins

This chapter describes the JTAG pins listed in Table 36.

16.3 Test Access Port Controller

received through the tms line. test features. After entry into a state, test feature operations are initiated on the rising edge of tck. Table 36. JTAG Pins

136 Preliminary Datasheet

16.4 Instruction Register

The 5-bit instruction register selects the test modes and features.The instruction register bits are interpreted as instructions, as shown in Table 37. The instructions select and control the operation of the boundary-scan and bypass registers. Table 37 describes the 21150’s instructions. The instruction register is loaded through the tdi pin. The instruction register has a shift-in stage from which the instruction is then loaded in parallel.

16.5 Bypass Register

The bypass register is a 1-bit shift register that provides a means for effectively bypassing the JTAG test logic through a single-bit serial connection through the chip from tdi to tdo. At board- level testing, this helps reduce overall length of the scan ring.

16.6 Boundary-Scan Register

The boundary-scan register is a single-shift register-based path formed by boundary-scan cells placed at the chip’s signal pins. The register is accessed through the JTAG port’s tdi and tdo pins. Table 37. JTAG Instruction Registers

Contents

Instruction Name (Test Mode or State) Test Register Selected Operation

00000 EXTEST Boundary-scan

External test (drives pins from the boundary-scan register)

00001 SAMPLE Boundary-scan Samples I/O

00010 BSROSC Boundary-scan Ring oscillates the

00011 BSRDLY Boundary-scan

00100 CLAMP Bypass

bypass register for shifts

00101 HIGHZ Bypass

00110--11111 BYPASS Bypass Selects the bypass register for shifts

16.6.1 Boundary-Scan Register Cells

• Input-only pins—The boundary-scan cell is basically a 1-bit shift register. The cell supports sample and shift functions.
• Output-only pins—The boundary-scan cell comprises a 1-bit shift register and an output multiplexer. The cell supports the sample, shift, and drive output functions.
• Bidirectional pins—The boundary-scan cell is identical to the output-only pin cell, but it captures test data from the incoming data line. The cell supports sample, shift, drive output, and hold output functions. It is used at all I/O pins. 16.6.2 21150 Boundary-Scan Order Table 38 lists the boundary-scan register order and the group disable controls. The group disable control either enables or tristates its corresponding group of bidirectional drivers. When the value of a group disable control bit is 0, the output driver is enabled. When the value is 1, the driver is tristated. There are nine groups of bidirectional drivers, and therefore nine group disable control bits. The Group Disable Number column in Table 38 shows which group disable bit controls the corresponding output driver. Group disable bits do not affect input-only pins, so those pins have a blank rather than a group number in the Group Disable Number column. The group disable control wire can control pins on either side of where the group disable boundary-scan register is placed. The group disable boundary-scan registers have a boundary-scan register number entry, but they do not have a corresponding pin number or signal name. Data shifts from tdi into the most significant bit of the boundary-scan register, and from the least significant bit of the boundary-scan register out to tdo.

Table 38. Boundary-Scan Order (Sheet 1 of 5)

138 Preliminary Datasheet

Table 38. Boundary-Scan Order (Sheet 2 of 5)

Table 38. Boundary-Scan Order (Sheet 3 of 5)

140 Preliminary Datasheet

Table 38. Boundary-Scan Order (Sheet 4 of 5)

16.7 Initialization

Table 38. Boundary-Scan Order (Sheet 5 of 5)

17.0 Electrical Specifications

• PCI electrical conformance
• Absolute maximum ratings
• dc specifications
• ac timing specifications

17.1 PCI Electrical Specification Conformance

17.2 Absolute Maximum Ratings

Table 39. Absolute Maximum Ratings Table 40. Functional Operating Range

144 Preliminary Datasheet

17.3 DC Specifications

the chip (chip sourcing) are denoted as negative (–) current.

17.4 AC Timing Specifications

1. Guarantees meeting the specification for the 5-V signaling environment.
2. For 3.3-V signaling environment.
3. For 5-V signaling environment.
4. Input leakage currents include high-Z output leakage for all bidirectional buffers with tristate outputs.

• Clock timing specifications
• PCI signal timing specifications
• Reset timing specifications
• gpio timing specifications
• JTAG timing specifications

Table 41. DC Parameters

17.4.1 Clock Timing Specifications

when tested within the functional operating range of Table 40. Figure 23. PCI Clock Signal AC Parameter Measurements Table 42. 33 MHz PCI Clock Signal AC Parameters (Sheet 1 of 2)

146 Preliminary Datasheet

17.4.2 PCI Signal Timing Specifications

1. 0.2 Vcc to 0.6 Vcc2. Measured with 30-pF lumped load
2. 0.2 Vcc to 0.6 Vcc2. To be determined
3. Measured with 30-pF lumped load

Figure 24, Table 44, and Table 45 show the PCI signal timing specifications. Table 43. 66 MHz PCI Clock Signal AC Parameters Table 42. 33 MHz PCI Clock Signal AC Parameters (Sheet 2 of 2)

1. All primary interface signals are synchronized to p_clk. All secondary interface signals are synchronized
2. Point-to-point signals are p_req_l, s_req_l<8:0>, p_gnt_l, and s_gnt_l<8:0>. Bused signals are p_ad,

Figure 24. PCI Signal Timing Measurement Conditions Table 44. 33 MHz PCI Signal Timing

148 Preliminary Datasheet

1. All primary interface signals are synchronized to p_clk. All secondary interface signals are synchronized
2. Point-to-point signals are p_req_l, s_req_l<8:0>, p_gnt_l, and s_gnt_l<8:0>. Bused signals are p_ad,

17.4.3 Reset Timing Specifications

Table 46 shows the reset timing specifications for p_rst_l and s_rst_l. Table 45. 66 MHz PCI Signal Timing Table 46. Reset Timing Specifications (Sheet 1 of 2)

1. Applies to rising (deasserting) edge only.

Table 47 and Table 48 show the gpio timing specifications. See also Figure 24. Table 46. Reset Timing Specifications (Sheet 2 of 2) Table 47. 33 MHz gpio Timing Specifications

150 Preliminary Datasheet

17.4.5 JTAG Timing Specifications

Table 49 shows the JTAG timing specifications. Table 48. 66 MHz gpio Timing Specifications Table 49. JTAG Timing Specifications (Sheet 1 of 2)

1. Measured between 0.8 V and 2.0 V.
2. Measured between 2.0 V and 0.8 V.

Table 49. JTAG Timing Specifications (Sheet 2 of 2)

18.0 Mechanical Specifications

Figure 25. 208-Pin PQFP Package

154 Preliminary Datasheet

Table 50 lists the 208-pin package dimensions in millimeters. 1 The value for this measurement is for reference only. Table 50. 208-Pin PQFP Package Dimensions

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