21143

21143 INTEL | Alldatasheet

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Technical content

Datasheet sections

• 1.1 General Description
• 1.2 Microarchitecture
• 2.0 PINOUT
• 2.1 Signal Reference Tables
• 2.2 Signal Reference Tables
• 2.3 Pin Tables
• 2.4 Signal Grouping by Function
• 3.0 ELECTRICAL AND ENVIRONMENTAL SPECIFICATIONS
• 3.1 Voltage Limit Ratings
• 3.2 Temperature Limit Ratings
• 3.3 Power Specifications
• 3.4 PCI Bus and CardBus Electrical Parameters
• 3.4.1 PCI and CardBus I/O Voltage Specifications
• 3.4.2 System Bus Reset
• 3.4.3 PCI and CardBus Clock Specifications
• 3.4.4 Other PCI and CardBus Signals
• 3.5 AUI and Twisted-Pair DC Specifications
• 3.6 Serial Interface Attachment Specifications
• 3.6.1 Serial Clock Timing
• 3.6.2 Internal SIA Mode AUI Timing—Transmit
• 3.6.3 Internal SIA Mode AUI Timing—Receive
• 3.6.4 Internal SIA Mode AUI Timing—Collision
• 3.6.5 Internal SIA Mode 10BASE-T Interface Timing—Transmit
• 3.6.6 Internal SIA Mode 10BASE-T Interface Timing—Receive
• 3.6.7 Internal SIA Mode 10BASE-T Interface Timing—Idle Link Pulse
• 3.7 MII Interface Specifications
• 3.8 MII/SYM Port Timing
• 3.8.1 MII/SYM 10/100-Mb/s and 10-Mb/s Timing—Transmit
• 3.8.2 MII/SYM 10/100-Mb/s Timing—Receive
• 3.8.3 SYM 10/100-Mb/s Timing—Signal Detect
• 3.8.4 MII 10/100-Mb/s Timing—Receive Error
• 3.8.5 MII 10/100-Mb/s Timing—Carrier Sense and Collision
• 3.9 Boot ROM and Serial ROM Port Specification
• 3.10 Boot ROM Port Timing
• 3.10.1 Boot ROM Read Timing
• 3.10.2 Boot ROM Write Timing
• 3.11 Serial ROM Port Timing
• 3.12 External Register Timing
• 3.13 Joint Test Action Group—Test Access Port
• 3.13.1 JTAG DC Specifications
• 3.13.2 JTAG Boundary-Scan Timing
• 4.0 MECHANICAL SPECIFICATIONS

21143 PCI/CardBus 10/100 Ethernet LAN

■ Fully compliant with Revision 2.1 of the PCI Local Bus Specification and with Revision 1.0 of the PCI Bus Power Management Interface Specification. ■ Fully compliant with Revision 1.0 of the Advanced Configuration and Power Interface (ACPI) Specification and with Revision 1.0 of the Network Device Class Power Management Specification, under the OnNow Architecture for Microsoft’s PC 97 Hardware Design Guide and PC 98 System Design Guide. ■ Supports IEEE 802.3 with full Auto-Negotiation algorithm of full-duplex and half-duplex operation for 10 Mb/s and 100 Mb/s (NWAY). ■ Supports IEEE 802.3 and ANSI 8802-3 Ethernet standards. ■ Supports direct memory access (DMA) and has direct interface to both the CardBus* and PCI local bus. ■ Provides glueless 32-bit PCI bus master interface. ■ Contains large independent receive and transmit FIFOs. ■ Contains internal PCS and scrambler/ descrambler for MII/SYM interface for 100BASE-TX. ■ Contains onchip integrated AUI port and a 10BASE-T transceiver. ■ Supports autodetection between 10BASE-T, AUI, and MII/SYM ports. ■ Provides an upgradable boot ROM interface up to 256KB. ■ Supports remote wake-up-LAN and Magic Packet* with the SecureON™ password option. ■ Supports PCI/CardBus clock speed frequency from dc to 33 MHz; network operation with PCI clock from 20 MHz to 33 MHz. ■ Implements low-power management with two power-saving modes (sleep and snooze). ■ Implements low-power, 3.3-V CMOS technology. Order Number: 278073-001 November 1998 Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 21143 PCI/CardBus 10/100 Ethernet LAN Controller may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners.

1.0 21143 Overview The Intel 21143 PCI/CardBus* 10/100-Mb/s Ethernet LAN Controller (21143) supports the peripheral component interconnect (PCI) bus or CardBus. It provides a direct interface connection to the PCI bus and adapts easily to the CardBus and most other standard buses. The 21143 software interface and data structures are optimized to minimize the host CPU load and to allow for maximum flexibility in the buffer descriptor management. The 21143 contains large onchip FIFOs, so no additional onboard memory is required. The 21143 also provides an upgradable boot ROM interface. In addition to the features listed on the title pages, the following features are also supported by the 21143: PCI and CardBus Features:

• Supports PCI and CardBus interfaces.
• Supports PCI/CardBus clock control through clkrun.
• Supports CardBus cstschg pin and Status Changed registers.
• Supports automatic loading of subvendor ID and CardBus card information structure (CIS) pointer from serial ROM to configuration registers.
• Supports storage of CardBus card information structure (CIS) in the serial ROM or the expansion ROM.
• Supports the advanced PCI/CardBus read multiple, read line, and write and invalidate commands.
• Supports an unlimited PCI/CardBus burst. Host Interface Features:
• Includes a powerful onchip direct memory access (DMA) with programmable burst size, providing low CPU utilization.
• Supports early interrupt on transmit and receive.
• Supports interrupt mitigation on transmit and receive.
• Supports big or little endian byte ordering for buffers and descriptors.
• Implements unique, patented intelligent arbitration between DMA channels to minimize underflow and overflow.
• Contains large independent receive and transmit FIFOs. Network Side Features:
• Supports three network ports: 10BASE-T (10 Mb/s), AUI (10 Mb/s), and MII/SYM (10/100 Mb/s).
• Contains a variety of flexible address filtering modes.
• Implements signal-detect filtering to avoid false detection of link with 100BASE-TX symbol interfaces.
• Enables automatic detection and correction of 10BASE-T receive polarity.
• Supports autodetection between 10BASE-T, AUI, and MII/SYM ports.
• Offers a unique, patented solution to Ethernet capture-effect problem.

2 Preliminary Datasheet

• Supports full-duplex operation on both MII/SYM and 10BASE-T ports.
• Provides internal and external loopback capability on all network ports.
• Supports IEEE 802.3 and ANSI 8802-3 Ethernet standards. Other Features:
• Provides MicroWire* interface for serial ROM (1K and 4K EEPROM).
• Provides LED indications for various network activity.
• Implements test-access port (JTAG-compatible) with boundary-scan pins.
• Contains a 4-bit, general-purpose programmable register and corresponding I/O pins with the ability to generate interrupts from two general-purpose pins.

1.1 General Description

The 21143 is an Ethernet LAN controller for both 100-Mb/s and 10-Mb/s data rates, which provides a direct interface to the peripheral component interconnect (PCI) local bus or the CardBus. The 21143 interfaces to the host processor by using onchip command and status registers (CSRs) and a shared host memory area, set up mainly during initialization. This minimizes processor involvement in the 21143 operation during normal reception and transmission. The 21143 is optimized for low power PCI/CardBus based systems and supports two types of power-management mechanisms. The main mechanism is based upon the OnNow architecture, which is required for PC 97 and PC 98. The alternative mechanism is based upon the older remote wake-up-LAN mechanism. Large FIFOs allow the 21143 to efficiently operate in systems with longer latency periods. Bus traffic is also minimized by filtering out received runt frames and by automatically retransmitting collided frames without a repeated fetch from the host memory. The 21143 provides three network ports: a 10BASE-T 10-Mb/s port, an attachment unit interface (AUI) 10-Mb/s port, and a media-independent/symbol interface (MII/SYM) 10/100-Mb/s port. The 10BASE-T port provides a direct Ethernet connection to the twisted-pair (TP) interface. The AUI port provides a direct Ethernet connection to the AUI. The MII/SYM port supports two operational modes:

• MII mode—A full implementation of the MII standard
• SYM mode—Symbol interface to an external 100-Mb/s front-end decoder (ENDEC). In this mode the 21143 uses an onchip physical coding sublayer (PCS) and a scrambler/descrambler circuit to enable a low-cost 100BASE-T implementation. The 21143 is capable of functioning in a full-duplex environment for the MII/SYM and 10BASE-T ports. The 21143 provides an upgradable boot ROM interface.

1.2 Microarchitecture

The following list describes the 21143 hardware components, and Figure 1 shows a block diagram of the 21143:

• PCI/CardBus interface—Includes all interface functions to the PCI and CardBus bus; handles all interconnect control signals; and executes DMA and I/O transactions
• Boot ROM port—Provides an interface to perform read and write operations to the boot ROM; supports accesses to bytes or longwords (32-bit); and provides the ability to connect an external 8-bit register to the boot ROM port
• Serial ROM port—Provides a direct interface to a MicroWire ROM for storage of the Ethernet address and system parameters
• General-purpose register—Enables software use for input or output functions and LEDs
• DMA—Contains independent receive and transmit controllers; handles data transfers between CPU memory and onchip memory
• FIFOs—Contains independent FIFOs for receive and transmit; supports automatic packet deletion on receive (runt packets or after a collision) and packet retransmission after a collision on transmit
• TxM—Handles all CSMA/CD 1 MAC 2 transmit operations, and transfers data from transmit FIFO to the ENDEC for transmission
• RxM—Handles all CSMA/CD MAC receive operations, and transfers the network data from the ENDEC to the receive FIFO
• SIA interface—Performs 10-Mb/s physical layer network operations; implements the AUI and 10BASE-T functions, including the Manchester encoder and decoder functions
• NWAY—Implements the IEEE 802.3 Auto-Negotiation algorithm
• Physical coding sublayer—Implements the encoding and decoding sublayer of the 100BASE-TX (CAT5) specification, including the squelch feature
• Scrambler/descrambler—Implements the twisted-pair physical layer medium dependent (TP-PMD) scrambler/descrambler scheme for 100BASE-TX
• Three network interfaces—An AUI interface, a 10BASE-T interface, and an MII/SYM interface provide a full MII signal interface and direct interface to the 100-Mb/s ENDEC for CAT5
• Wake-up-controller—Enables power-management control compliant with the ACPI and remote power-up capabilities using the remote wake-up-LAN mechanism 1. Carrier-sense multiple access with collision detection. 2. Media access control.

4 Preliminary Datasheet

Figure 1. 21143 Block Diagram

10 Mb/s 10 Mb/s

2.0 Pinout

and their respective signal definitions. Table 1. Index to Pinout Tables

6 Preliminary Datasheet

Figure 2. 21143 Pinout Diagram (Top View)

2.1 Signal Reference Tables

Table 2 provides an alphabetical list of the 21143 logic names and their pin numbers. Table 3 provides a list of the 21143 power pin numbers.

8 Preliminary Datasheet

Table 2. Logic Signals (Sheet 1 of 2)

2.2 Signal Reference Tables

The functional grouping of each pin is listed in Section 2.4.

• Address phase Address and appropriate bus commands are driven during this cycle.
• Data phase Data and the appropriate byte enable codes are driven during this cycle.
• _l All pin names with the _l suffix are asserted low. The following pins in Table 4 have an internal pull-up: tms tdi br_ce_l sr_do mii/sym_tclk Pin sr_cs has an internal pull-down. Table 4 uses the following abbreviations: I = Input O = Output I/O = Input/output O/D = Open drain P = Power tp_td+ + 7 trdy_l 52 vcap_h 110 xtal1 106 xtal2 105 ——

Table 3. Power Pins Table 2. Logic Signals (Sheet 2 of 2)

10 Preliminary Datasheet

Table 4. Functional Description of 21143 Signals (Sheet 1 of 6) transaction, the address bits contain a physical address (32 bits). aui_cd– I 138 Attachment unit interface receive collision differential negative data. aui_cd+ I 137 Attachment unit interface receive collision differential positive data. aui_rd– I 140 Attachment unit interface receive differential negative data. aui_rd+ I 139 Attachment unit interface receive differential positive data. aui_td– O 143 Attachment unit interface transmit differential negative data. aui_td+ O 142 Attachment unit interface transmit differential positive data. connected to a pull-down resistor. address and control lines by the two external latches. cycle. During the data cycle, bits 7 through 0 contain data. br_ce_l O 87 Boot ROM or external register chip enable. command and byte enable are multiplexed on the same PCI pins. 0 applies to byte 0, and bit 3 applies to byte 3. requesting normal clock operation to be maintained or restored.

Device select is asserted by the target of the current bus access. indicate that the next data phase is the final data phase transaction.

• A general-purpose pin that performs either input or output functions. This general-purpose pin can provide an interrupt when functioning as an input.
• A control pin that provides an AUI (10BASE5) or BNC (10BASE2) select line. This control pin is mainly used to enable the external BNC transceiver in 10BASE2 mode. When set, the 10BASE5 mode is selected. When reset, the 10BASE2 mode is selected. NOTE: This control pin is internally forced to the aui_bnc function when the 21143 is in remote wake-up-LAN mode. gep<1>/activ I/O 101 This pin can be configured by software to be:
• A general-purpose pin that performs either input or output functions. This general-purpose pin can provide an interrupt when functioning as an input.
• A status pin that provides an LED that indicates either receive or transmit activity. gep<2>/ rcv_match/ wake I/O 102 This pin can be configured by software to be:
• A general-purpose pin that performs either input or output functions.
• A status pin that provides an LED that indicates a receive packet has passed address recognition. If the PME_Enable bit (Func0_HwOptions<3>) in the serial ROM is set, this pin is forced to function as a wake-up event pin that can be connected to pin pme# of the PCI connector or pin cstschg of the CardBus connector. When the 21143 is in remote wake-up-LAN mode, this pin is used as an indicator that a Magic Packet* has been successfully detected. When this pin is in a wake function, bit MiscHwOptions<1> in the serial ROM determines the polarity. The PME function takes precedence over the Magic Packet indication function. gep<3>/link I/O 103 This pin can be configured by software to be:
• A general-purpose pin that performs either input or output functions. When configured as an input pin in OnNow mode, this pin functions as link status. When used with an MII PHY device, this pin should be connected to the MII PHY link indication pin (the 21143 interprets link-pass when this pin is high). This pin should not be left unconnected if it is configured as an input in D1, D2 or D3 power states.
• A status pin that provides an LED to indicate: –Network link integrity state for 10BASE-T or 100BASE-TX if Func1_Hw_Options<8> is cleared in the SROM. –Both network activity and network link integrity state if Func1_Hw_Options<8> is set in the SROM.

Table 4. Functional Description of 21143 Signals (Sheet 2 of 6)

12 Preliminary Datasheet

configuration cycle to the 21143. into the appropriate CSR5 bit. support edge-triggered systems. iref I 108 Current reference input for the analog phase-locked loop logic. current data phase of the transaction. until both irdy_l and trdy_l are asserted together. operations to indicate that valid data is present on the 32-bit ad lines. device detects a collision, it asserts this pin. (PMD) device and should be synchronized to the sym_rclk signal. the PHY when the media is active. controlled by an external PMD device. packet. This signal should be synchronized with the mii_rclk signal. status between the PHY and the 21143. equals 0 when the 21143 is in 10BASE-T/AUI mode (CSR6<18>=0). Table 4. Functional Description of 21143 Signals (Sheet 3 of 6)

external PMD device. This clock should always be active. the rising edge of the mii_tclk signal. port to an external PHY device. Parity error asserts when a data parity error is detected. a master-read or a slave-write operation. bit in CSR5, the 21143 continues its operation. that it wants to use the bus. output pins are put into tristate and all PCI O/D signals are floated. clocks after the failing address. the 21143 to the serial ROM device. the serial ROM device to the 21143. Table 4. Functional Description of 21143 Signals (Sheet 4 of 6)

14 Preliminary Datasheet

master to stop the current transaction. master, either to disconnect, retry, or abort. 21143 during JTAG test operations. If the JTAG port is unused, this pin should be connected to vss. 21143 during JTAG test operations. during JTAG test operations. interference on the twisted-pair medium. interference on the twisted-pair medium. current data phase of the transaction. target is prepared to accept data. vcap_h I 110 Capacitor input for analog phase-locked loop logic. connected to the main power. vddac P 109, 111 Supplies +3.3-V input for analog phase-locked loop logic. Supplies +5-V or +3.3-V reference for clamp logic. Table 4. Functional Description of 21143 Signals (Sheet 5 of 6)

2.3 Pin Tables

• Table 5 lists the input pins.
• Table 6 lists the output pins.
• Table 7 lists the input/output pins.
• Table 8 lists the open drain pins. xtal2 O 105 Crystal feedback output pin used for crystal connections only. If this pin is unused, then it should be unconnected.

Table 4. Functional Description of 21143 Signals (Sheet 6 of 6) Table 5. Input Pins Table 6. Output Pins

16 Preliminary Datasheet

Table 7. Input/Output Pins a. The active level is controlled by bit MiscHwOptions<1> (PME_STSCHG) in the serial ROM. Table 8. Open Drain Pins

2.4 Signal Grouping by Function

Table 9 lists the signals according to their interface function. Table 9. Signal Functions (Sheet 1 of 2)

18 Preliminary Datasheet

Table 9. Signal Functions (Sheet 2 of 2)

3.0 Electrical and Environmental Specifications

This section contains the electrical and environmental specifications for the 21143. the reliability of the 21143.

3.1 Voltage Limit Ratings

Table 10 lists the voltage limit ratings.

3.2 Temperature Limit Ratings

Table 11 lists the temperature limit ratings. Table 10. Voltage Limit Ratings

1. In the 3.3-V signaling environment, vdd_clamp must not be greater than vdd + 0.3 V.

Table 11. Temperature Limit Ratings

20 Preliminary Datasheet

3.3 Power Specifications

network data rate of 10/100 Mb/s for MII for legacy power-saving modes. and a network data rate of 10/100 Mb/s for ACPI modes.

3.4 PCI Bus and CardBus Electrical Parameters

This section describes the PCI Bus and CardBus characteristics for the 21143. Table 12. Legacy Power-Saving Modes Specification Table 13. ACPI Modes Power Specification

3.4.1 PCI and CardBus I/O Voltage Specifications

The 21143 meets the I/O voltage specifications listed in Table 14 and Table 15. Table 14. I/O Voltage Specifications for 5.0-V Levels

1. Input leakage currents include high-impedance output leakage for all bidirectional buffers with tristate outputs.
2. Signals without pull-up resistors must have 3-mA low output current. Signals requiring pull-up resistors (including

frame_l, trdy_l, irdy_l, devsel_l, stop_l, serr_l, and perr_l) must have 6 mA.

1. Parameter design guarantee.

Table 15. I/O Voltage Specifications for 3.3-V Levels

1. Input leakage currents include high-impedance output leakage for all bidirectional buffers with tristate outputs.
2. Parameter design guarantee.

22 Preliminary Datasheet

3.4.2 System Bus Reset

characteristics, and Table 16 lists the reset signal limits.

3.4.3 PCI and CardBus Clock Specifications

Figure 3. Reset Timing Diagram Table 16. Reset Timing Parameters

1. The PCI and CardBus clock frequency is from dc to 33 MHz; network operational with the PCI or CardBus clock from 20 MHz to

Figure 4. PCI and CardBus Clock Specification Timing Diagram Table 17. PCI and CardBus Clock Timing Specifications

1. Rise and fall times are specified in terms of the edge rate measured in V/ns. Parameter design guarantee.

24 Preliminary Datasheet

3.4.4 Other PCI and CardBus Signals

Figure 5. Timing Diagram for Other PCI and CardBus Signals in a 3.3-V signaling environment. Table 18. Other PCI and CardBus Signals’ Timing Specifications

1. Load for this measurement is as specified in PCI Local Bus Specification, Revision 2.0 and PCI Local Bus Specification,
2. Valid delays for PCI, selected by default when pin cb_pad_l is not pulled down externally.
3. Valid delays for CardBus, selected by default when pin cb_pad_l is pulled down externally.
4. Parameter design guarantee.

4 Output rise and fall slew rate5

1. Slew rate for PCI, selected by default when pin cb_pad_l is not pulled down externally.

1 V/ns 4 V/ns

1. Slew rate for CardBus, selected when pin cb_pad_l is pulled down externally.

0.25 V/ns 1 V/ns

3.5 AUI and Twisted-Pair DC Specifications

Table 19 lists the dc specifications for the AUI and twisted-pair parts of the SIA. Table 19. AUI and Twisted-Pair DC Specifications

1. Parameter design guarantee.

1 Transmit differential output idle

1 Differential input voltage range

26 Preliminary Datasheet

3.6 Serial Interface Attachment Specifications

This section describes the dc specifications and timing limits of the SIA unit.

3.6.1 Serial Clock Timing

clock timing specifications. Figure 6. Serial Clock (XTAL) Timing Diagram Table 20. Serial Clock (XTAL) Timing Specifications

1. Parameter design guarantee.

3.6.2 Internal SIA Mode AUI Timing—Transmit

internal SIA transmit timing limits for the AUI. Figure 7. Internal SIA Mode AUI Timing Diagram—Transmit Table 21. Internal SIA Mode AUI Timing Specifications—Transmit

1. Parameter design guarantee.

28 Preliminary Datasheet

3.6.3 Internal SIA Mode AUI Timing—Receive

internal SIA receive timing limits for the AUI.

3.6.4 Internal SIA Mode AUI Timing—Collision

internal SIA collision timing limits for the AUI. Figure 8. Internal SIA Mode AUI Timing Diagram—Receive Figure 9. Internal SIA Mode AUI Timing Diagram—Collision Table 22. Internal SIA Mode AUI Timing Specifications—Receive and

1. Parameter design guarantee.

3.6.5 Internal SIA Mode 10BASE-T Interface Timing—Transmit

Table 23 lists the internal SIA transmit limits. Figure 10. Internal SIA Mode 10BASE-T Interface Timing Diagram— Table 23. Internal SIA Mode 10BASE-T Interface Timing Specifications—Transmit

1. Parameter design guarantee.

30 Preliminary Datasheet

3.6.6 Internal SIA Mode 10BASE-T Interface Timing—Receive

Table 24 lists the internal SIA receive limits for the 10BASE-T interface. Figure 11. Internal SIA Mode 10BASE-T Interface Timing Diagram— Table 24. Internal SIA Mode 10BASE-T Interface Timing Specifications—Receive

1. Parameter design guarantee.

3.6.7 Internal SIA Mode 10BASE-T Interface Timing—Idle Link Pulse

and Table 25 lists the internal SIA idle link pulse limits for the 10BASE-T interface. Figure 12. Internal SIA Mode 10BASE-T Interface Timing Table 25. Internal SIA Mode 10BASE-T Interface Timing Specifications—Idle Link

1. Parameter design guarantee.

32 Preliminary Datasheet

3.7 MII Interface Specifications

Table 26 lists the specifications for the MII interface.

3.8 MII/SYM Port Timing

This section describes the MII/SYM port timing limits.

3.8.1 MII/SYM 10/100-Mb/s and 10-Mb/s Timing—Transmit

port transmit timing limits. Table 26. MII Interface

Figure 13. MII/SYM Port Timing Diagram—Transmit Table 27. MII/SYM Port Timing Limits—Transmit

1. t=1 for 100-Mb/s operation; t=10 for 10-Mb/s operation.
2. Parameter design guarantee.
3. The transmit data (mii/sym_txd) and transmit enable (mii_txen) output pins are driven internally from the rising edge

34 Preliminary Datasheet

3.8.2 MII/SYM 10/100-Mb/s Timing—Receive

Figure 14. MII/SYM Port Timing Diagram—Receive Table 28. MII/SYM Port Timing Limits—Receive

1. t=1 for 100-Mb/s operation; t=10 for 10-Mb/s operation.
2. Parameter design guarantee.
3. The receive data (mii/sym_rxd) and data valid (mii_dv) input pins are latched internally on the rising edge of mii/

3.8.3 SYM 10/100-Mb/s Timing—Signal Detect

signal detect timing limits.

3.8.4 MII 10/100-Mb/s Timing—Receive Error

receive error timing limits. Figure 15. SYM Port Timing Diagram—Signal Detect Table 29. SYM Port Timing Limits—Signal Detect

1. Input signal detect (sd) is latched internally on the falling edge of sym_rclk.

Figure 16. MII Port Timing Diagram—Receive Error Table 30. MII Port Timing Limits—Receive Error

1. Input signal detect (mii_rx_err) is latched internally on the falling edge of mii_rclk.

36 Preliminary Datasheet

3.8.5 MII 10/100-Mb/s Timing—Carrier Sense and Collision

the MII port carrier sense and collision timing limits.

3.9 Boot ROM and Serial ROM Port Specification

apply in any mode in which the ports are used. Figure 17. MII Port Timing Diagram—Carrier Sense and Collision Table 31. MII Port Timing Limits—Carrier Sense and Collision Table 32. Boot ROM and Serial ROM Port DC Specifications

1 Maximum tristate output

1. For sr_do and br_ce_l, the maximum value is 1000.0 mA.

3.10 Boot ROM Port Timing

This section describes the boot ROM port timing.

3.10.1 Boot ROM Read Timing

Figure 18. Boot ROM Read Timing Diagram Table 33. Boot ROM Read Timing Specifications

1. Parameter design guarantee.

38 Preliminary Datasheet

3.10.2 Boot ROM Write Timing

Figure 19. Boot ROM Write Timing Diagram Table 34. Boot ROM Write Timing Specifications

1. There are no maximum specifications.

3.11 Serial ROM Port Timing

identical to the timing for the MII management signals (mii_mdio and mii_mdc).

3.12 External Register Timing

Figure 20. Serial ROM Port Timing Diagram Table 35. Serial ROM Port Timing Characteristics

1. Parameter design guarantee.

Figure 21. External Register Read Timing Diagram

40 Preliminary Datasheet

Figure 22. External Register Write Timing Diagram Table 36. External Register Timing Specifications

1. Parameter design guarantee.

3.13 Joint Test Action Group—Test Access Port

This section provides the joint test action group (JTAG) test access port specifications.

3.13.1 JTAG DC Specifications

Table 37. JTAG DC Specifications

1. For pins tdi and tms that have internal pull-ups, the leakage current can get to 1.0 mA when Vin = 0 V.

42 Preliminary Datasheet

3.13.2 JTAG Boundary-Scan Timing

Figure 23. JTAG Boundary-Scan Timing Diagram Table 38. JTAG Interface Signal Timing Relationships

1. Parameter design guarantee.

4.0 Mechanical Specifications

The 21143 is contained in either a 144-pin LQFP package type or a 144-pin MQFP package type. Figure 24 shows the mechanical layout of the LQFP, and Table 39 lists the LQFP package dimensions in millimeters. Figure 25 shows the mechanical layout of the MQFP, and Table 40 lists the MQFP package dimensions in millimeters.

44 Preliminary Datasheet

Figure 24. 144-Pin LQFP Package R Notes: All dimensions are in millimeters.

Table 39. 144-Pin LQFP Package Dimensions

1. The value for this measurement is for reference only.
2. ANSI Y14.5M–1982 American National Standard Dimensioning and Tolerancing, Section 1.3.2, defines Basic Dimension

46 Preliminary Datasheet

Figure 25. 144-Pin MQFP Package R Note: All dimensions are in millimeters.

Table 40. 144-Pin MQFP Package Dimensions

1. The value for this measurement is for reference only.
2. ANSI Y14.5M–1982 American National Standard Dimensioning and Tolerancing, Section 1.3.2, defines Basic Dimension

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