087900-00

MX879 IXYS | Alldatasheet

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Technical content

Drawing No. 087909 www.claremicronix.com MX879 8-Channel, 60V Relay/Load Driver Open Drain Output, 3 Wire Interface Features:

• 8 Outputs Rated at 60V, 120mA
• Open Drain Pull-Up Driver Configuration
• 6V to 60V Driver Supply Range
• 2.7V to 5.5V Logic Supply Range
• 3 Wire Serial Interface plus Chip Select
• Captures Serial & Parallel Input Data
• Outputs can be paralleled
• 28 Lead QFN Package Applications:
• White Goods
• ATE
• Industrial Equipment
• Automotive Relay Control General Description The MX879 is an 8 channel high voltage switch with 8-bit parallel or serial input control. The MX879 connects directly to a microprocessor through a standard 3 wire serial interface. The open drain pull- up output configuration can drive up to 60 volts at 120mA. Outputs can be paralleled for increased drive current up to a device total of 600mA source. The MX879 is designed to operate over a temperature range of -40°C to +85°C, and is available in a QFN-28 Package.

Ordering Information

Part No. Description Qty 087900-00 QFN-28 73 087941-00 QFN-28 Tape & Reel 2500 Functional Block Diagram Parallel Inputs Shift Direction VCC VPWR CS* SDO IN7 IN6 OUT7 IN5 I/O Register Latch Register Driver OUT6 IN4 OUT5 IN3 OUT4 IN2 OUT3 IN1 OUT2 IN0 OUT1 OUT0 SCK SDI OE GND Parallel In & Out Level Translator

Drawing No. 087909 www.claremicronix.com MX879 IXYS Absolute Maximum Ratings (Voltages with respect to GND=0V) Parameter Symbol Min Max Unit VPWR Supply Voltage VPWR 62 V Logic Supply Voltage VCC 6 V Input Pin Voltage V IN 6 V Continuous Output Current I OUT(OUT0-7) 150 mA Storage Temperature T STG -55 150 C o Operating Ambient Temp T A -40 85 C o Operating Junction Temp T J 150 C o Thermal Resistance (Junction to Ambient) RθJA 110 Typical C o/W ESD Warning ESD (electrostatic discharge) sensitive device. Although the MX879 features proprietary ESD protection circuitry, permanent damage may be sustained if subjected to high energy electrostatic discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. VCC=5.0V, VPWR=42V, TA=25oC, unless otherwise specified. Parameter Condition Min Typ Max Unit Logic Supply Voltage 2.7 5.5 V Logic Supply Current fSCK = 5 MHz 50 µA Quiescent Logic Supply Current fSCK = 0 1 µA VPWR Voltage 6 60 V VPWR Current Total of all outputs 600 mA Quiescent VPWR Current VPWR = 42V, No load 0.75 mA High Level Input Voltage IN0-7, SCK, SDI, OE, CS Ä VCC-0.5 V Low Level Input Voltage 0.5 V Input Leakage Current 1 µA SDO Tri-State Leakage Current CSÄ = Logic High 1 µA Out0-7 Current Any one output, source 120 mA Out0-7 ON Resistance VPWR = 42V 7 Ω Out0-7 Tri-State Leakage Current OE = Logic Low 1 µA Notes: To avoid unwanted output during VPWR application a nd system initialization, keep OE at a logic low until CSÄ has completed one cycle. Thermal Resistance is measured in still air with the device so ldered to a 6 square inch board without a ground plane. Applications may require derating of the specified maximum currents to avoid exceeding the maximum operation junction temperature. Absolute Maximu m Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the dev ice at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and affect its reliability.

Drawing No. 087909 www.claremicronix.com MX879 IXYS VCC=5.0V, VPWR=42V, TA=25oC, unless otherwise specified. Parameter Symbol Condition Min Typ Max Unit SCK Period 1 100 DC nS SCK High Time 1 40 nS SCK Low Time 1 40 nS CSÄ High Time 1 tCSwh 50 nS CSÄ Falling to SCK Rising 1 tCSs Setup Time 150 nS CSÄ Low Time 1 tCSwl SCK Low, (parallel input mode) 150 nS INX to CS Falling (SETUP TIME) 1 tINs 15 nS INX to CS Falling (HOLD TIME) 1 tINh 30 SDI to SCK Rising (SETUP TIME) 1 tSDIs 20 nS SDI to SCK Rising (HOLD TIME) 1 tSDIh 25 SCK Falling to SDO Data Valid tSDO 10 nS CSÄ Rising to SDO High Z tSDOz 12 nS CSÄ Rising to OUTX Rising tOUTr To 50%, C(OUTx) = 1000pF 680 nS OUTX Rise Time From 10% to 90%, C(OUTx) = 1000pF 110 nS OE Rising to OUTX Rising To 90% 580 nS OE Rising to OUTX Falling To 90% 390 nS To 10%, OUTx High 130 nS OE Falling to OUTX High Z To 10%, OUTx Low 90 nS Note 1: Guaranteed by design.

Drawing No. 087909 www.claremicronix.com MX879 IXYS Serial Timing Parallel Timing INx tINs tINh CS* tCSs tCSwh SCK tSDIs tSDIh SDI tSDO tSDOz SDO t O U T r O U T x tOUTf INx tINs tINh CS* tCSwl tOUTr OUTx tOUTf

Drawing No. 087909 www.claremicronix.com MX879 IXYS Pin Description Pin No. Pin Name Description 4, 17 VPWR High Voltage Supply ( 6V to 60V) 2, 5 - No Connect 6 VCC Logic Supply (2.7V to 5.5V)

7 SDO Serial Data Output

8 IN7 Parallel Input

9 IN6 Parallel Input

10 IN5 Parallel Input

11 IN4 Parallel Input

12 IN3 Parallel Input

13 IN2 Parallel Input

14 IN1 Parallel Input

15 IN0 Parallel Input

16 SCK Serial Clock

18 SDI Serial Data Input

19 CS Ä Chip Select (Active Low)

20 OE Output Enable

3, 21 GND Ground

22 OUT0 Parallel Output

23 OUT1 Parallel Output

24 OUT2 Parallel Output

25 OUT3 Parallel Output

26 OUT4 Parallel Output

27 OUT5 Parallel Output

28 OUT6 Parallel Output

1 OUT7 Parallel Output

Drawing No. 087909 www.claremicronix.com MX879 IXYS Functional Description The MX879 is an 8 channel high voltage driver with 8-bit input control. The MX879 interfaces to a microprocessor through a standard 3 wire serial interface and an active low chip select, or can be used in a parallel-in, parallel-out configuration. Parallel data is transferred to the I/O register of the MX879 through the parallel input pins, IN0 through IN7 on the falling edg e of the chip select pin, CSÄ. When CSÄ is in a logic low state, serial data can be transferred to the I/O register through the serial input pin, SDI, and from the I/O register through the serial output pin, SDO. Parallel or serial input data is transferred from the I/O register to the latch and high voltage output drivers, OUT0 through OUT7, on the positive edge of CS Ä. This data remains latched until the next positive edge of CSÄ. The 8-bit I/O shift register is clocked by the serial clock pin, SCK. Serial data presented at the SDI pin is transferred to the shift register on the positive edge of SCK. Data shifts out of the register through the SDO pin on the negative edge of SCK. SDI and SCK are ignored, and SDO transitions to a high impedance condition when CS Ä is at a logic high state. Serial data is received by the MX879 through the SDI pin. This data is accepted on the rising edge of SCK. A specific output is programmed to a logic high state if SDI is at a logic high state during the rising edge of SCK. Conversely, a specific output is programmed to a logic low state if SDI is at a logic low state during the rising edge of SCK. Outputs transition to their programmed states on the positive edge of CS Ä if the output enable pin, OE is in a logic high state. The MSB input data (IN7) is presented at the serial output pin, SDO on the falling edge of CS Ä. Input data from IN6 thro ugh IN0 is sequentially presented at SDO on negative SCK transitions if CSÄ remains in a logic low state. If CS Ä is at a logic low state beyond 8 cycles of SCK, SDI data that has propagated through the I/O register will then be presented at SDO. The SDO pin transitions to a high impedance state when CS Ä is in a logic level high state, thus allowing multiple serial peripherals to share the microprocessor data pin. Serial Data Transfer Example 00 0 0 00 0 0 11 1 1 111 IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0 SDI SCK CS SDO SDI at time t1 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 Devices may be serially cascaded by connecting SDO to SDI of the next device. Pins SCK and CSÄ are common to all devices in serial cascade. For n-cascaded devices the CSÄ should remain low for 8n cycles of SCK. An output enable pin, OE enables the driver outputs OUT0 through OUT7 when logic high. A logic low level on OE forces the OUT0 through OUT7 outputs to a high impedance state. The MX879 can also operate as a parallel-in, parallel-out level shifter and driver. SCK must remain at a logic low state when operating in this mode. Parallel input data presented to IN0 through IN7 is captur ed on the falling edge of CS Ä. This data is transferred to OUT0 through OUT7 on the rising edge of CS Ä, and remains latched until the next rising edge of CSÄ.

Drawing No. 087909 www.claremicronix.com MX879 IXYS Parallel-in / Parallel-out Application Serial Cascade Application I N O U T 8 8 C S * S D I OE SCK MASTER IN SDO IN OUT 8 8 S C K C S * O E SDI SDO IN OUT 8 8 S C K C S * O E SDI MASTER OUT

Drawing No. 087909 www.claremicronix.com MX879 IXYS Control System Application S y s t e m MX879 c a p t u r e s e n s o r s I N S D I S D O d r i v e S C K u C actuators OUT CS*

8 O E

Type 1 timing: capture N drive N analyze N, calculate N+1 capture N+1 drive N+1 CS* SDI uC output N uC output N+1 SCK SDO input N uC input N+1 uC Type 2 timing: capture N analyze N, calculate N+1 drive N+1 capture N+1 CS* SDI don't care uC output N+1 SCK SDO input N uC ignore

Drawing No. 087909 www.claremicronix.com MX879 IXYS IXYS Corporation makes no representations or warranties with res pect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descrip tions at any time without notice. Neith er circuit patent licenses nor indem nity are expressed or implied. Except as se t forth in IXYS’ Standard Terms and Conditions of Sale, IXYS Corporation assumes no liability whatsoever, and disclaims any expressed or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantab ility, fitness for a particular purpose, or infringement of an y intellectual property right .128.118 3.25 3.00E2 NOTES: (UNLESS OTHERWISE SPECIFIED) HE AT SINK SLUG AS WE LL AS THE TE R MINALS. 3. MOLDED PACKAGE SHALL CONFORM TO 2. DIMENSIONS AND TOLERANCING CONFORM 1. COP LANAR ITY AP P LIE S TO THE E XP OSE D .0197 BSC .0256 MO-220 VARIATION VHHD-1. TO ASME Y14.5M-1994. JEDEC STANDARD CONFIGURATION .0177 L N e .500 BSC .65.45 BOTTOM VIEW SIDE VIEW 28 LE AD 5MM X 5MM X 0.90MM QFN MM.INCH .039 .008 R E F. .012 .197 BSC .128 .197 BSC .002 MAX. .031 .007 .118 E D b A DIM. MIN.

5.00 BSC

3.253.00 ,200 R E F . 1.0.80 .30.18 .050 MAX.MIN. DIMENSIONS TOP VIEW PIN 1 (REF.)

Drawing No. 087909 www.claremicronix.com World Wide Sales Offices IXYS IXYS Corporation

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