X9241A INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Four potentiometers in one package
  • 2-wire serial interface
  • Register oriented format - Direct read/write/transfer of wiper positions - Store as many as four positions per potentiometer
  • Terminal Voltages: +5V, -3.0V
  • Cascade resistor arrays
  • Low power CMOS
  • High Reliability - Endurance–100,000 data changes per bit per register - Register data retention–100 years
  • 16-bytes of nonvolatile memory
  • 3 resistor array values -2 k Ω to 50kΩ mask programmable - Cascadable for values of 500 Ω to 200kΩ
  • Resolution: 64 taps each pot
  • 20 Ld plastic DIP, 20 Ld TSSOP and 20 Ld SOIC packages
  • Pb-free plus anneal available (RoHS compliant) Block Diagram Data R1R0 R3R2 VH0/RH0 VL0/RL0 VW0/RW0 Wiper Counter Register (WCR) VH1/RH1 VL1/RL1 VW1/RW1 Register Array Pot 1 Wiper Counter Register (WCR) R1R0 R3R2 SCL SDA Interface and Control Circuitry VH2/ VL2/RL2 VW2/RW2 VH3/RH3 VL3/RL3 VW3/RW3 Register Array Pot 2 Wiper Counter Register (WCR) R1R0 R3R2 Register Array Pot 3 Wiper Counter Register (WCR) R1R0 R3R2 VCC VSS RH2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Data Sheet FN8164.1 September 15, 2005

2 FN8164.1 September 15, 2005

Ordering Information

(V) POTENTIOMETER ORGANIZATION (K) TEMP RANGE (°C) PACKAGE X9241AMP X9241AMP 5 ±10% 2/10/50 0 to 70 20 Ld PDIP X9241AMPZ (Note) X9241AMPZ 0 to 70 20 Ld PDIP (Pb-free) X9241AMPI X9241AMPI -40 to 85 20 Ld PDIP X9241AMPIZ (Note) X9241AMPIZ -40 to 85 20 Ld PDIP (Pb-free) X9241AMS* X9241AMS 0 to 70 20 Ld SOIC X9241AMSZ* (Note) X9241AMS Z 0 to 70 20 Ld SOIC (Pb-free) X9241AMSI* X9241AMSI -40 to 85 20 Ld SOIC X9241AMSIZ* (Note) X9241AMSI Z -40 to 85 20 Ld SOIC (Pb-free) X9241AMV* X9241AMV 0 to 70 20 Ld TSSOP X9241AMVZ* (Note) X9241AMV Z 0 to 70 20 Ld TSSOP (Pb-free) X9241AMVI* X9241AMVI -40 to 85 20 Ld TSSOP X9241AMVIZ* (Note) X9241AMVI Z -40 to 85 20 Ld TSSOP (Pb-free) X9241AWP X9241AWP 10 0 to 70 20 Ld PDIP X9241AWPZ (Note) 0 to 70 20 Ld PDIP (Pb-free) X9241AWPI X9241AWPI -40 to 85 20 Ld PDIP X9241AWPIZ (Note) X9241AWPI Z -40 to 85 20 Ld PDIP (Pb-free) X9241AWS* X9241AWS 0 to 70 20 Ld SOIC X9241AWSZ* (Note) X9241AWS Z 0 to 70 20 Ld SOIC (Pb-free) X9241AWSI* X9241AWSI -40 to 85 20 Ld SOIC X9241AWSIZ* (Note) X9241AWSI Z -40 to 85 20 Ld SOIC (Pb-free) X9241AWV* X9241AWV 0 to 70 20 Ld TSSOP X9241AWVZ* (Note) X9241AWVZ 0 to 70 20 Ld TSSOP (Pb-free) X9241AWVI* X9241AWVI -40 to 85 20 Ld TSSOP X9241AWVIZ* (Note) X9241AWVI Z -40 to 85 20 Ld TSSOP (Pb-free) X9241AYP X9241AYP 2 0 to 70 20 Ld PDIP X9241AYPZ (Note) X9241AYP Z 0 to 70 20 Ld PDIP (Pb-free) X9241AYPI X9241AYPI -40 to 85 20 Ld PDIP X9241AYPIZ (Note) X9241AYPI Z -40 to 85 20 Ld PDIP (Pb-free) X9241AYS* X9241AYS 0 to 70 20 Ld SOIC X9241AYSZ* (Note) X9241AYS Z 0 to 70 20 Ld SOIC (Pb-free) X9241AYSI* X9241AYSI -40 to 85 20 Ld SOIC X9241AYSIZ* (Note) -40 to 85 20 Ld SOIC (Pb-free) X9241AYV* X9241AYV 0 to 70 20 Ld TSSOP X9241AYVZ* (Note) X9241AYV Z 0 to 70 20 Ld TSSOP (Pb-free) X9241AYVI* X9241AYVI -40 to 85 20 Ld TSSOP X9241AYVIZ* (Note) X9241AYVI Z -40 to 85 20 Ld TSSOP (Pb-free) X9241A

3 FN8164.1 September 15, 2005 Pin Descriptions Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9241A. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire- ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. Address The Address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9241A. Potentiometer Pins VH/RH(VH0/RH0—V H3/RH3), VL/RL (VL0/RL0—V L3/RL3) The RH and RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. VW/RW (VW0/RW0—V W3/RW3) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Pin Configuration X9241AUP X9241AUP 5 ±10% 50 0 to 70 20 Ld PDIP X9241AUPZ (Note) X9241AUP Z 0 to 70 20 Ld PDIP (Pb-free) X9241AUPI X9241AUPI -40 to 85 20 Ld PDIP X9241AUPIZ (Note) X9241AUPI Z -40 to 85 20 Ld PDIP (Pb-free) X9241AUS* X9241AUS 0 to 70 20 Ld SOIC X9241AUSZ* (Note) X9241AUS Z 0 to 70 20 Ld SOIC (Pb-free) X9241AUSI* X9241AUSI -40 to 85 20 Ld SOIC X9241AUSIZ* (Note) X9241AUSI Z -40 to 85 20 Ld SOIC (Pb-free) X9241AUV* X9241AUV 0 to 70 20 Ld TSSOP X9241AUVZ* (Note) X9241AUV Z 0 to 70 20 Ld TSSOP (Pb-free) X9241AUVI* X9241AUVI -40 to 85 20 Ld TSSOP X9241AUVIZ* (Note) X9241AUVI Z -40 to 85 20 Ld TSSOP (Pb-free) *Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products em ploy special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Ordering Information (Continued) PART NUMBER PART MARKING VCC LIMITS (V) POTENTIOMETER ORGANIZATION (K) TEMP RANGE (°C) PACKAGE Pin Names SYMBOL DESCRIPTION SCL Serial Clock SDA Serial Data A0–A3 Address VH0/RH0–VH3/RH3, VL0/RL0–VL3/RL3 Potentiometer Pins (terminal equivalent) VW0/RW0–VW3/RW3 Potentiometer Pins (wiper equivalent) VW0/RW0 VH1/RH1 SDA V SS V CC SCL DIP/SOIC/TSSOP X9241A VL0/RL0 VH0/RH0 VW1/RW1 VL1/RL1 VW3/RW3 VL3/RL3 VH3/RH3 VW2/RW2 VL2/RL2 VH2/RH2 X9241A

between the host and the XDCP potentiometers. The X9241A supports a bidirectional bus oriented protocol. bus as a transmitter and the receiving device as the receiver. considered a slave device in all applications. are reserved for indicating start and stop conditions. respond to any command until this condition is met. successfully received the eight bits of data. See Figure 7. respond with a final acknowledge. can be read and written by the host system. to Figure 1 below). For the X9241A this is fixed as 0101[B]. FIGURE 1. SLAVE ADDRESS

associated registers. The format is shown below in Figure 2. when a register oriented instruction is issued.

  1. These two-byte instructions exchange data between the

one of their associated registers. Four instructions require a three-byte sequence to complete. Register, write a new value to the selected Data Register. The sequence of operations is shown in Figure 4. steps; thereby, providing a fine tuning capability to the host. Figures 5 and 6 respectively. FIGURE 2. INSTRUCTION BYTE FORMAT

0101 A 3 A 2 A 1 A 0

FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS

TABLE 1. INSTRUCTION SET FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER

organization and array operation follows. contents of its Data Register zero (DR0) upon power-up. Each potentiometer has four nonvolatile Data Registers. will take a maximum of 10ms. system parameters or user preference data. FIGURE 8. DETAILED POTE NTIOMETER BLOCK DIAGRAM

10 FN8164.1 September 15, 2005 Notes: (1) Absolute Linearity is utilized to determi ne actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative Linearity is utilized to determi ne the actual change in voltage between two successive tap positions when used as a potenti- ometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (R H–RL)/63, single pot (4) Max. = all four arrays cascaded together, Typical = individual array resolutions. Absolute Maximum Ratings Recommended Operating Conditions Voltage on SCK, SCL or any address Voltage on any VH/RH, VW/RW or VL/RL Supply Voltage (VCC) Limits CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stres s rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Analog Specifications (Over recommended operating conditions unless otherwise stated.) SYMBOL PARAMETER TEST CONDITION LIMITS UNITMIN TYP MAX RTOTAL End to end resistance -20 +20 % Power rating 25°C, each pot 50 mW IW Wiper current See Note 7, 8 mA RW Wiper resistance Wiper Current = ± 1mA (Note 7) 40 130 Ω VTERM Voltage on any VH/RH, VW/RW or VL/RL Pin -3.0 +5 V Noise Ref: 1kHz See Note 5 ≤120 dBV Resolution(4) See Note 5 1.6 0.4 % Absolute linearity(1) Rw(n)(actual) - Rw(n)(expected) ±1 MI (3) Relative linearity(2) Rw(n + 1) - [Rw(n) + MI]± 0 . 2 M I (3) Temperature Coefficient of RTOTAL See Note 5 ±300 ppm/°C Ratiometric temperature coefficient See Note 5 ±20 ppm/C CH/CL/CW Potentiometer capacitances See Circuit #3 and Note 5 15/15/25 pF lAL RH, RI, RW leakage current V IN = VTERM. Device is in stand-by mode. 0.1 1 µA SYMBOL PARAMETER TEST CONDITION LIMITS UNITMIN TYP MAX lCC Supply current (active) f SCL = 100kHz, SDA = Open, Other Inputs = VSS 3m A ISB VCC current (standby) SCL = SDA = V CC, Addr. = VSS 200 500 µA ILI Input leakage current V IN = VSS to VCC 10 µA ILO Output leakage current V OUT = VSS to VCC 10 µA VIH Input HIGH voltage 2 V CC + 1 V VIL Input LOW voltage -1 0.8 V VOL Output LOW voltage I OL = 3mA 0.4 V X9241A

11 FN8164.1 September 15, 2005 Power-up Requirements (Power Up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First Vcc, then the potentiometer pins. It is suggested that Vcc reach 90% of its final value before power is applied to the potentiometer pins. The Vcc ramp rate specification should be met, and any glitches or slope changes in the Vcc line should be held to <100mV if possible. Also, Vcc should not reverse polarity by more than 0.5V. Notes: (5) This parameter is guaranteed by characterization or sample testing. (6) t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are guaranteed by design. (7) This parameter is guaranteed by design. (8) Maximum Wiper Current is derated over tem perature. See the Wiper Current Derating Curve. (9) Ti value denotes the maximum noise glitch pulse width that the device will ignore on either SCL or SDA pins. Any noise glitc h pulse width that is greater than this maximum value will be considered as a valid clock or data pulse and may cause communication failure to the device. Symbol Table Endurance and Data Retention PARAMETER MIN UNIT Minimum endurance 100,000 Data changes per bit per register Data retention 100 Years Capacitance SYMBOL PARAMETER TEST CONDITION MAX UNIT CI/O(5) Input/output capacitance (SDA) V I/O = 0V 19 pF CIN(5) Input capacitance (A0, A1, A2, A3 and SCL) V IN = 0V 12 pF Power-up Timing SYMBOL PARAMETER MIN TYP MAX UNIT tPUR(6) Power-up to initiation of read operation 1 ms tPUW(6) Power-up to initiation of write operation 5 ms tRVCC VCC Power up ramp rate 0.2 50 V/msec AC Conditions of Test Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels V CC x 0.5 WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance X9241A

12 FN8164.1 September 15, 2005 Equivalent AC Test Circuit Circuit #3 SPICE Macro Model Guidelines for Calculating Typical Values of Bus Pull-Up Resistors DCP Wiper Current De-rating Curve 1533Ω 100pF SDA Output RH CH 10pF CW RL CL RW RTOTAL 25pF 10pF Macro Model 120 100 20 40 60 80 100 120 Bus Capacitance (pF) Min. Resistance Max. Resistance RMAX =CBUS tR RMIN = IOL MIN VCC MAX=1.8kΩ Resistance (kΩ) 20 40 60 70 80 90 Ambient Temperature (°C) Maximum DCP Wiper Current 5010 30 SYMBOL PARAMETER LIMITS UNIT REFERENCE FIGUREMIN MAX fSCL(5) SCL clock frequency 0 100 kHz 10 tLOW(5) Clock LOW period 4700 ns 10 tHIGH(5) Clock HIGH period 4000 ns 10 tR(5) SCL and SDA rise time 1000 ns 10 tF(5) SCL and SDA fall time 300 ns 10 Ti(5)(9) Noise suppression time constant (glitch filter) 20 ns 10 tSU:STA(5) Start condition setup time (for a repeated start condition) 4700 ns 10 & 12 tHD:STA(5) Start condition hold time 4000 ns 10 & 12 tSU:DAT(5) Data in setup time 250 ns 10 tHD:DAT(5) Data in hold time 0 ns 10 tAA(5) SCL LOW to SDA data out valid 3500 ns 11 tDH(5) Data out hold time 50 ns 11 tSU:STO(5) Stop condition setup time 4700 ns 10 & 12 tBUF(5) Bus free time prior to new transmission 4700 ns 10 tWR(5) Write cycle time (nonvolatile write operation) 10 ms 13 X9241A

14 FN8164.1 September 15, 2005 Packaging Information 0.022 (0.559) 0.014 (0.356) (3.81) 0.150 (2.92) 0.1150 0.10 (BSC) (2.54) 1.060 (26.92) 0.980 (24.89) 0.900 (23.66) Ref. Pin 1 Index 0.195 (4.95) 0.115 (2.92) 0.015 (0.38) Pin 1 Seating Plane 0.070 (1.778) 0.045 (1.143) 0.280 (7.11) 0.240 (6.096) 0.005 (0.127) 15° 20-Lead Plastic Dual In-Line Package Type P 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 0.014 (0.356) 0.008 (0.2032) 0.300 (7.62) (BSC) NOTE: X9241A

15 FN8164.1 September 15, 2005 Packaging Information 0.290 (7.37) 0.299 (7.60) 0.393 (10.00) 0.420 (10.65) 0.014 (0.35) 0.020 (0.50) Pin 1 Pin 1 Index 0.050 (1.27) 0.496 (12.60) 0.508 (12.90) 0.003 (0.10) 0.012 (0.30) 0.092 (2.35) 0.105 (2.65) (4X) 7° 20-Lead Plastic Small Outline Gull Wing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.420" 0.050" Typical 0.050" Typical 0.030" Typical

20 PlacesFOOTPRINT

0.010 (0.25) 0.020 (0.50) 0.015 (0.40) 0.050 (1.27) 0.007 (0.18) 0.011 (0.28) 0°–8° X 45° X9241A

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8164.1 September 15, 2005 Packaging Information NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20-Lead Plastic, TSSOP, Package Type V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .260 (6.6) .252 (6.4) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) X9241A