CS82C85

82C85 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

• Generates the System Clock For CMOS or NMOS Microprocessors and Peripherals
• Complete Control Over System Operation for Very Low System Power - Stop-Oscillator - Low Frequency - Stop-Clock - Full Speed Operation
• DC to 25MHz Operation (DC to 8MHz System Clock)
• Generates 50% and 33% Duty Cycle Clocks (Synchronized)
• Uses a Parallel Mode Crystal Circuit or External Frequency Source
• TTL Compatible Inputs/Outputs
• 24 Lead Slimline Dual-In-Line or 28 Pad Square LCC Package Options
• Single 5V Power Supply
• Operating Temperature Range oC to +70oC Pinouts

24 LEAD CERDIP

Description

The Intersil 82C85 Static CMOS Clock Controller/Genera- tor provides complete control of static CMOS system oper- ating modes and supports full speed, slow, stop-clock and stop-oscillator operation. While directly compatible with the Intersil 80C86 and 80C88 16-bit Static CMOS Microproces- sor Family, the 82C85 can also be used for general system clock control. For static system designs, separate signals are provided on the 82C85 for stop (S0, S1, S2/STOP ) and start (START) control of the crystal oscillator and system clocks. A single control line (SLO /FST) determines 82C85 fast (crystal/EFI frequency divided by 3) or slow (crystal/EFI frequency divided by 768) mode operation. Automatic maximum mode 80C86 and 80C88 software HALT instruction decode logic in the 82C85 enables software- based clock control. Restart logic insures valid clock start- up and complete synchronization of system clocks. The 82C85 is manufactured using the Intersil advanced Scaled SAJI IV CMOS process. In addition to clock control circuitry, the 82C85 also contains a crystal controlled oscillator (up to 25MHz), clock generation logic, complete “Ready” synchronization and reset logic. This permits the designer to tailor the system power-performance product to provide optimum performance at low power levels.

28 LEAD PLCC, CLCC

Ordering Information

PART NUMBER PACKAGE TEMP. RANGE PKG. NO. CS82C85 28 Ld PLCC 0 oC to +70oCN 2 8 . 4 5 IS82C85 -40 oC to +85oCN 2 8 . 4 5 CD82C85 24 Ld CERDIP 0 oC to +70oC F24.3 ID82C85 -40 oC to +85oC F24.3 MD82C85/B -55 oC to +125oC F24.3 MR82C85/B 28 Pad CLCC -55 oC to +125oCJ 2 8 . A CSYNC PCLK AEN1 RDY1 READY RDY2 AEN2 CLK GND CLK50 START SLO/FST VCC ASYNC EFI F/C RES S2/STOP OSC RESET 1911 3 2 14 14 15 16 17 1812 13 28 27 26 RDY1 READY RDY2 AEN2 CLK GND NC NC ASYNC EFI F/C OSC RES RESET CLK50 START SLO/FST NC S2/STOP AEN1 PCLK CSYNC NC VCC FN2976.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved

I O CRYSTAL CONNECTIONS: X1 and X2 are the crystal oscillator connections. The crystal frequency must be 3 times the maximum desired processor clock frequency. X1 is the oscillator circuit input and X2 is the output of the oscillator circuit. If the crystal inputs are not used, X1 must be tied to VCC or GND, and X2 should be left open. EFI 20 I EXTERNAL FREQUENCY IN: When F/C is HIGH, CLK is generated from the EFI input signal. This input signal should be a square wave with a frequency of three times the maximum desired CLK output frequency. If the crystal inputs are not used. XI must be tied to VCC or GND, and X2 should be left open. F/C 19 I FREQUENCY/CRYSTAL SELECT: F/C selects either the crystal oscillator or the EFI input as the main frequency source. When F/C is LOW, the 82C85 clocks are derived from the crystal oscillator circuit. When F/C is HIGH, CLK is generated from the EFI input. F/C cannot be dynamically switched during normal operation. START 11 I A low-to-high transition on START will restart the CLK, CLK50 and PCLK outputs after the appro- priate restart sequence is completed. When in the crystal mode (F/C LOW) with the oscillator stopped. The oscillator will be restarted when a Start command is received. The CLK, CLK50 and PCLK outputs will start after the oscillator input signal (X1) reaches the Schmitt trigger input threshold and 8K internal counter reaches termi- nal count. If F/C is HIGH (EFI mode), CLK, CLK50 and PCLK will restart within 3 EFI cycles after START is recognized. The 82C85 will restart in the same mode (SLO /FST) in which it stopped. A high level on START disables the STOP mode. SO S2/STOP I I I /STOP, S1, SO are used to stop the 82C85 clock outputs (CLK, CLK50, PCLK) and are sampled by the rising edge of CLK, CLK50 and PCLK are stopped by S2 /STOP, S1, SO being in the LHH state on the low-to-high transition of CLK. This LHH state must follow a passive HHH state occurring on the previous low-to-high CLK transition. CLK and CLK50 stop in the high state when F/C is low and may stop in either the high or low state when F/C is high. PCLK stops in its current state (high or low). When in the crystal mode (F/C) low and a STOP command is issued, the 82C85 oscillator will stop along with the CLK, CLK50 and PCLK outputs. When in the EFI mode, only the CLK, CLK50 and PCLK out- puts will be halted. The oscillator circuit if operational, will continue to run. The oscillator and/or clock is restarted by the START input signal going true (HIGH) or the reset input (RES) going low. SLO/FST 12 I SLO /FST is a level-triggered input. When HIGH, the CLK and CLK50 outputs run at the maximum frequency (crystal or EFI frequency divided by 3). When LOW, CLK and CLK50 frequencies are equal to the crystal or EFI frequency divided by 768. SLO /FST changes are internally synchronized so proper CLK and CLK50 phase relationships are maintained and minimum pulse width specifica- tions are met. START and STOP control of the oscillator or EFI is available in either the SLOW or FAST frequency modes. The SLO /FST input must be held LOW for at least 195 OSC/EFI clock cy- cles before it will be recognized. This eliminates unwanted frequency changes which could be caused by glitches or noise transients. The SLO /FST input must be held HIGH for at least 6 OSC/EFI clock pulses to guarantee a transition to FAST mode operation. CLK 8 O PROCESSOR CLOCK: CLK is the clock output used by the 80C86 or 80C88 processor and other peripheral devices. When SLO/FST is high, CLK has an output frequency which is equal to the crys- tal or EFI input frequency divided by three. When SLO /FST is low, CLK has an output frequency which is equal to the crystal or EFI input frequency divided by 768. CLK has a 33% duty cycle. CLK50 10 O 50% DUTY CYCLE CLOCK: CLK50 is an auxiliary clock with a 50% duty cycle and is synchronized to the falling edge of CLK. When SLO/FST is high, CLK50 has an output frequency which is equal to the crystal or EFI input frequency divided by 3. When SLO/FST is low, CLK50 has an output fre- quency equal to the crystal or EFI input frequency divided by 768. PCLK 2 O PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is equal to the crystal or EFI input frequency divided by 6 and has a 50% duty cycle. PCLK frequency is unaffected by the state of the SLO/FST input. OSC 18 O OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is equal to that of the crystal oscillator circuit. OSC is unaffected by the state of the SLO /FST input. When the 82C85 is in the crystal mode (F/C low) and a STOP command is issued, the OSC output will stop in the HIGH state. When the 82C85 is in the EFI mode (F/C HIGH, the oscillator (if operational) will continue to run when a STOP command is issued and OSC remains active. 82C85

RES 17 I RESET IN: RES is an active LOW signal which is used to generate RESET. The 82C85 provides a Schmitt trigger input so that an RC connection can be used to establish the power-up reset of proper duration. RES starts crystal oscillator operation. RESET 16 O RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its timing characteristics are determined by RES. RESET is guaranteed to be HIGH for a minimum of 16 CLK pulses after the rising edge of RES . CSYNC 1 I CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple 82C85 and 82C84A to be synchronized to provide multiple in-phase clock signals When CSYNC is HIGH, the internal counters are reset and force CLK, CLK50 and PCLK into a HIGH state. When CSYNC is LOW, the internal counters are allowed to count and the CLK, CLK50 and PCLK outputs are active. CSYNC must be externally synchronized to EFI. AEN1 AEN2 I I ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready Signal (RDY1 or RDY2). AEN1 validates RDY1 while AEN2 validates RDY2. Two AEN signal inputs are useful in system configurations which permit the processor to access two Multi-Master System Buses. RDY1 RDY2 I I BUS READY: (Transfer Complete). RDY is an active HIGH signal which is an indication from a de- vice located on the system data bus that data has been received, or is available RDY1 is qualified by AEN1 while RDY2 is qualified by AEN2 . ASYNC 21 I READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization mode of the READY logic. When ASYNC is LOW, two stages of READY synchronization are pro- vided. When ASYNC is left open or HIGH a single stage of READY synchronization is provided. READY 5 O READY: READY is an active HIGH signal which is the synchronized RDY signal input. GND 9 I Ground VCC 24 I V CC: is the +5V power supply pin. A 0.1mF capacitor between V CC and GND is recommended. Pin Descriptions (Continued) SYMBOL DIP PIN NUMBER TYPE DESCRIPTION STOP LOGIC SYNC LOGIC PERIPHERAL CLOCK (DIVIDE BY 6) READY SYNC OSCILLATOR READY SELECT SPEED SELECT DIV 256 OR DIV 1 RESTART LOGIC CLOCK (DIVIDE LOGIC BY 3) RESET PULSE CONDITIONING LOGIC RESET CLK CLK50 PCLK OSC READY (16) (8) (10) (2) (18) (5) (17) (1) (12) (19) (23) (21) (11) (20) (22) (15) (14) (13) (4) (3) (7) (6) RES START CSYNC SLO/FST F/C EFI S2/STOP RDY1 AEN1 AEN2 RDY2 ASYNC RESTART SYNC MASTER SELECTED OSC HALT VCC (24) GND (9) OSC OSCEXTERNAL FREQ. SELECT 82C85

logic, complete “Ready” synchronization and reset logic. and complete synchronization of CLK, CLK50 and PCLK. of a particular system at a specific time (See Table 1). needed at a specific time or in a particular circumstance. and a synchronizing flip-flop to generate the reset timing. The reset signal is synchronized to the falling edge of CLK. by utilizing this function of the 82C85. issued while the 82C85 oscillator is stopped. diately after the START or RES input is synchronized internally. CLK50) start cleanly with the proper phase relationship. TABLE 1. STATIC SYSTEM OPERATING MODE CHARACTERISTICS

tion of any peripheral I/O device prior to initialization. quency determined by the main oscillator or EFI frequency. FIGURE 1. CMOS PERIPHERAL CONTROL OF 82C85 STOP, TABLE 2. TYPICAL SYSTEM POWER SUPPLY CURRENT FOR STATIC CMOS OPERATING MODES

The 82C85 S2 /STOP, S1 and S0 control lines were designed to detect a passive 111 state followed by a HALT 011 logic state before recognizing the HALT instruction and stopping the system clocks. In the MAXimum mode, the 80C86/88 status lines go into a passive (no bus cycle) logic 111 state prior to executing a HALT instruction. The qualifi- cation of a passive no bus cycle logic 111 state insures that random transitions of the status lines into a logic 011 state will not stop the system clock. This is necessary since the status lines of the 80C86/88 transition through an unknown state during T3 of the bus cycle. Once the HALT instruction is decoded by the 82C85, either the oscillator is stopped (STOP-OSCILLATOR mode F/C tied low) or the external frequency source is gated off inter- nally (STOP-CLOCK mode F/C HIGH). When the HALT instruction is decoded with F/C low, the CLK and CLK50 will be stopped in a logic high state after 2 additional cycles of the clock. PCLK stops in it’s current state (high or low). This is true for both SLOW and FAST mode operation. The HALT instruction is detected in the same manner whether the 82C85 is in the SLOW or FAST mode. Independent Stop Control for Minimum Mode Operation When the 80C86 and 80C88 microprocessors are config- ured in MINimum Mode (MN/MX pin tied high), their status lines S0, S1, and S2 assume alternate functions. The logic states and sequences (passive before a HALT) necessary for automatic HALT detect in the 82C85 do not occur as in the MAXimum mode. The 82C85 controller cannot use the microprocessor status lines to detect a software Halt instruc- tion when operating in MINimum mode. However, the negative edge-activated S2 /STOP pin pro- vides a simple means for clock control in MINimum mode 80C86 and 80C88 systems. S2 /STOP can be used as an independent STOP control when S1 and S0 are held in the logical HIGH state. Keeping the S0 and S1 inputs at a logic 1 level and transitioning S2 /STOP f rom h igh to l ow wi ll mee t the passive 111 state prior to a 011 state requirement of the 82C85. This feature allows 82C85 operation with the 80C86 and 80C88 in the MINimum mode, provides compatibility with other static CMOS microprocessors and allows maxi- mum flexibility in a system. With S2/STOP being used as a stand-alone STOP com- mand line, system clocks can be controlled via an 82C55A programmable peripheral interface or other similar interface circuits. This is accomplished by driving the S2 /STOP input with a PORT pin on the 82C55A (See Figure 1). The 82C55A port pin should be configured as an output and must present a logic HIGH to the S2 /STOP input for at least one CLK cycle, followed by a LOW state. This will meet the 82C85 status input requirement of 111 followed by a 011. When a logic 0 is written to a 82C55A port pin, the S2/ STOP pin is pulled low, stopping the system clocks (CLK, CLK50, PCLK). In essence, the 82C85 is software controlled via the 82C55A. As with the SLO /FST interface, PORT C is a logical choice for this job since the individual bit set and reset com- mands available for this port make control of the S2 /STOP input simple. A START command issued to the 82C85 will override a STOP command and the 82C85 will begin normal operation. The low state of the negative-edge triggered S2 /STOP input will not prohibit the clocks from restarting. After a START or RES command, the 82C85 must see a passive (111) state followed by a HALT (011) state to stop the system clocks. To accomplish this, the 82C55A port output must be brought high and then returned low again for the 82C85 to recognize the next STOP command. External Decode Adds Halt Control SS0, IO/M and DT/R can identify a MINimum mode 80C88 HALT execution. During T2 of the system timing (while ALE is high), SS0, IO/M , and DT/R go into a 111 state when the 80C88 is executing a software HALT. These signals cannot be tied directly to the S2 /STOP, S1 and S0 inputs since they are not guaranteed to go into a passive state prior to their 111 state. These signals can be decoded during the time ALE is high to indicate a software HALT execution. Slow Mode When continuous operation is critical but power consump- tion remains a concern, the 82C85 SLOW mode operation provides a lower frequency at the CLK and CLK50 outputs (crystal/EFI frequency divided by 768). The frequency of PCLK is unaffected. The SLOW mode allows the CPU and the system to operate at a reduced rate which, in turn, reduces system power. For example, the operating power for the 80C86 or 80C88 CPU is 10mA/MHz of clock frequency. When the SLOW mode is used in a typical 5MHz system, CLK and CLK50 run at approximately 20kHz. At this reduced frequency, the aver- age operating current of the CPU drops to 200 µA. Adding the 80C86/88 500µA standby current brings the total current to 700µA. While the CPU and peripherals run slower and the 82C85 CLK and CLK50 outputs switch at a reduced frequency, the main 82C85 oscillator is still running at the maximum fre- quency (determined by the crystal or EFI input frequency.) Since CMOS power is directly related to operating fre- quency, 82C85 power supply current will typically be reduced by 15-20%. Clock Slow/Fast Operation The SLO /FST input determines whether the CLK and CLK50 outputs run at full speed (crystal or EFI frequency divided by 3) or at slow speed (crystal or EFI frequency divided by 768) (See Figure 4). When in the SLOW mode, 82C85 stop-clock and stop-oscillator functions operate in the same manner as in the FAST mode. Internal logic requires that the SLO /FST pin be held low for at least 195 oscillator or EFI clock pulses before the SLOW mode command is recognized. This requirement eliminates unwanted FAST-to-SLOW mode frequency changes which could be caused by glitches or noise spikes. To guarantee FAST mode recognition, the SLO/FST pin must be held high for at least 6 OSC or EFI pulses. The 82C85 will begin FAST m ode operation on the next PCLK 82C85

input frequency divided by 768 when SLO /FST is low. drive the 80C86 and 80C88 microprocessors directly. frequencies which are OSC (EFI) divided by 768. has a 50% duty cycle. PCLK is unaffected by SLO /FST. the occurrence of metastable (or indeterminate) states. date their respective RDY signals. chronization are provided for active READY input signals. of synchronization for each device in the system. FIGURE 6. 82C85 AND 82C84A CSYNC SYNCHRONIZATION

Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) (Soldering 10s) (PLCC - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. TA = -40oC to +85oC (I82C85); TA = -55oC to +125oC (M82C85) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 2.0 2.2 V C82C85, I82C85 M82C85 VIHR Reset Input High Voltage 2.8 - V VIL Logical Zero Input Voltage - 0.8 V Note 1 VT+ - VT Reset Input Hysteresis 0.25 - V VOH Logical One Output Voltage V CC-0.4 - V I OH = -5.0 mA (CLK, CLK50) IOH = -1.0mA (X2) IOH = -2.5mA (all other outputs) VOL Logical Zero Output Voltage - 0.4 V I OL = +2.5mA (X2) IOL = +5.0mA (all other outputs) II Input Leakage Current -1.0 1.0 µAV IN = VCC or GND, except DIP Pins 11 - 15, 21, 23 IBHH Bus-hold High Leakage Current -10 -200 µAV IN = 3.0V; Pins 11 - 15, 21 ICCSB Standby Power Supply Current - 100 µA 82C85 in HALT state with oscillator stopped ICCOP Operating Power Supply Current - 50 mA Crystal Frequency = 15MHz, outputs open, inputs = GND or VCC - 70 mA Crystal Frequency = 25MHz, outputs open, inputs = GND or VCC ICCSLOW Slow Mode Operating Current - 40 mA Crystal Freq = 15MHz Outputs Open; SLO/FST = GND, START = VCC, Other inputs - VIN = VCC or GND- 60 mA Crystal Freq = 25MHz NOTE: 1. For CSYNC, V IL = GND Capacitance TA = 25oC SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CIN Input Capacitance 15 pF FREQ = 1MHz, all measurements are referenced to device GNDCOUT Output Capacitance 20 pF 82C85

TA = -40oC to +85oC (I82C85); TA = -55oC to +125oC (M82C85) SYMBOL PARAMETER LIMITS UNITS CONDITIONSMIN MAX TIMING REQUIREMENTS (1) TEHEL External Frequency HIGH Time 15 - ns 90%-90% V IN, Note 1, f = 25MHz (2) TELEH External Frequency LOW Time 15 - ns 10%-10% V IN, Note 1, f = 25MHz (3) TELEL EFI or Crystal Period 40 - ns Note 1 (4) TEFIDC External Frequency Input Duty Cycle 45 55 % f = 25MHz, Note 1 (5) Fx Crystal Frequency 2.4 25 MHz Note 1 (6) TR1VCL RDY1, RDY2 Active Setup to CLK 35 - ns ASYNC = HIGH (7) TR1VCH RDY1, RDY2 Active Setup to CLK 35 - ns ASYNC = LOW (8) TR1VCL RDY1, RDY2 Inactive Setup to CLK 35 - ns (9) TCLR1X RDY1, RDY2 Hold to CLK 0 - ns (10) TAYVCL ASYNC Setup to CLK 50 - ns (11) TCLAYX ASYNC Hold to CLK 0 - ns (12) TA1VR1V AEN1 , AEN2 Setup to RDY1, RDY2 15 - ns (13) TCLA1X AEN1 , AEN2 Hold to CLK 0 - ns (14) TYHEH CSYNC Setup to EFI 10 - ns (15) TEHYL CSYNC Hold to EFI 10 - ns (16) TYHYL CSYNC Pulse Width 2TELEL - ns (17) TI1HCL RES Setup to CLK 65 - ns Note 2 (18) TSVCH S0, S1, S2 /STOP Setup to CLK 35 - ns (19) TCHSV S0, S1, S2 /STOP Hold to CLK 35 - ns (20) TRSVCH RES , START Setup to CLK 65 - ns Note 2 (21) TSHSL RES (Low) or START (High) Pulse Width TCLCLs3 - ns (22) TSFPC SLO /FST Setup to PCLK TEHEL + 100 - ns Note 2 (23) TSTART RES or START Valid to CLK Low 2TELEL + 2 - ns (24) TSTOP STOP Command Valid to CLK High 2TCHCH + TRSVCH 3TCHCH + 34 ns TCHCH = TCLCL TIMING RESPONSES (25) TCLCL CLK/CLK50 Cycle Period 125 - ns Note 1 (26) TCHCL CLK HIGH Time (1/3 TCLCL)+2 - ns 82C85

(27) TCLCH CLK LOW Time (2/3 TCLCL)-15 - ns (28) T5CHCL CLK50 HIGH Time (1/2 TCLCL)-7.5 - ns (29) T5CLCH CLK50 LOW Time (1/2 TCLCL)-7.5 - ns (30) TCH1CH2 CLK/CLK50 Rise Time - 8 ns 1.0V to 3.5V (31) TCL2CL1 CLK/CLK50 Fall Time - 8 ns 1.0V to 3.5V (32) TPHPL PCLK HIGH Time TCLCL-20 - ns (33) TPLPH PCLK LOW Time TCLCL-20 - ns (34) TRYLCL Ready Inactive to CLK -8 - ns Note 4 (35) TRYHCH Ready Active to CLK 2/3(TCLCL)-15 - ns Note 3 (36) TCLIL CLK to Reset Delay - 40 ns (37) TCLPH CLK to PCLK HIGH Delay - 22 ns (38) TCLPL CLK to PCLK LOW Delay - 22 ns (39) TOST Start/Reset Valid to Clock LOW - 2 ms Typ. - Note 8 (40) TOLOH Output Rise Time (except CLK) - 15 ns From 0.8V to 2.0V (41) TOHOL Output Fall Time (except CLK) - 12 ns From 2.0V to 0.8V (42) TRST RESET output HIGH Time 16 x TCLCL - ns (43) TCLC50L CLK LOW to CLK50 LOW Skew - 5 ns NOTES: 1. Slow and Fast Modes. 2. Setup and hold necessary only to guarantee recognition at next clock. 3. Applies only to T3, TW states. 4. Applies only to T2 states. 5. All timing delays are measured at 1.5V unless otherwise noted. 6. Input signals must switch between V IL max - 0.4 and VIH min + 0.4 volts 7. Timing measurements made with EFI duty cycle = 50%. 8. Oscillator start up time depends on several factors including crystal frequency, crystal manufacturer, capacitive load, temperature, power supply voltage, etc. This parameter is given for information only. 9. Output signals switch between V OH and VOL unless otherwise specified. TA = -40oC to +85oC (I82C85); TA = -55oC to +125oC (M82C85) (Continued) SYMBOL PARAMETER LIMITS UNITS CONDITIONSMIN MAX 82C85

FIGURE 11. CLOCKS START (F/C HIGH) FIGURE 12. CLOCK START (F/C LOW) NOTE: Start up count begins when the crystal oscillator reaches a suitable threshold level.

8192 CYCLESCRYSTAL

FIGURE 15. SLO/FST TIMING OVERVIEW FIGURE 16. FAST TO SLOW CLOCK MODE TRANSITION NOTE: IF TSFPC is not met on one edge of PLCK. SLO/FST will be recognized on the next edge of PLCK.

197 TO 200 EFI

FIGURE 17. SLOW TO FAST CLOCK MODE TRANSITION NOTE: IF TSFPC is not met on one edge of PLCK. SLO/FST will be recognized on the next edge of PLCK.

6 EFI

A.C. Testing Input, Output Waveform Test Load Circuits PASSIVE LOAD R = 360 at V = 2.25 for CLK and CLK50 outputs R = 470 at V = 2.87 for all other outputs (Except X2) NOTES: 1. C L = 100pF for CLK and CLK50 output 2. C L = 50pF minimum for all other outputs 3. C L = Includes probe and jig capacitance DYNAMIC LOAD IOL = 5mA, IOH = -5mA for CLK and CLK50 outputs IOL = 5mA, IOH = -2.5mA for all other outputs (Except X2) IOL = 2.5mA, IOH = -1.0mA for X2 output (DC Performance characteristic only) VTRIP = 1.4V TCHCL, TCLCH LOAD CIRCUIT (USING X1, X2) TCHCL, TCLCH LOAD CIRCUIT (USING EFI) TRYLCL, TRYHCH LOAD CIRCUIT (USING X1, X2) TRYLCL, TRYHCH LOAD CIRCUIT (USING EFI) V R FROM OUTPUT UNDER TEST CL SEE NOTE 3 V R FROM OUTPUT UNDER TEST CL SEE NOTE 3 CSYNC CLK F/C LOAD (SEE NOTE 1) LOAD (SEE NOTE 1) CLK50 EF1 CSYNC CLK F/C VCC PULSE GENERATOR LOAD (SEE NOTE 1) LOAD (SEE NOTE 1)CLK50 CLK LOAD (SEE NOTE 1) LOAD (SEE NOTE 2) CSYNC F/C AEN2 PULSE GENERATOR TRIGGER VCC 24MHZ READY OSC AEN1 RDY2 EF1 CLK LOAD (SEE NOTE 1) F/C VCC PULSE GENERATOR CSYNC RDY2 AEN2 LOAD (SEE NOTE 2) AEN1 READY TRIGGER PULSE GENERATOR INPUT VIH + 0.4V VIL + 0.4V 1.5V 1.5V VOH VOL OUTPUT 82C85

NOTES: 1. V CC = 5.5V ±0.5V, GND = 0V 3. V IL = -0.2 to 0.4V 5. R 2 = 10kΩ, ±5% 6. R 3 = 47kΩ, ±5% 8. C1 = 0.01 µF (minimum) 9. F0 = 100kHz ±10% VCC VCC VCC B NC NC VCC VCC A VCC VCC GND VCC A GND A GND VCC NC VCC GND A VCC VCC A VCC B R3R4 R4 1µF EACH INPUT NC - NO CONNECT EACH BOARD VCC GND R2 R2 R2 VCC NC VCC VCC A B NC NC NCAG N D 3 24 1412 13 15 16 17 18 1 28 27 26 VCCAN C V CC NC VCC GND A GND NC VCC VCC 82C85

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TST, Kowloon Hong Kong TEL: +852 2723 6339 FAX: +852 2730 1433 Die Characteristics DIE DIMENSIONS: 107.9 x 122.0 x 19 ± 1mil METALLIZATION: Type: Si - AL Thickness: 11k Å ± 1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ WORST CASE CURRENT DENSITY: 2.26x 105 A/cm2 This device meets glassivation integrity test requirements per MIL-STD-883 Method 2021 Metallization Mask Layout 82C85 AEN1 PCLK CSYNC V CC X1 X2 ASYNC EFI F/C OSC RES RESET S2/STOPS1S0SLO/FSTSTARTCLK50 GND CLK AEN2 RDY2 READY RDY1