CS82C84A

82C84A INTERSIL | Alldatasheet

Document overview

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Technical content

Features

• Generates the System Clock For CMOS or NMOS Microprocessors
• Up to 25MHz Operation
• Uses a Parallel Mode Crystal Circuit or External Frequency Source
• Provides Ready Synchronization
• Generates System Reset Output From Schmitt Trigger Input
• TTL Compatible Inputs/Outputs
• Very Low Power Consumption
• Single 5V Power Supply
• Operating Temperature Ranges oC to +70oC

Description

The Intersil 82C84A is a high performance CMOS Clock Generator- driver which is designed to service the requirements of both CMOS and NMOS microprocessors such as the 80C86, 80C88, 8086 and the 8088. The chip contains a crystal controlled oscillator, a divide-by- three counter and complete “Ready” synchronization and reset logic. Static CMOS circuit design permits operation with an external fre- quency source from DC to 25MHz. Crystal controlled operation to 25MHz is guaranteed with the use of a parallel, fundamental mode crystal and two small load capacitors. All inputs (except X1 and RES) are TTL compatible over tempera- ture and voltage ranges. Power consumption is a fraction of that of the equivalent bipolar cir- cuits. This speed-power characteristic of CMOS permits the designer to custom tailor his system design with respect to power and/or speed requirements.

Ordering Information

NUMBER TEMP. RANGE PACKAGE PKG. NO. CP82C84A 0 oC to +70oC 18 Ld PDIP E18.3 IP82C84A -40 oC to +85oC E18.3 CS82C84A 0 oC to +70oC 20 Ld PLCC N20.35 IS82C84A -40 oC to +85oC N20.35 CD82C84A 0 oC to +70oC 18 Ld CERDIP F18.3 ID82C84A -40 oC to +85oC F18.3 MD82C84A/B -55 oC to +125oC F18.3 8406801VA SMD# F18.3 MR82C84A/B -55 oC to +125oC 20 Pad CLCC J20.A 84068012A SMD# J20.A Pinouts 82C84A (PDIP, CERDIP) TOP VIEW 82C84A (PLCC, CLCC) TOP VIEW

1 VCC

File Number 2974.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

CONTROL PIN LOGICAL 1 LOGICAL 0 F/C External Clock Crystal Drive RES Normal Reset RDY1, RDY2 Bus Ready Bus Not Ready AEN1, AEN2 Address Disabled Address Enable ASYNC 1 Stage Ready Synchronization

2 Stage Ready

D CK DQ FF2 Q 10RES F/C AEN1 AEN2 ASYNC SYNC ÷ 2 SYNC ÷ 3 82C84A

SYMBOL NUMBER TYPE DESCRIPTION AEN1, AEN2 3, 7 I ADDRESS ENABLE: AEN is an active LOW signal.AEN serves to qualify its respective Bus Ready Signal (RDY1 or RDY2).AEN1 validates RDY1 whileAEN2 validates RDY2. TwoAEN signal inputs are useful in system configurations which permit the processor to access two Multi- Master System Busses. In non-Multi-Master configurations, the AEN signal inputs are tied true (LOW). RDY1, RDY2 4, 6 I BUS READY (Transfer Complete). RDY is an active HIGH signal which is an indication from a device located on the system data bus that data has been received, or is available RDY1 is qual- ified by AEN1 while RDY2 is qualified byAEN2. ASYNC 15 I READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization mode of the READY logic. WhenASYNC is low, two stages of READY synchronization are pro- vided. WhenASYNC is left open or HIGH, a single stage of READY synchronization is provided. READY 5 O READY: READY is an active HIGH signal which is the synchronized RDY signal input. READY is cleared after the guaranteed hold time to the processor has been met. X1, X2 17, 16 I O CRYSTAL IN: X1 and X2 are the pins to which a crystal is attached. The crystal frequency is 3 times the desired processor clock frequency, (Note 1). F/C 13 I FREQUENCY/CRYSTAL SELECT: F/ C is a strapping option. When strapped LOW. F/C permits the processor’s clock to be generated by the crystal. When F/C is strapped HIGH, CLK is gen- erated for the EFI input, (Note 1). EFI 14 I EXTERNAL FREQUENCY IN: When F/ C is strapped HIGH, CLK is generated from the input fre- quency appearing on this pin. The input signal is a square wave 3 times the frequency of the de- sired CLK output. CLK 8 O PROCESSOR CLOCK: CLK is the clock output used by the processor and all devices which di- rectly connect to the processor’s local bus. CLK has an output frequency which is 1/3 of the crys- tal or EFI input frequency and a 1/3 duty cycle. PCLK 2 O PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is 1/2 that of CLK and has a 50% duty cycle. OSC 12 O OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is equal to that of the crystal. RES 11 I RESET IN: RES is an active LOW signal which is used to generate RESET. The 82C84A pro- vides a Schmitt trigger input so that an RC connection can be used to establish the power-up reset of proper duration. RESET 10 O RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its timing characteristics are determined by RES. CSYNC 1 I CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple 82C84As to be synchronized to provide clocks that are in phase. When CSYNC is HIGH the internal counters are reset. When CSYNC goes LOW the internal counters are allowed to resume count- ing. CSYNC needs to be externally synchronized to EFI. When using the internal oscillator CSYNC should be hardwired to ground. GND 9 Ground V CC 18 V CC : The +5V power supply pin. A 0.1µF capacitor between VCC and GND is recommended for decoupling. NOTE: 1. If the crystal inputs are not used X1 must be tied to VCC or GND and X2 should be left open. 82C84A

crystal from which the basic operating frequency is derived. ble, crystal-controlled source. tolerance specified by the crystal manufacturer. section can be used independently for another clock source. eral clock signal whose output frequency is 1/2 that of CLK. CLK, after which time the READY output will go active (HIGH). the required RDY setup time. TABLE 1. CRYSTAL SPECIFICATIONS FIGURE 1. CSYNC SYNCHRONIZATION then EFI should be tied to VCC or GND.

Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range oC to +70oC oC to +150oC (PLCC - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TA = 0oC to +70oC (C82C84A), TA = -40oC to +85oC (I82C84A), TA = -55oC to +125oC (M82C84A) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 2.0 2.2 V C82C84A, I82C84 M82C84A, Notes 1, 2 VIL Logical Zero Input Voltage - 0.8 V Notes 1, 2, 3 VIHR Reset Input High Voltage V CC -0.8 - V VILR Reset Input Low Voltage - 0.5 V VT+ - VT- Reset Input Hysteresis 0.2 V CC -- VOH Logical One Output Current V CC -0.4 - V I OH = -4.0mA for CLK Output IOH = -2.5mA for All Others VOL Logical Zero Output Voltage - 0.4 V I OL = +4.0mA for CLK Output IOL = +2.5mA for All Others II Input Leakage Current -1.0 1.0 µAV IN = VCC or GND exceptASYNC, X1: (Note 4) ICCOP Operating Power Supply Current - 40 mA Crystal Frequency = 25MHz Outputs Open, Note 5 NOTES: 2. Due to test equipment limitations related to noise, the actual tested value may differ from that specified, but the specified limit is guaranteed. 3. CSYNC pin is tested with VIL≤ 0.8V. 4. ASYNC pin includes an internal 17.5kΩ nominal pull-up resistor. ForASYNC input at GND,ASYNC input leakage current = 300µA nominal, X1 - crystal feedback input. 5. f = 25MHz may be tested using the extrapolated value based on measurements taken at f = 2MHz and f = 10MHz. CapacitanceTA = +25oC SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS C IN Input Capacitance 10 pF FREQ = 1MHz, all measurements are referenced to device GND COUT Output Capacitance 15 pF 82C84A

TA = 0oC to +70oC (C82C84A), TA = -40oC to +85oC (I82C84A), TA = -55oC to +125oC (M82C84A) SYMBOL PARAMETER LIMITS UNITS (NOTE 1) TEST CONDITIONSMIN MAX TIMING REQUIREMENTS (1) TEHEL External Frequency HIGH Time 13 - ns 90%-90% V IN (2) TELEH External Frequency LOW Time 13 - ns 10%-10% V IN (3) TELEL EFI Period 36 - ns XTAL Frequency 2.4 25 MHz Note 2 (4) TR2VCL RDY1, RDY2 Active Setup to CLK 35 - ns ASYNC = HIGH (5) TR1VCH RDY1, RDY2 Active Setup to CLK 35 - ns ASYNC = LOW (6) TR1VCL RDY1, RDY2 Inactive Setup to CLK 35 - ns (7) TCLR1X RDY1, RDY2 Hold to CLK 0 - ns (8) TAYVCL ASYNC Setup to CLK 50 - ns (9) TCLAYX ASYNC Hold to CLK 0 - ns (10) TA1VR1V AEN1, AEN2 Setup to RDY1, RDY2 15 - ns (11) TCLA1X AEN1, AEN2 Hold to CLK 0 - ns (12) TYHEH CSYNC Setup to EFI 20 - ns (13) TEHYL CSYNC Hold to EFI 20 - ns (14) TYHYL CSYNC Width 2 TELEL - ns (15) TI1HCL RES Setup to CLK 65 - ns Note 3 (16) TCLI1H RES Hold to CLK 20 - ns Note 3 TIMING RESPONSES (17) TCLCL CLK Cycle Period 125 - ns Note 6 (18) TCHCL CLK HIGH Time (1/3 TCLCL) +2.0 - ns Note 6 (19) TCLCH CLK LOW Time (2/3 TCLCL) -15.0 - ns Note 6 (20) (21) TCH1CH2 TCL2CL1 CLK Rise or Fall Time - 10 ns 1.0V to 3.0V (22) TPHPL PCLK HIGH Time TCLCL-20 - ns Note 6 (23) TPLPH PCLK LOW Time TCLCL-20 - ns Note 6 (24) TRYLCL Ready Inactive to CLK (See Note 4) -8 - ns Note 4 (25) TRYHCH Ready Active to CLK (See Note 3) (2/3 TCLCL) -15.0 - ns Note 5 (26) TCLIL CLK to Reset Delay - 40 ns (27) TCLPH CLK to PCLK HIGH Delay - 22 ns (28) TCLPL CLK to PCLK LOW Delay - 22 ns (29) TOLCH OSC to CLK HIGH Delay -5 22 ns (30) TOLCL OSC to CLK LOW Delay 2 35 ns NOTES: 1. Tested as follows: f = 2.4MHz, V 2. Tested using EFI or X1 input pin. 3. Setup and hold necessary only to guarantee recognition at next clock. 4. Applies only to T2 states. 5. Applies only to T3 TW states. 6. Tested with EFI input frequency = 4.2MHz. 82C84A

NOTES: VCC = 5.5V±0.5V, GND = 0V. VIH = 4.5V±10%. VIL = -0.2 to 0.4V. R1 = 47kΩ ,±5%. R2 = 10kΩ ,±5%. R3 = 2.2kΩ ,±5%. R4 = 1.2kΩ ,±5%. C1 = 0.01µF (minimum). F0 = 100kHz±10%. R2R2 VCC VCC GND VCC GND F11 F10 OPEN F12 VCC GND VCC GND VCC GND 91 0 1 1 1 2 13 321 2 0 1 9 VCC C1 OPEN VCC / 2 VCC / 2 F12 VCC / 2 VCC / 2 OPEN F11 F10 OPEN VCC / 2 82C84A

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Die Characteristics DIE DIMENSIONS: 66.1 x 70.5 x 19 ±1mils METALLIZATION: Type: Si - AI Thickness: 11k Å ± 1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ WORST CASE CURRENT DENSITY: 1.42 x 105 A/cm2 Metallization Mask Layout 82C84A AEN1 PCLK CSYNC V CC X1 RDY1 READY RDY2 AEN2 CLK GND RESET RES OSC ASYNC EFI F/C 82C84A