CS82C55A

82C55A_06 INTERSIL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 29

Technical content

Features

• Pb-Free Plus Anneal Available (RoHS Compliant) (See Ordering Info)
• Pin Compatible with NMOS 8255A
• 24 Programmable I/O Pins
• Fully TTL Compatible
• High Speed, No “Wait State” Operation with 5MHz and 8MHz 80C86 and 80C88
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• L7 Process
• 2.5mA Drive Capability on All I/O Ports

Ordering Information

TEMP . RANGE (°C) PACKAGE PKG. DWG. #5MHz PART MARKING 8MHz PART MARKING CP82C55A-5 CP82C55A-5 CP82C55A CP82C55A 0 to +70 40 Ld PDIP E40.6 CP82C55A-5Z (Note) CP82C55A-5Z CP82C55AZ (Note) CP82C55AZ 0 to +70 40 Ld PDIP (Pb-free) IP82C55A IP82C55A -40 to +85 40 Ld PDIP IP82C55AZ (Note) IP82C55AZ -40 to +85 40 Ld PDIP (Pb-free) CS82C55A-5* CS82C55A-5 CS82C55A* CS82C55A* 0 to +70 44 Ld PLCC N44.65 CS82C55A-5Z* (Note) CS82C55A-5Z CS82C55AZ* (Note) CS82C55AZ 0 to +70 44 Ld PLCC (Pb-free) IS82C55A-5* IS82C55A-5 IS82C55A* IS82C55A* -40 to +85 44 Ld PLCC IS82C55A-5Z* (Note) IS82C55A-5Z IS82C55AZ* (Note) IS82C55AZ -40 to +85 44 Ld PLCC (Pb-free) CQ82C55A* CQ82C55A* 0 to +70 44 Ld MQFP Q44.10x10 CQ82C55AZ (Note) CQ82C55AZ 0 to +70 44 Ld MQFP (Pb-free) IQ82C55A* IQ82C55A* -40 to +85 44 Ld MQFP IQ82C55AZ* (Note) IQ82C55AZ -40 to +85 44 Ld MQFP (Pb-free) ID82C55A ID82C55A -40 to +85 40 Ld CERDIP F40.6 MD82C55A/B MD82C55A/B -55 to +125 8406602QA 8406602QA SMD# 8406602XA 8406602XA SMD# 44 Ld CLCC J44.A *Add “96” suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb- free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet November 16, 2006

2 FN2969.10 November 16, 2006 Pinouts 82C55A (PDIP, CERDIP) TOP VIEW 82C55A (CLCC) TOP VIEW 82C55A (PLCC) TOP VIEW 82C55A (MQFP) TOP VIEW PA3 PA2 PA1 PA0 RD CS GND PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 PA4 PA5 PA6 PA7 WR RESET V CC PB7 PB6 PB5 PB4 PB3 4065 321 4 4 4 3 4 2 4 14 18 19 20 21 22 23 24 25 26 27 28 GND NC PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 V CC NC NC RESET NC CS RD PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 WR CS GND PC7 PC6 PC5 PC4 PC0 PC1 PC3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 NC NC RESET V CC RD PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 WR NC PC2 NC 44 43 42 41 40 2827 123456 262524232221201918 PC6 PC7 GND CS 1 12 13 14 15 16 17 PC5 PC4 PC0 PC1 PC2

2221201918 PB7

V CC 39 38 37 36 35 34 44 43 42 41 40 NC PA4 PA5 PA6 PA7 WR RESET RD PA0 PA1 PA2 PA3 NC PB3 PB4 PB5 PB6 NC NC PC3 PB0 PB1 PB2 82C55A

3 FN2969.10 November 16, 2006 Functional Diagram Pin Description SYMBOL TYPE DESCRIPTION VCC VCC: The +5V power supply pin. A 0.1 μF capacitor between VCC and GND is recommended for decoupling. GND GROUND D0-D7 I/O DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the system data bus. RESET I RESET: A high on this input clears the control register and al l ports (A, B, C) are set to the input mode with the “Bus Hold” circuitry turned on. CS I CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the Data Bus for CPU communications. RD I READ: Read is an active low input control signal used by th e CPU to read status information or data via the data bus. WR I WRITE: Write is an active low input c ontrol signal used by the CPU to load control words and data into the 82C55A. A0-A1 I ADDRESS: These input signal s, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. A0 and A1 are normally connected to the least significant bits of the Address Bus A0, A1. PA0-PA7 I/O PORT A: 8-bit input and output port. Both bus hol d high and bus hold low circuitry are present on this port. PB0-PB7 I/O PORT B: 8-bit input and output port. Bus hol d high circuitry is present on this port. PC0-PC7 I/O PORT C: 8-bit input and output port. Bus hold circuitry is present on this port. GROUP A PORT A (8) GROUP A PORT C UPPER (4) GROUP B PORT C LOWER (4) GROUP B PORT B (8) GROUP B CONTROL GROUP A CONTROL DATA BUS BUFFER READ WRITE CONTROL LOGIC RD WR RESET CS D7-D0 POWER SUPPLIES +5V GND BIDIRECTIONAL DATA BUS I/O PA7-PA0 I/O PC7-PC4 I/O PC3-PC0 I/O PB7-PB0 8-BIT INTERNAL DATA BUS 82C55A

information are also transferred through the data bus buffer. external transfers of both Data and Control or Status words. and in turn, issues commands to both of the Control Groups. communication between the 82C55A and the CPU. essence, it allows the CPU to “read from” the 82C55A. write data or control words into the 82C55A. bits of the address bus (A0 and A1). initializes the functional configuration of the 82C55A. proper commands to its associated ports. control word format for both Read and Write operations. “1”, as this implies control word mode information. are present on Port A. See Figure 2A. data input buffer. See Figure 2B.

00010 P o r t A → Data Bus

01010 P o r t B → Data Bus

10010 P o r t C → Data Bus

11010 C o n t r o l W o r d → Data Bus

00100 D a t a B u s → Port A

01100 D a t a B u s → Port B

10100 D a t a B u s → Port C

11100 D a t a B u s → Control

FIGURE 1. 82C55A BLOCK DIAGRAM. DATA BUS BUFFER,

support almost any peripheral device with no external logic. requirements in control-based applications. operation just as if they were output ports. the bit set/reset function of port C. other device in the interrupt structure. written to or read from a specific port.

• Two 8-bit ports and two 4-bit ports
• Any Port can be input or output
• Outputs are latched
• Inputs are not latched
• 16 different Input/Output configurations possible

FIGURE 5. BIT SET/RESET FORMAT

7 FN2969.10 November 16, 2006 Mode 0 (Basic Input) Mode 0 (Basic Output) Mode 0 Configurations CONTROL WORD #0 CONTROL WORD #2 CONTROL WORD #1 CONTROL WORD #3 tRA tHR tRR tIR tAR tRD tDF RD INPUT CS, A1, A0 D7-D0 tAW tWA tWB tWW tWDtDW WR D7-D0 CS, A1, A0 OUTPUT PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C 82C55A

8 FN2969.10 November 16, 2006 CONTROL WORD #4 CONTROL WORD #8 CONTROL WORD #5 CONTROL WORD #9 CONTROL WORD #6 CONTROL WORD #10 CONTROL WORD #7 CONTROL WORD #11 Mode 0 Configurations (Continued) PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C 82C55A

• Two Groups (Group A and Group B)
• Each group contains one 8-bit port and one 4-bit control/data port
• The 8-bit data port can be either input or output. Both inputs and outputs are latched.
• The 4-bit port is used for control and status of the 8-bit port. Input Control Signal Definition (Figures 6 and 7) STB (Strobe Input) A “low” on this input loads data into the input latch. IBF (Input Buffer Full F/F) A “high” on this output indicates that the data has been loaded into the input latch: in essence, an acknowledgment. IBF is set by STB input being low and is reset by the rising edge of the RD input. CONTROL WORD #12 CONTROL WORD #14 CONTROL WORD #13 CONTROL WORD #15 Mode 0 Configurations (Continued) PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C PA7 - PA0 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 - D0 82C55A A B C

FIGURE 6. MODE 1 INPUT

FIGURE 14. MODE 2 COMBINATIONS

FIGURE 23. BASIC FLOPPY DISC INTERFACE FIGU RE 24. MACHINE TOOL CONTROLLER INTERFACE

18 FN2969.10 November 16, 2006 Absolute Maximum Ratings TA = +25°C Thermal Information Operating Conditions Operating Temperature Range Die Characteristics Thermal Resistance (Typical, Note 1) θJA (°C/W) θJC(°C/W) Maximum Junction Temperature (PLCC and MQFP Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VCC = 5.0V ±10%; TA = Operating Temperature Range SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNITS VIH Logical One Input Voltage 2.0 2.2 VIL Logical Zero Input Voltage -0 . 8 V VOH Logical One Output Voltage I OH = -2.5mA, IOH = -100μA 3.0 VCC -0.4 VOL Logical Zero Output Voltage I OL +2.5mA - 0.4 V II Input Leakage Current V IN = VCC or GND, RD, CS, A1, A0, RESET, WR -1.0 +1.0 μA IO I/O Pin Leakage Current VO = V CC or GND, D0 - D7 -10 +10 μA IBHH Bus Hold High Current VO = 3.0V. Ports A, B, C TA = -55°C -50 -450 μA TA = +128°C -50 -400 μA IBHL Bus Hold Low Current VO = 1.0V. Port A ONLY TA = -55°C 50 450 μA TA = +128°C 50 400 μA IDAR Darlington Drive Current Ports A, B, C. Test Condition 3 -2.5 Note 2, 4 mA ICCSB Standby Power Supply Current V CC = 5.5V, VIN = VCC or GND. Output Open - 10 μA ICCOP Operating Power Supply Current T A = +25°C, VCC = 5.0V, Typical (See Note 3) - 1 mA/MHz NOTES: 2. No internal current limiting exists on Port Outputs. A resistor must be added externally to limit the current. 3. ICCOP = 1mA/MHz of Peripheral Read/Write cycle time. (Example: 1.0 μs I/O Read/Write cycle time = 1mA). 4. Tested as VOH at -2.5mA. Capacitance TA = +25°C SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CIN Input Capacitance 10 pF FREQ = 1MHz, All Measurements are referenced to device GNDCI/O I/O Capacitance 20 pF 82C55A

19 FN2969.10 November 16, 2006 SYMBOL PARAMETER 82C55A-5 82C55A UNITS TEST CONDITIONSMIN MAX MIN MAX READ TIMING (1) tAR Address Stable Before RD 0-0- n s (2) tRA Address Stable After RD 0-0- n s (3) tRR RD Pulse Width 250 - 150 - ns (4) tRD Data Valid From RD - 200 - 120 ns 1 (5) tDF Data Float After RD 10 75 10 75 ns 2 (6) tRV Time Between RD s and/or WRs 300 - 300 - ns WRITE TIMING (7) tAW Address Stable Before WR 0-0- n s (8) tWA Address Stable After WR 20 - 20 - ns (9) tWW WR Pulse Width 100 - 100 - ns (10) tDW Data Valid to WR High 100 - 100 - ns (11) tWD Data Valid After WR High 30 - 30 - ns OTHER TIMING (12) tWB WR = 1 to Output - 350 - 350 ns 1 (13) tIR Peripheral Data Before RD 0-0- n s (14) tHR Peripheral Data After RD 0-0- n s (15) tAK ACK Pulse Width 200 - 200 - ns (16) tST STB Pulse Width 100 - 100 - ns (17) tPS Peripheral Data Before STB High 20 - 20 - ns (18) tPH Peripheral Data After STB High 50 - 50 - ns (19) tAD ACK = 0 to Output - 175 - 175 ns 1 (20) tKD ACK = 1 to Output Float 20 250 20 250 ns 2 (21) tWOB WR = 1 to OBF = 0 - 150 - 150 ns 1 (22) tAOB ACK = 0 to OBF = 1 - 150 - 150 ns 1 (23) tSIB STB = 0 to IBF = 1 - 150 - 150 ns 1 (24) tRIB RD = 1 to IBF = 0 - 150 - 150 ns 1 (25) tRIT RD = 0 to INTR = 0 - 200 - 200 ns 1 (26) tSIT STB = 1 to INTR = 1 - 150 - 150 ns 1 (27) tAIT ACK = 1 to INTR = 1 - 150 - 150 ns 1 (28) tWIT WR = 0 to INTR = 0 - 200 - 200 ns 1 (29) tRES Reset Pulse Width 500 - 500 - ns 1, (Note) NOTE: Period of initial Reset pulse after power-on must be at least 50 μsec. Subsequent Reset pulses may be 500ns minimum. 82C55A

FIGURE 30. WRITE TIMING FIGURE 31. READ TIMING and FALL times are driven at 1ns/V.

23 FN2969.10 November 16, 2006 Burn-In Circuits CERDIP NOTES: 1. V CC = 5.5V ± 0.5V 3. VIL = -0.2V to 0.4V 4. GND = 0V CLCC NOTES: 1. C1 = 0.01 μF minimum 2. All resistors are 47k Ω ± 5% 3. f0 = 100kHz ± 10% GND F10 F10 F12 F13 F14 F15 F11 F12 F13 F14 F15 F11 F12 VCC F13 F14 F15 F11 F12 F11 F10 VCC F13 F14 F10 F12 F11 F15 GND F10 F10 46 3 1 4041424344 2827262524232221201918 F12 F13 F14 F15 F12 F13 F14 F15 F11 F12 F11 F11 82C55A

24 FN2969.10 November 16, 2006 Die Characteristics METALLIZATION: Type: Silicon - Aluminum Thickness: 11kÅ ±1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ Metallization Mask Layout 82C55A RD PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 WR CS GND PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 V CC RESET 82C55A

25 FN2969.10 November 16, 2006 82C55A Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be per- pendicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dam- bar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E40.6 (JEDEC MS-011-AC ISSUE B)

40 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.250 - 6.35 4 A1 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.030 0.070 0.77 1.77 8 C 0.008 0.015 0.204 0.381 - D 1.980 2.095 50.3 53.2 5 D1 0.005 - 0.13 - 5 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N4 0 4 0 9 Rev. 0 12/93

26 FN2969.10 November 16, 2006 82C55A Ceramic Dual-In-Line Frit Seal Packages (CERDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead di mensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE -D--A- -C- -B- α D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 A M S S ccc C A - BM DS S aaa CA - BM DS S eA F40.6 MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A)

40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

A - 0.225 - 5.72 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 2.096 - 53.24 5 E 0.510 0.620 12.95 15.75 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.070 0.38 1.78 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N4 0 4 0 8 Rev. 0 4/94

27 FN2969.10 November 16, 2006 82C55A Ceramic Leadless Chip Carrier Packages (CLCC) D j x 45o B h x 45o A A1 E L L3 e PLANE 2 PLANE 1

0.010 E HS S

0.010 E FS S

-E-

0.007 E FM S HS

-H- -F- J44.A MIL-STD-1835 CQCC1-N44 (C-5)

44 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE

A 0.064 0.120 1.63 3.05 6, 7 A1 0.054 0.088 1.37 2.24 - B 0.033 0.039 0.84 0.99 4 B1 0.022 0.028 0.56 0.71 2, 4 B2 0.072 REF 1.83 REF - B3 0.006 0.022 0.15 0.56 - D 0.640 0.662 16.26 16.81 - D1 0.500 BSC 12.70 BSC - D2 0.250 BSC 6.35 BSC - D3 - 0.662 - 16.81 2 E 0.640 0.662 16.26 16.81 - E1 0.500 BSC 12.70 BSC - E2 0.250 BSC 6.35 BSC - E3 - 0.662 - 16.81 2 e 0.050 BSC 1.27 BSC - e1 0.015 - 0.38 - 2 h 0.040 REF 1.02 REF 5 j 0.020 REF 0.51 REF 5 L 0.045 0.055 1.14 1.40 - L1 0.045 0.055 1.14 1.40 - L2 0.075 0.095 1.90 2.41 - L3 0.003 0.015 0.08 0.38 - ND 11 11 3 NE 11 11 3 N4 4 4 4 3 Rev. 0 5/18/94 NOTES: 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol “N” is the maximum number of terminals. Symbols “ND” and “NE” are the number of terminals along the sides of length “D” and “E”, respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer’s option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension “A” controls the overall package thickness. The maxi- mum “A” dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH.

28 FN2969.10 November 16, 2006 82C55A Plastic Leaded Chip Carrier Packages (PLCC) NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. -C- A SEATING PLANE 0.020 (0.51) MIN VIEW “A” D2/E2 0.025 (0.64) 0.045 (1.14) R 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP EE1 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER CL D 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. 0.004 (0.10) C -C- D2/E2 CL N44.65 (JEDEC MS-018AC ISSUE A)

44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.685 0.695 17.40 17.65 - D1 0.650 0.656 16.51 16.66 3 D2 0.291 0.319 7.40 8.10 4, 5 E 0.685 0.695 17.40 17.65 - E1 0.650 0.656 16.51 16.66 3 E2 0.291 0.319 7.40 8.10 4, 5 N4 4 4 4 6 Rev. 2 11/97

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2969.10 November 16, 2006 82C55A Metric Plastic Quad Flatpack Packages (MQFP) D E E1 -A- PIN 1 A2 A1 A 12o-16o 12o-16o 0o-7o 0.40

0.016 MIN

L 0o MIN PLANE b 0.005/0.009 0.13/0.23WITH PLATING BASE METAL SEATING 0.005/0.007 0.13/0.17 -B- e 0.008

0.20 A-B SD SCM

0.076 0.003 -C- -D- -H- Q44.10x10 (JEDEC MS-022AB ISSUE B)

44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE

A - 0.096 - 2.45 - A1 0.004 0.010 0.10 0.25 - A2 0.077 0.083 1.95 2.10 - b 0.012 0.018 0.30 0.45 6 b1 0.012 0.016 0.30 0.40 - D 0.515 0.524 13.08 13.32 3 D1 0.389 0.399 9.88 10.12 4, 5 E 0.516 0.523 13.10 13.30 3 E1 0.390 0.398 9.90 10.10 4, 5 L 0.029 0.040 0.73 1.03 - N4 4 4 47 e 0.032 BSC 0.80 BSC - Rev. 2 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and toleranc es per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane . 4. Dimensions D1 and E1 to be determined at datum plane 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. -C- -H-