82C87H INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Full Eight Bit Bi-Directional Bus Interface
  • Industry Standard 8287 Compatible Pinout
  • High Drive Capability - B Side I
  • Three-State Inverting Outputs
  • Gated Inputs - Reduce Operating Power - Eliminate the Need for Pull-Up Resistors
  • Single 5V Power Supply
  • Operating Temperature Range oC to +70oC

Description

The Intersil 82C87H is a high performance CMOS Octal Transceiver manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C87H provides a full eight-bit bi-directional bus interface in a 20 pin package. The Transmit (T) control determines the data direction. The active low output enable ( OE) permits simple interface to the 80C86, 80C88 and other microprocessors. The 82C87H has gated inputs, eliminating the need for pull-up/pull-down resis- tors and reducing overall system operating power dissipation. The 82C87H provides inverted data at the outputs.

Ordering Information

TEMP. RANGE PKG. NO.5MHz 8MHz CP82C87H-5 CP82C87H 20 Ld PDIP 0oC to +70oC E20.3 IP82C87H-5 IP82C87H -40 oC to +85oC E20.3 CS82C87H-5 CS82C87H 20 Ld PLCC 0oC to +70oC N20.35 IS82C87H-5 IS82C87H -40 oC to +85oC N20.35 CD82C87H-5 CD82C87H 20 Ld CERDIP 0oC to +70oC F20.3 ID82C87H-5 ID82C87H -40 oC to +85oC F20.3 MD82C87H-5/B - -55 oC to +125oC F20.3 5962- 8757702RA - SMD # F20.3 MR82C87H-5/B - 20 Pad CLCC -55oC to +125oC J20.A 5962- 87577022A - SMD # J20.A CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

82C87H (PDIP, CERDIP) TOP VIEW 82C87H (PLCC, CLCC) TOP VIEW 1A0 OE GND VCC T 193 2 201 9 10 11 12 13 OE GND T V CC TRUTH TABLE T OE A B X H Hi-Z Hi-Z HL IO LLOI H = Logic One L = Logic Zero I = Input Mode O = Output Mode X = Don’t Care Hi-Z = High Impedance PIN NAMES PIN DESCRIPTION A 0-A7 Local Bus Data I/O Pins B0-B7 System Bus Data I/O Pins T Transmit Control Input OE Active Low Output Enable 82C87H82C87H

Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range oC to +70oC Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) oC to +150oC (PLCC - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TA = -40oC to +85oC (I82C87H); TA = -55oC to +125oC (M82C87H) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One 2.0 - V C82C87H, I82C87H Input Voltage 2.2 - V M82C87H (Note 1) VIL Logical Zero Input Voltage - 0.8 V VOH Logical One Output Voltage B Outputs 3.0 - V I OH = -8mA A Outputs 3.0 - V I OH = -4mA A or B Outputs V CC -0.4 - V I OH = -100µA VOL Logical Zero Output Voltage B Outputs - 0.45 V I OL = 20mA A Outputs - 0.45 V I OL = 12mA II Input Leakage Current -10.0 10.0 µAV IN = GND or VCC DIP Pins 9, 11 IO Output Leakage Current -10.0 10.0 µA VO = GND or V CC ,OE ≥ VCC -0.5V DIP Pins 1 - 8, 12 - 19 ICCSB Standby Power Supply Current -1 0 µAV IN = VCC or GND, VCC = 5.5V, Outputs Open ICCOP Operating Power Supply Current - 1 mA/MHz T A = +25oC, Typical (See Note 2) NOTES: 1. VIH is measured by applying a pulse of magnitude = VIH(MIN) to one data input at a time and checking the corresponding device output for a valid logical “1” during valid input high time. Control pins (T,OE) are tested separately with all device data input pins at VCC -0.4. 2. Typical ICCOP = 1mA/MHz of read/ cycle time. (Example: 1.0µs read/write cycle time = 1mA). Capacitance TA = +25oC SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CIN Input Capacitance B Inputs 18 pF Freq = 1MHz, all measurements are referenced to device GND A Inputs 14 pF 82C87H82C87H

Freq = 1MHz T A = -40oC to +85oC (I82C87H); TA = -55oC to +125oC (M82C87H) SYMBOL PARAMETER MIN NOTE 4 UNITS TEST CONDITIONS 82C87H MAX 82C87H-5 MAX (1) TIVOV Input to Output Delay Notes 1, 2 Inverting 5 30 35 ns Non-Inverting 5 32 35 ns (2) TEHTV Transmit/Receive Hold Time 5 - - ns Notes 1, 2 (3) TTVEL Transmit/Receive Setup Time 10 - - ns Notes 1, 2 (4) TEHOZ Output Disable Time 5 30 35 ns Notes 1, 2 (5) TELOV Output Enable Time 10 50 65 ns Notes 1, 2 (6) TR, TF Input Rise/Fall Times - 20 20 ns Notes 1, 2 (7) TEHEL Minimum Output Enable High Time Note 3 82C87H 30 - - ns 82C87H-5 35 - - ns NOTES: 1. All AC parameters tested as per test circuits and definitions in timing waveforms and test load circuits. Input rise and fall times are driven at 1ns/V. 2. Input test signals must switch between V IL - 0.4V and VIH +0.4V. 3. A system limitation only when changing direction. Not a measured parameter. 4. 82C87H is available in commercial and industrial temperature ranges only. 82C87H-5 is available in commercial, industrial and military temperature ranges. INPUTS TR, TF (6) 2.0V 0.8V VOH -0.1V TELOV (5) VOL +0.1V TTVEL (3) 3.0V 0.45VOUTPUTS T TEHEL (7) TIVOV (1) TEHOZ (4) TEHTV (2) OE 82C87H82C87H

NOTE: Includes jig and stray capacitance. Burn-In Circuits MD82C87H CERDIP OUTPUT TEST POINT 2.36V 100pF 160Ω (SEE NOTE) OUTPUT TEST POINT 1.5V 100pF 375Ω (SEE NOTE) OUTPUT TEST POINT 1.5V 100pF 91Ω (SEE NOTE) OUTPUT TEST POINT 2.36V 50pF 160Ω (SEE NOTE) OUTPUT TEST POINT 2.27V 300pF 91Ω (SEE NOTE) OUTPUT TEST POINT 1.5V 300pF 180Ω (SEE NOTE) OUTPUT TEST POINT 1.5V 300pF 51Ω (SEE NOTE) OUTPUT TEST POINT 2.27V 50pF 91Ω (SEE NOTE) VCC A A A A A A A A VCC VCC A 82C87H82C87H

NOTES: 1. VCC = 5.5V± 0.5V, GND = 0V 2. VIH = 4.5V± 10% 3. VIL = -0.2V to 0.4V 4. R1 = 47kΩ± 5% 5. R2 = 2.4kΩ± 5% 6. R3 = 1.5kΩ± 5% 7. R4 = 1kΩ± 5% 8. R5 = 5kΩ± 5% 9. C1 = 0.01µF minimum 10. F0 = 100kHz± 10% Burn-In Circuits (Continued) 91 01 1 1 2 13 VCC C1 F2 F2 R5 R5 F1F0 F3 R4R4 R5 R5 321 2 0 1 9 82C87H82C87H

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Die Characteristics DIE DIMENSIONS: 138.6 x 155.5 x 19± 1mils METALLIZATION: Type: Si - Al Thickness: 11k Å ± 1kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ WORST CASE CURRENT DENSITY: 1.47 x 105 A/cm2 Metallization Mask Layout 82C87H A2 A1 A0 V CC B0 B1 B6B7TGNDOEA7 82C87H82C87H