82C88 INTERSIL | Alldatasheet
Document overview
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- PDF pages: 10
Technical content
Features
- Compatible with Bipolar 8288
- Performance Compatible with: - 8089
- Provides Advanced Commands for Multi-Master Busses
- Three-State Command Outputs
- Bipolar Drive Capability
- Scaled SAJI IV CMOS Process
- Single 5V Power Supply
- Low Power Operation
- Operating Temperature Ranges oC to +70oC
Description
The Intersil 82C88 is a high performance CMOS Bus Con- troller manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). The 82C88 provides the control and command timing signals for 80C86, 80C88, 8086, 8088, 8089, 80186, and 80188 based systems. The high output drive capability of the 82C88 eliminates the need for addi- tional bus drivers. Static CMOS circuit design insures low operating power. The Intersil advanced SAJI process results in performance equal to or greater than existing equivalent products at a significant power savings. Pinouts
20 LEAD PDIP, CERDIP
20 LEAD PLCC, CLCC
Ordering Information
PKG. NO. CP82C88 20 Ld PDIP 0 oC to +70oC E20.3 CP82C88-10 0 oC to +70oC E20.3 IP82C88 -40 oC to +85oC E20.3 CS82C88 20 Ld PLCC 0oC to +70oC N20.35 IS82C88 -40 oC to +85oC N20.35 CD82C88 20 Ld CERDIP 0oC to +70oC F20.3 ID82C88 -40 oC to +85oC F20.3 MD82C88/B -55 oC to +125oC F20.3 8406901RA SMD# F20.3 MR82C88/B 20 Pad CLCC -55 oC to +125oC J20.A 84069012A SMD# J20.A 1IOB CLK ALE GND DT/ R AEN MRDC AMWC MWTC VCC MCE/ PDEN DEN CEN IORC AIOWC IOWC INTA S2 4 91 0 1 1 1 2 13 321 2 0 1 9 ALE DT/ R AEN MRDC AMWC GND IORC AIOWC IOWC MWTC VCC IOB CLK DEN CEN MCE/ PDEN INTA File Number 2979.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999
SYMBOL NUMBER TYPE DESCRIPTION VCC 20 V CC : The +5V power supply pin. A 0.1µF capacitor between pins 10 and 20 is recommended for decoupling. GND 10 GROUND. S0,S1,S2 19, 3, 18 I STATUS INPUT PINS: These pins are the input pins from the 80C86, 80C88,8086/88, 8089 processors. The 82C88 decodes these inputs to generate command and control signals at the appropriate time. When Status pins are not in use (passive), command outputs are held HIGH (See Table1). CLK 2 I CLOCK: This is a CMOS compatible input which receives a clock signal from the 82C84A or 82C85 clock generator and serves to establish when command/control signals are generated. ALE 5 O ADDRESS LATCH ENABLE: This signal serves to strobe an address into the address latches. This sig- nal is active HIGH and latching occurs on the falling (HIGH to LOW) transition. ALE is intended for use with transparent D type latches, such as the 82C82 and 82C83H. DEN 16 O DATA ENABLE: This signal serves to enable data transceivers onto either the local or system data bus. This signal is active HIGH. DT/ R 4 O DATA TRANSMIT/RECEIVE: This signal establishes the direction of data flow through the transceivers. A HIGH on this line indicates Transmit (write to I/O or memory) and a LOW indicates Receive (read from I/O or memory). AEN 6 I ADDRESS ENABLE: AEN enables command outputs of the 82C88 Bus Controller a minimum of 110ns (250ns maximum) after it becomes active (LOW).AEN going inactive immediately three-states the com- mand output drivers.AEN does not affect the I/O command lines if the 82C88 is in the I/O Bus mode (IOB tied HIGH). CEN 15 I COMMAND ENABLE: When this signal is LOW all 82C88 command outputs and the DEN and PDEN con- trol outputs are forced to their Inactive state. When this signal is HIGH, these same outputs are enabled. IOB 1 I INPUT/OUTPUT BUS MODE: When the IOB pin is strapped HIGH, the 82C88 functions in the I/O Bus mode. When it is strapped LOW, the 82C88 functions in the System Bus mode (See I/O Bus and System Bus sections). VCC GND COMMAND SIGNALS MULTIBUS TM CONTROL INPUT IOB CEN CLK AEN CONTROL SIGNAL GENERATOR DEN ALE DT/R MCE/ PDEN COMMAND SIGNAL GENERATOR AIOWC IOWC AMWC MWTC MRDC IORCS2 INTA ADDRESS LATCH, DATA TRANSCEIVER, AND INTERRUPT CONTROL SIGNALS CONTROL LOGIC STATUS DECODER 82C88 Intel™ is a Registered Trademark of Intel Corporation
determine what command is to be issued (see Table 1). bus in this configuration because no arbitration is present. AEN line is activated (LOW). AEN line) when the bus is free for use. Both memory and I/O commands wait for bus arbitration. and memory are shared by more than one processor. the data bus. This signal is active LOW. acknowledged and that it should drive vectoring information onto the data bus. This signal is active LOW. the data bus. The MCE signal is active HIGH. the data bus transceiver for the I/O bus that DEN performs for the system bus.PDEN is active LOW. TABLE 1. COMMAND DECODE DEFINITION
INTA (Interrupt Acknowledge) acts as an I/O read during an interrupt cycle. Its purpose is to inform an interrupting device that its interrupt is being acknowledged and that it should place vectoring information onto the data bus. The command outputs are: MRDC - Memory Read Command MWTC - Memory Write Command IORC - I/O Read Command IOWC - I/O Write Command AMWC - Advanced Memory Write Command AIOWC - Advanced I/O Write Command INTA - Interrupt Acknowledge Control Outputs The control outputs of the 82C88 are Data Enable (DEN), Data Transmit/Receive (DT/R) and Master Cascade Enable/ Peripheral Data Enable (MCE/PDEN). The DEN signal determines when the external bus should be enabled onto the local bus and the DT/ R determines the direction of data transfer. These two signals usually go to the chip select and direction pins of a transceiver. The MCE/ PDEN pin changes function with the two modes of the 82C88. When the 82C88 is in the IOB mode (IOB HIGH), the PDEN signal serves as a dedicated data enable signal for the I/O or Peripheral System bus. Interrupt Acknowledge and MCE The MCE signal is used during an interrupt acknowledge cycle if the 82C88 is in the System Bus mode (IOB LOW). During any interrupt sequence, there are two interrupt acknowledge cycles that occur back to back. During the first interrupt cycle no data or address transfers take place. Logic should be provided to mask off MCE during this cycle. Just before the second cycle begins the MCE signal gates a mas- ter Priority Interrupt Controller’s (PIC) cascade address onto the processor’s local bus where ALE (Address Latch Enable) strobes it into the address latches. On the leading edge of the second interrupt cycle, the addressed slave PIC gates an interrupt vector onto the system data bus where it is read by the processor. If the system contains only one PIC, the MCE signal is not used. In this case, the second Interrupt Acknowledge signal gates the interrupt vector onto the processor bus. Address Latch Enable and Halt Address Latch Enable (ALE) occurs during each machine cycle and serves to strobe the current address into the 82C82/82C83H address latches. ALE also serves to strobe the status ( S0,S1,S2) into a latch for halt state decoding. Command Enable The Command Enable (CEN) input acts as a command qualifier for the 82C88. If the CEN pin is high, the 82C88 functions normally. If the CEN pin is pulled LOW, all com- mand lines are held in their inactive state (not three-state). This feature can be used to implement memory partitioning and to eliminate address conflicts between system bus devices and resident bus devices. 82C88
Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range oC to +70oC Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) oC to +150oC Maximum Junction Temperature (PLCC - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TA = 0oC to +70oC (C82C88); TA = -40oC to +85oC (I82C88); TA = -55oC to +125oC (M82C88) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 2.0 2.2 V V C82C88, I82C88 M82C88 VIL Logical Zero Input Voltage - 0.8 V VIHC CLK Logical One Input Voltage V CC -0.8 - V VILC CLK Logical Zero Input Voltage - 0.8 V VOH Output High Voltage Command Outputs 3.0 VCC -0.4 V IOH = -8.0mA IOH = -2.5mA Output High Voltage Control Outputs 3.0 VCC -0.4 V IOH = -4.0mA IOH = -2.5mA VOL Output Low Voltage Command Outputs - 0.5 V I OL = +12.0mA Output Low Voltage Control Outputs - 0.4 V I OL = +8.0mA II Input Leakage Current -1.0 1.0 µAV IN = GND or VCC , exceptS0,S1,S2, DIP Pins 1-2, 6, 15 IBHH Input Leakage Current-Status Bus -50 -300 µAV IN = 2.0V,S0,S1,S2 (See Note 1) IO Output Leakage Current -10.0 10.0 µAV O = GND or VCC , IOB = GND,AEN = VCC , DIP Pins 7-9, 11-14 ICCSB Standby Power Supply - 10 µAV CC = 5.5V, VIN = VCC or GND, Outputs Open ICCOP Operating Power Supply Current - 1 mA/MHz V CC = 5.5V, Outputs Open (See Note 2) NOTES: 1. IBHH should be measured after raising the VIN onS0,S1,S2 to VCC and then lowering to valid input high level of 2.0V. 2. ICCOP = 1mA/MHz of CLK cycle time (TCLCL) Capacitance TA = +25oC SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CIN Input Capacitance 10 pF FREQ = 1MHz, all measurements are referenced to device GNDCOUT Output Capacitance 17 pF 82C88
and VCC -0.4V. Input rise and fall times are driven at 1ns/V.
- TAELCH measurement is between 1.5V and 2.5V.
- TAEHCZ measured at 0.5V change in VOUT.
TABLE 2. TEST CONDITION DEFINITION TABLE
Timing Waveforms (Note 3) NOTES: 1. Address/Data Bus is shown only for reference purposes. 2. Leading edge of ALE and MCE is determined by the falling edge of CLK or status going active. Whichever occurs last. 3. All timing measurements are made at 1.5V unless otherwise specified. FIGURE 1. STATE CLK S2,S1,S0 ADDRESS/DATA ALE MRDC, IORC, INTA, AMWC, AIOWC MWTC, IOWC DEN (READ) (INTA) PDEN (READ) (INTA) DEN (WRITE) PDEN (WRITE) DT/R (READ) (INTA) MCE T4 T1 T2 T3 T4 TCLCL (1) TCLCH (2) TCHCL (3) TCLSH (7) TSHCL (6)TSVCH (4) TCHSV (5) TCLLH (10) TSVLH (12) TCHLL (14) TCLML (15) TCLML (15) TCLMH (16) TCVNX (9) TCVNV (8) TCVNV (8) TCVNX (9) TCHDTH (18) TCHDTL (17) TCHDTH (18) TCLMCH (11) TSVMCH (13) TCVNX (9) 1WRITE DATA VALID ADDRESS VALID 82C88
NOTES: 1. VCC = 5.5V± 0.5V GND = 0V 2. VIH = 4.5V± 10% VIL = -0.2V to +0.4V 3. Component Values: R1 = 47kΩ , 1/4W, 5% R3 = 10kΩ , 1/4W, 5% C1 = 0.01µF (Min) F0 = 100kHz± 10% F1 = F0/2 R 3 R 3 VCC A A A VCC A A A VCC A A A A A A 91 0 1 1 1 2 13 321 2 0 1 9 VCC / 2 VCC / 2 VCC / 2 R4 R4 R4R4 VCC / 2VCC / 2 R1R4 R1 R4 VCCF0 F7F3 F4 VCC / 2 VCC / 2 VCC / 2 VCC / 2 VCC 82C88
All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Die Characteristics DIE DIMENSIONS: 103.5 x 116.5 x 19± 1mils METALLIZATION: Type: Si - Al Thickness: 11k Å ± 2kÅ GLASSIVATION: Type: Nitrox Thickness: 10k Å WORST CASE CURRENT DENSITY: 1.9 x 105 A/cm2 Metallization Mask Layout 82C88 S1 CLK IOB V CC S0 S2 MCE/ DEN CEN INTA IORCAIOWCIOWCGNDMWTCAMWC MRDC AEN ALE DT/R PDEN 82C88