X80200 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Sequence three voltage supplies independently - Core and Logic I/O VCC power sequencer for processor supplies - Power up and power down control - Voltage monitors have undervoltage lockout - Internal charge pump drives external N-channel FET switches - Cascadable to sequence more than 3 supplies - Time based or voltage based sequencing
  • Status register bits monitor gate output status
  • SMBus compatible Interface
  • Slave address identification for up to 8 power sequencers (24 supplies) on the same bus
  • Surface mount 20-pin TSSOP Package

Applications

  • Distributed Power Supply Designs
  • Multi-voltage systems
  • Multiprocessor systems
  • Embedded Processor Applications
  • Digital Signal Processors, FPGAs, ASICs, Memory Controllers
  • N + 1 Redundant Power Supplies
  • Support for SSI – Server System Infrastructure Specifications
  • -48V Hotswap Power Backplane/Distribution
  • Card Insertion Detection and Power
  • Power Sequencing DC-DC Supplies
  • Databus Power Interfacing
  • Custom Industrial Power Backplanes
  • Other: ATE, Data Acquisition, Mass Storage, Servers, Data com, Wireless Basestations VFBGND DNC SETV VDDL REF VDDM VDDH GATE_H GATEH_ENREADY GATE_M SCL SDA GATE_L ENS NC

Ordering Information

PART NUMBER UVLO H UVLOM UVLOL PACKAGE X80200V20I 4.5 3.0 0.9 TSSOP X80201V20I 4.5 2.25 0.9 TSSOP X80202V20I 3.0 2.25 1.7 TSSOP X80203V20I 3.0 2.25 0.9 TSSOP X80204V20I 3.0 0.9 0.9 TSSOP Data Sheet January 21, 2005

2 FN8154.0 Functional Diagram GATEH_EN GATE_L SCL VDDH VFB DNC GATE_M GATE_H 18 17 16 15 14 45 6 7 8 CORE-UP-FIRST CORE-DOWN-LAST UVLOH UVLOM UVLOL OSCSEQUENCE DELAY LOGIC CHARGE PUMP_M CHARGE PUMP_H CHARGE PUMP_L GND A1 A2 NC SDA STATUS REGISTER REMOTE SHUTDOWN REGISTER 2-WIRE READY VDDM VDDL SETV REF ENS12 INTERFACE Pin Descriptions PIN NAME DESCRIPTION 1 SETV Set Voltage. This pin is used for voltage based power sequencing of supplies VDDM and VDDL. If unused connect to ground. 2 REF Reference voltage. This pin is used for voltage based sequencing. The voltage on this pin is compared to the voltage on the VFB pin and provides the threshold for turn on of the GATE_M output. Either a voltage source or external resistor divider can be used to provide the reference. If time based sequencing is used this pin should be tied to VDDH. 3 A0 Slave address pin assignment. It has an Internal pull down resistor. (>10MΩ typical) 4 GND Voltage Ground. 5 A1 Slave address pin assignment. It has an Internal pull down resistor. (>10MΩ typical) 6 A2 Slave Address pin assignment. It has an Internal pull down resistor. (>10MΩ typical) 7 NC No internal connections. 8 SDA Serial bus data input/output pin. 9 SCL Serial bus clock input pin.

10 READY READY Output Pin: This open-drain ou tput pin goes LOW while VDDH is below UVLO

H and remains LOW for tPURST after VDDH goes above UVLOH. READY goes HIGH after tPURST. 11 GATEH_EN GATE_H Enable. When this pin is HIGH and VDDH > UVLO H the charge pump of the GATE_H pin turns on and the output drives HIGH. When this pin is LOW, the charge pump is disabled and the GATE_H output is LOW. An external RC time delay can be connected between the enable signal and this pin to delay the GATE_H turn on. 12 ENS Enable Sequence. This pin is used for time-based power seq uencing of supplies VDDM and VDDL. If unused, connect to ground. 13 GATE_L GATE_L Output: This output is connected to the gate of an (external) Power Switch “L”. The GATE_L pin is driven HIGH when charge pump L is enabled and pulled LOW when the charge pump is disabled. 14 GATE_H GATE_H Output: This output is connected to the gate of a (external) Power Switch “H”. The GATE_H pin driven HIGH when charge pump H is enabled and pulled LOW when the charge pump is disabled. 15 GATE_M GATE_M Output: This output is connected to the gate of a (external) Power Switch “M”. The GATE_M pin driven HIGH when charge pump M is enabled and pulled LOW when the charge pump is disabled. 16 DNC Do not connect (must be left floating). 17 VFB Voltage Feedback Pin. This input pin is used with voltage based power sequencing to monitor the level of a previously turned- on supply. If unused, connect to ground. 18 VDDH Primary supply voltage (typically 5V). 19 VDDM Monitored Supply Voltage “M” input. 20 VDDL Monitored Supply Voltage “L” input. X80200, X80201, X80202, X80203, X80204

3 FN8154.0 Absolute Maximum Ratings Recommended Operating Conditions Voltage on given pin (Power Sequencing Functions): All V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Power Sequencing Control Circuits Over the recommended operating conditions unless otherwise specified SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC CHARACTERISTICS – Undervoltage Lockout Comparators VDDH Supply Operating Range 3.05 5.5 V VDDM Supply Operating Range 0.95 5.5 V VDDL Supply Operating Range 0.95 5.5 V IDDH Supply Current V DDH = 5.5V 2.5 mA IDDH Supply Current V DDH = 3.1V 200 µA UVLOH Undervoltage lockout for VDDH X80200 4.425 4.5 4.575 V X80201 4.425 4.5 4.575 V X80202 2.95 3.0 3.05 V X80203 2.95 3.0 3.05 V X80204 2.95 3.0 3.05 V UVLO M Undervoltage lockout for VDDM X80200 2.2 3.0 3.05 V X80201 2.2 2.25 2.3 V X80202 2.2 2.25 2.3 V X80203 2.2 2.25 2.3 V X80204 0.875 0.9 0.925 V UVLO L Undervoltage lockout for VDDL X80200 0.875 0.9 0.925 V X80201 0.875 0.9 0.925 V X80202 1.65 1.7 1.75 V X80203 0.875 0.9 0.925 V X80204 0.875 0.9 0.925 V V HYS UVLOH,M,L comparator Hysteresis 30 mV DC CHARACTERISTICS – Gates and Others VIH Voltage Input Valid High for ENS, SETV, GATEH_EN VDDH x 0.7 VDDH + 0.5 V VIL Voltage Input Valid Low for ENS, SETV, GATEH_EN -0.5 VDDH x 0.3 V VOL Output LOW Voltage (SDA, READY) 0.4 V X80200, X80201, X80202, X80203, X80204

4 FN8154.0 VGATE_ON GATE_H, GATE_M V DDH = 5.5V 9.0 10 11.0 V GATE_L 7.0 8 9.0 GATE_H, GATE_M V DDH = 3.1V 7.0 8 9.0 V GATE_L 6.0 7.0 8.0 VGATE_OFF Gate Voltage Drive (OFF) for GATE_H, GATE_M, GATE_L 00 . 1 V IGATE_ON Gate Current Drive (ON) for GATE_H, GATE_M, GATE_L (Note 1) 20 35 45 µA IGATE_OFF Gate Sinking Current Drive (OFF) for GATE_H, GATE_M, GATE_L VDDH = 5.5V, VDDM = 0V, VDDL = 0V, GATEH_EN = 0, GATE_H = 5.5, GATE_L = 5.5, GATE_M = 5.5 (Note 1) 91 01 1 m A V HYST VFB comparator (Note 1) 25°C 15 20 25 mV AC CHARACTERISTICS tPURST Delayed READY Output (READY output delayed after VDDH rises above UVLOH) VDDH = 5.5V 10 12 15 ms VDDH = 3.1V 40 80 tDELAY_UP VDDH = 5.5V, CGATE = 0 600 750 900 µs VDDH = 3.1V, CGATE = 0 6 ms tDELAY_DOWN VDDH = 5.5V 700 800 900 µs VDDH = 3.1V 6 ms tOFF GATE_H, GATE_M, GATE_L turn-off time VDDH = 5.5V, (Note 1) 40 µs VDDH = 3.1V, (Note 1) 80 µs tON GATE_H, GATE_M, GATE_L turn-on time VDDH = 5.5V, (Note 1) 0.5 0.6 0.7 ms VDDH = 3.1V, (Note 1) 2 5 ms tR VDDH Rise Time (Note 1) 1.0 µs tF VDDH Fall Time (Note 1) 1.0 µs Power Sequencing Control Circuits Over the recommended operating conditions unless otherwise specified (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDDH tR tF GATE_H, M, L tON tOFF GATE_L GATE_M tDELAY_UP tDELAY_DOWN tPURST UVLOH VDDH READY X80200, X80201, X80202, X80203, X80204

5 FN8154.0 Equivalent AC Output Load Circuit for VDDH = 5V Symbol Chart Serial bus Interface Electrical Characteristics SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNIT VIL Signal Input Low Voltage 0.8 V VIH Signal Input High Voltage 2.0 V VOL Signal Output Low Voltage (Note 1), I pullup ≥ 4mA 0.4 V CBUS Capacitive Load per bus segment (Note 1) 400 pF Capacitance SYMBOL PARAMETER TEST CONDITIONS MAX UNIT COUT Output Capacitance (SDA) V OUT = 0V, (Note 1) 8 pF CIN Input Capacitance (SCL) V IN = 0V, (Note 1) 6 pF NOTE: 1. Guaranteed by device characterization. VDDH SDA, READY 30pF 2.06kΩ AC Test Conditions Input pulse levels V CC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing levels V CC x 0.5 Output load Standard output load Must be steady Will be steady May change from LOW Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance WAVEFORM INP UTS OUTPUTS to HIGH X80200, X80201, X80202, X80203, X80204

7 FN8154.0 Principles of Operation Power Sequencing Control (PSC) The Intersil X80200 supports a variety of sequencing applications. The sequencing can be voltage-based or time- based. Some examples are shown in Figure , Figure , and Figure in the Applications section. The X80200 allows for designs that can control the power sequencing of up to three voltage supplies. For systems with more than three supplies, the X80200 may be cascaded. Basic Functions VDDH is the primary voltage for the X80200. Once VDDH rises above the primary undervoltage lockout level (UVLO for time tPURST, the READY output goes HIGH indicating that the supply power is good. By connecting READY directly to GATEH_EN, the GATE_H output goes high immediately, turning on the power FET connected in series with VDDH. The system primary voltage may be delayed by using an external RC circuit between READY and GATEH_EN. VDDH must be stable before VDDM and VDDL supplies are monitored and power sequencing begins. The second supply voltage (I/O supply) is monitored by the VDDM pin. VDDM must be greater than the I/O supply undervoltage lockout level (UVLO M) prior to any activation of the GATE_M output. The VDDM voltage is used to turn on the charge pump that drives the GATE_M output. The third supply (core supply) is monitored by the VDDL pin. VDDL must be greater than the core supply undervoltage lockout level (UVLO L) prior to any activation of the GATE_L output. The VDDL voltage is used to turn on the charge pump that drives the GATE_M output. Power Sequencing Functions X80200 provides two options for power sequencing. In time based sequencing, the ENS (Enable Sequence) input signals that the core and I/O voltages are to turn on with a fixed time relationship. In voltage based sequencing, the SETV (Set Voltage) initiates turn-on of the core voltage. The I/O voltage remains off until the core voltage reaches a set threshold. In both cases the X80200 uses a core-voltage first and core voltage-last power up/down algorithm. TIME-BASED POWER SEQUENCING A rising edge (LOW to HIGH) transition of the ENS pin turns on the charge pump that drives the GATE_L output. A falling edge (HIGH to LOW) transition of the ENS signal turns off the charge pump that drives the GATE_M output. This technique provides a “forced” core-voltage-first power up and core-voltage-last power down algorithm. The ENS signal does not control the ramp up/down rates of the GATE_M or GATE_L outputs. In the absence of an externally provided ENS signal, the ENS pin can be connected in a number of different ways.

  • ENS can connect to the VDDH pin. In this case, the GATE_H and GATE_L outputs are enabled at the same time. GATE_H could be delayed by using an external RC timer between READY and GATEH_EN to provide a sequence where VDDL is the first supply voltage applied to the system.
  • ENS can connect to a delayed READY signal, so that the VDDL voltage follows the VDDH voltage by a fixed time.
  • ENS can connect to the system side of the VDDH FET, so the VDDL voltage will follow immediately after the primary supply is applied to the system. See "Functional Description" on page 7 for details on timing and ramp-up. VOLTAGE-BASED POWER SEQUENCING In this configuration, the drain of the “L” MOSFET is connected to the VFB input of the X80200, the ENS pin is tied to ground and a resistor divider provides a reference voltage to the REF pin. A LOW to HIGH transition of the SETV pin turns on the GATE_L output. This turns on the “L” MOSFET. Once the drain of this FET reaches the REF level, GATE_M turns on. Since the trigger for the GATE_M output is selected by a threshold level, the user has the ability to specify relative core and I/O voltage sequencing. System Monitoring and Remote Shutdown The X80200 Status Register contains fault detection bits that indicate the status of the GATE_H, GATE_M, and GATE_L pins. These bits are Stat_GATEH, Stat_GATEM, and Stat_GATEL. The status register can be read via 2-wire bus. This feature allows for system monitoring of the power sequencing of supplies. The system can turn off the FETs by writing to the Remote Shutdown Register through the 2-wire interface. There are three turn-off selections. See "Remote Shutdown Register (RSR) (Volatile)" on page 10 for more details. Functional Description Voltage Inputs. The X80200 has three voltage monitors for power sequencing: the VDDH (primary voltage), VDDM (I/O voltage), and VDDL (core voltage). These voltage monitors operate independently of each other. PRIMARY VOLTAGE VDDH This voltage is the primary voltage for the device and is required before X80200 can power sequence VDDM and VDDL. As VDDH powers up, it is compared to an internal UVLO H reference. This undervoltage lockout level is preset at the factory. For information on this setting, see Ordering Information. For custom programmed levels, contact Intersil. X80200, X80201, X80202, X80203, X80204

10 FN8154.0 Register Information The Register Block is organized as follows:

  • Status Register (SR) (1 Byte). Located at address 00h.
  • Remote Shut Down Register (RSR) (1 Byte). Located at address FFh. The Status Register provides the user a mechanism for checking the status of GATE_H, GATE_M and GATE_L. These bits are volatile and are read only. The gate status values in the Status Register can be read at any time by performing a random read operation. Only one byte is returned by each read operation. The master should supply a stop condition following the output byte to be consistent with the bus protocol. STAT_GATEH: GATEH Status Flag (volatile) STAT_GATEH will be set to ‘1’ when the GATE_H charge pump is turned on. It will be reset to ‘0’ when the GATE_H charge pump is turned off. STAT_GATEM: GATEM Status Flag (volatile) STAT_GATEM will be set to ‘1’ when GATE_M charge pump is turned on. It will be reset to ‘0’ when the GATE_M charge pump is turned off. STAT_GATEL: GATEL Status Flag (volatile) STAT_GATEL will be set to ‘1’ when GATE_L charge pump is turned on. It will be reset to ‘0’ when the GATE_L charge pump is turned off. The status register also contains a WEL bit that controls write operations to the Shutdown Register. Bits 7, 6, 5, and 4 should always be set to ‘0’. WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the Remote Shutdown Register (RSR). This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to the RSR will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the status register. The X80200 provides the user with a software shutdown of GATE_H, GATE_L and GATE_M. This over-rides the normal output control. A write operation with data 01h to the RSR will immediately turn off GATE_M followed by GATE_L. The GATE_L turn off is delayed by t DELAY_DOWN. A write operation with data 02 to the RSR will turn off GATE_H. A write operation with data 03 to RSR will shutdown all gates. GATE_H turn off at the same time as GATE_M. GATE_L turns off after a delay of t DELAY_DOWN. A write operation with data 00h to the RSR will remove the software override function. Assuming all supplies are good, the X80200 will return to the previous state by first turning on GATE_H and GATE_L. Then, GATE_M is turned on according to the power sequencing mode chosen. Bits 7, 6, 5, 4, 3 and 2 of the Remote Shutdown Register should always be set to ‘0’. The data in the RSR can be read by performing a random read operation to the RSR. The data in the RSR powers up in ‘0’ state. Bus Interface Information Interface Conventions The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. Therefore, the devices in this family operate as slaves in all applications. Status Register (Volatile) 7 6 5 4 321 0 0000S T A T _ GATEH STAT_ GATEM STAT_ GATEL WEL Remote Shutdown Register (RSR) (Volatile) RSR DATA GATE SHUTDOWN SEQUENCE

01 GATE_M,

GATE_L GATE_M turns off, then after time tDELAY_DOWN GATE_L turns off.

02 GATE_H Immediate turn off of GATE_H

03 GATE_H,

GATE_M, GATE_L GATE_H and GATE_M turn off, then after time t DELAY_DOWN GATE_L turns off. 00 no override X80200 returns to previous condition, assuming all supplies are good, GATE_H and GATE_L turn on, then GATE_M turns on according to the chosen sequence mode. X80200, X80201, X80202, X80203, X80204

one, the master must first perform a “dummy” write operation. and then issue a stop condition. transfer sequence. See Figure 1 for bus timing.

  • The device is in the low power standby state.
  • The WEL bit is set to ‘0’. It is not possible to write to the device.
  • The WEL bit must be set to allow write operations.
  • SDA pin is the input mode.
  • The data in the RSR powers up in ‘0’ state. SA6SA7 SA5 SA2 SA1 SA0 DEVICE TYPE IDENTIFIER READ/ SA4 R/W101 0 WRITEADDRESS INTERNAL DEVICE A2 A1 A0 BIT SA0 OPERATION 0W R I T E

1 READ

FIGURE 10. ADDRESS FORMAT

FIGURE 14. TELECOM BACKPLACE/SYSTEM POWER SUPPLY TIME BASED POWER SEQUENCING

FIGURE 15. POWER SEQUENCING OF VRM SUPPLIES

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8154.0 Packaging Information NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 20-Lead Plastic, TSSOP, Package Code V20 See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .252 (6.4) .260 (6.6) .002 (.05) .006 (.15) .041 (1.05) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) X80200, X80201, X80202, X80203, X80204