X4163S8I

X4163 INTERSIL | Alldatasheet

Document overview

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Technical content

FN8120.0 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X4163, X4165 16K, 2K x 8 Bit CPU Supervisor with 16K EEPROM

FEATURES

• Selectable watchdog timer
• L o w VCC detection and reset assertion —Four standard reset threshold voltages —Adjust low V CC reset threshold voltage using special programming sequence —Reset signal valid to V CC = 1V
• Low power CMOS —<20µA max standby current, watchdog on —<1µA standby current, watchdog OFF —3mA active current
• 16Kbits of EEPROM —64-byte page write mode —Self-timed write cycle —5ms write cycle time (typical)
• Built-in inadvertent write protection —Power-up/power-down protection circuitry —Block Lock (1, 2, 4, 8 pages, all, none)
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available Packages —8-lead SOIC —8-lead TSSOP

DESCRIPTION

The X4163/5 combines four popular functions, Power- on Reset Control, Watchdo g Timer, Supply Voltage Supervision, and Serial EEPROM Memory in one pack- age. This combination lowe rs system cost, reduces board space requirements, and increases reliability. Applying power to the dev ice activates the power on reset circuit which holds RESET /RESET active for a period of time. This allows the power supply and oscilla- tor to stabilize before the processor can execute code. The Watchdog Timer provides an independent protec- tion mechanism for microcontrollers. When the micro- controller fails to restart a timer within a selectable time out interval, the device activates the RESET /RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device’s low V CC detection circuitry protects the user’s system from low voltage conditions, resetting the system when VCC falls below the set minimum VCC trip point. RESET/RESET is asserted until V CC returns to proper operating level and stabilizes. Four industry standard V TRIP thresholds are available, however, Inter- sil’s unique circuits allow the threshold to be repro- grammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision. BLOCK DIAGRAM Watchdog Timer Reset Data Register Command Decode & Control Logic SDA SCL VCC Reset & Watchdog Timebase Power on and GenerationVTRIP RESET (X4163) Reset Low Voltage Status Register Protect Logic EEPROM Array Watchdog Transition Detector WP VCC Threshold Reset logic Block Lock Control 2Kb RESET (X4165) Data Sheet April 13, 2005

2 FN8120.0 April 13, 2005 PIN CONFIGURATION PIN FUNCTION VSS VCC SDA SCL3 8-Pin JEDEC SOIC WP RESET/RESET VCC SCL RESET/RESET VSS3 WP SDA

8 Pin TSSOP

(SOIC) Pin (TSSOP) Name Function

13 S 0 Device Select Input

24 S 1 Device Select Input

35 RESET/

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 250ms. RESET/RESET goes active if the Watchdog Timer is enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time out period. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET goes active on power up and remains active for 250ms after the power supply sta- bilizes. 46 V SS Ground 57 S D A Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and may be wire ORed with other open drain or open collector outputs. This pin requires a pull up resistor and the input buffer is always active (not gated). Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET /RESET going active. 68 S C L Serial Clock. The Serial Clock controls the serial bus timing for data input and output. 71 W P Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the control register.

82 V CC Supply Voltage

X4163, X4165

active. This signal provides several benefits. to operate with insufficient voltage. bilization of the oscillator. tion prior to initialization of the circuit. reducing the likelihood of data corruption on power up. /RESET allowing the system to begin operation. signal remains active until the voltage drops below 1V. allowed and no nonvolatile write operation can start. goes active are allowed to finish. memory Block Lock and the Write Protect (WP) pin. These are discussed elsewhere in this document. Figure 1. Set V

Figure 4. VTRIP Programming Sequence data byte is allowed for each register write operation. the Control Register" below. any data bytes written after the first byte is entered. time by performing a random read at address FFFFh. Only one byte is read by each register read operation. The X4163/5 resets itself after the first byte is read.

tile latch that powers up in the LOW (disabled) state. tion immediately after the stop condition. Watchdog Timer. The options are shown below. written and the block protect bits cannot be changed. long as the WP pin is held HIGH. Table 1. Write Protect Enable Bit and WP Pin Function

Figure 10. Writing 12-bytes to a 64-byte page starting at location 60. contents of the array will not be effected. can then proceed with the read or write operation. Refer to the flow chart in Figure 11. Figure 11. Acknowledge Polling Sequence

4 Bytes

8 Bytes

Figure 14. Sequential Read Sequence acknowledge and then issuing a stop condition. address n followed by the data from address n + 1. – next two bits are the device address. write operation. Refer to Figure 15. the device outputs an acknowledge on the SDA line. is undefined on a power up condition.

Figure 15. X4163/5 Addressing – The device is in the low power standby state. – SDA pin is the input mode. /RESET Signal is active for tPURST. – The WEL bit must be set to allow write operations. HIGH will prevent all writes to the Control Register. array from write operations.

14 FN8120.0 April 13, 2005 ABSOLUTE MAXIMUM RATINGS Voltage on any pin with respect to VSS... -1.0V to +7V COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any ot her conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Notes: (1) The device enters the Active state after any start, and re mains active until: 9 clock cycl es later if the Device Selec t Bits in the Slave Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation. (2) The device goes into Standby: 200ns afte r any stop, except those that initiate a nonvolatile write cycle; t WC after a stop that initiates a nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte. (3) V IL Min. and VIH Max. are for reference only and are not tested. Symbol Parameter VCC = 2.7 to 5.5V Unit Test ConditionsMin Max ICC1(1) Active Supply Current Read 1.0 mA V IL = VCC x 0.1, VIH = VCC x 0.9 fSCL = 400kHz, SDA = CommandsICC2(1) Active Supply Current Write 3.0 mA ISB(2) Standby Current DC (WDT off) 1 µA V SDA = VSCL = VSB Others = GND or VSB ISB(2) Standby Current DC (WDT on) 20 µA V SDA=VSCL=VSB Others = GND or VSB ILI Input Leakage Current 10 µA V IN = GND to VCC ILO Output Leakage Current 10 µA V SDA = GND to VCC Device is in Standby(2) VIL(3) Input LOW Voltage -0.5 V CC x 0.3 V VIH(3) Input nonvolatile V CC x 0.7 V CC + 0.5 V VHYS Schmitt Trigger Input Hysteresis Fixed input level VCC related level 0.2 .05 x VCC V V V OL Output LOW Voltage 0.4 V I OL = 3.0mA (2.7- 5.5V) RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0°C 70°C Industrial -40°C +85°C Option Supply Voltage Limits -2.7 and -2.7A 2.7V to 5.5V Blank and -4.5A 4.5V to 5.5V X4163, X4165

15 FN8120.0 April 13, 2005 CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5V) Notes: (4) This parameter is periodically sampled and not 100% tested. EQUIVALENT A.C. LOAD CIRCUIT A.C. TEST CONDITIONS A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Notes: (1) Typical values are for T A = 25°C and VCC = 5.0V (2) Cb = total capacitance of one bus line in pF. Symbol Parameter Max. Unit Test Conditions COUT(4) Output Capacitance (SDA, RST/RST)8 p F V OUT = 0V CIN(4) Input Capacitance (SCL, WP) 6 pF V IN = 0V SDA or RESET 1533Ω 100pF For VOL= 0.4V and IOL = 3 mA Input pulse levels 0.1V CC to 0.9VCC Input rise and fall times 10ns Input and output timing levels 0.5V CC Output load Standard output load Symbol Parameter Min. Max. Unit fSCL SCL Clock Frequency 0 400 kHz tIN Pulse width Suppression Time at inputs 50 ns tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs tBUF Time the bus free before start of new transmission 1.3 µs tLOW Clock LOW Time 1.3 µs tHIGH Clock HIGH Time 0.6 µs tSU:STA Start Condition Setup Time 0.6 µs tHD:STA Start Condition Hold Time 0.6 µs tSU:DAT Data In Setup Time 100 ns tHD:DAT Data In Hold Time 0 µs tSU:STO Stop Condition Setup Time 0.6 µs tDH Data Output Hold Time 50 ns tR SDA and SCL Rise Time 20 + .1Cb 300 ns tF SDA and SCL Fall Time 20 + .1Cb 300 ns tSU:WP WP Setup Time 0.6 µs tHD:WP WP Hold Time 0 µs Cb Capacitive load for each bus line 400 pF X4163, X4165

16 FN8120.0 April 13, 2005 TIMING DIAGRAMS Bus Timing WP Pin Timing Write Cycle Timing Nonvolatile Write Cycle Timing Notes: (1) t WC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. Symbol Parameter Min. Typ. (1) Max. Unit tWC(1) Write Cycle Time 5 10 ms tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DATSCL SDA IN SDA OUT tF tLOW tBUFtAA tR tHD:WP SCL SDA IN WP tSU:WP Clk 1 Clk 9 Slave Address Byte START SCL SDA tWC 8th bit of Last Byte ACK Stop Condition Start Condition X4163, X4165

17 FN8120.0 April 13, 2005 Power-Up and Power-Down Timing RESET Output Timing Notes: (8) This parameter is periodically sampled and not 100% tested. SDA vs. RESET Timing Symbol Parameter Min. Typ. Max. Unit VTRIP Reset Trip Point Voltage, X4163/5-4.5A Reset Trip Point Voltage, X4163/5 Reset Trip Point Voltage, X4163/5-2.7A Reset Trip Point Voltage, X4163/5-2.7 4.5 4.25 2.85 2.55 4.62 4.38 2.92 2.62 4.75 4.5 3.0 2.7 V tPURST Power-up Reset Time Out 100 250 400 ms tRPD(8) VCC Detect to Reset/Output 500 ns tF(8) VCC Fall Time 100 µs tR(8) VCC Rise Time 100 µs VRVALID Reset Valid VCC 1V VCC tPURST tR tF tRPD

0 Volts

(X4165) (X4163) tPURST VRVALID tRSP<tWDO tRST RESET SDA tRSP Note: All inputs are ignored during the active reset period (tRST). tRST SCL tRSP>tWDO tRSP>tWDO X4163, X4165

18 FN8120.0 April 13, 2005 RESET Output Timing VTRIP Programming Timing Diagram (WEL = 1) VTRIP Programming Parameters Symbol Parameter Min. Typ. Max. Units tWDO Watchdog Time Out Period, WD1 = 1, WD0 = 1 (factory setting) WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 100 450 OFF 250 650 1.5 400 850 ms ms sec t RST Reset Time Out 100 250 400 ms Parameter Description Min. Max. Unit tVPS VTRIP Program Enable Voltage Setup time 1 µs tVPH VTRIP Program Enable Voltage Hold time 1 µs tTSU VTRIP Setup time 1 µs tTHD VTRIP Hold (stable) time 10 ms tWC VTRIP Write Cycle Time 10 ms tVPO VTRIP Program Enable Voltage Off time (Between successive adjustments) 0 µs tRP VTRIP Program Recovery Period (Between successive adjustments) 10 ms VP Programming Voltage 15 18 V VTRAN VTRIP Programmed Voltage Range 2.55 4.75 V Vta1 Initial VTRIP Program Voltage accuracy (VCC applied - VTRIP) (Programmed at 25°C.) -0.1 +0.4 V Vta2 Subsequent VTRIP Program Voltage accuracy [(VCC applied - Vta1) - VTRIP. Programmed at 25°C.] -25 +25 mV Vtr VTRIP Program Voltage repeatability (Successive program operations. Programmed at 25°C.) -25 +25 mV Vtv VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.) -25 +25 mV VTRIP programming parameters are periodically sampled and are not 100% tested. VCC (VTRIP) WP tTSU tTHD tVPHtVPS VP VTRIP tVPO SCL SDA A0h 01h or 03h tRP 00h 00h X4163, X4165

19 FN8120.0 April 13, 2005 PACKAGING INFORMATION 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.019 (0.49) Pin 1 Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4X) 7° 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0° - 8° X 45° 8-Lead Plastic Small Outline Gull Wing Package Type S NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.250" 0.050"Typical 0.050" Typical 0.030" Typical

8 PlacesFOOTPRINT

X4163, X4165

20 FN8120.0 April 13, 2005 PACKAGING INFORMATION NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 8-Lead Plastic, TSSOP, Package Type V See Detail “A” .031 (.80) .041 (1.05) .169 (4.3) .025 (.65) BSC .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0° - 8° .010 (.25) .019 (.50) .029 (.75) Gage Plane Seating Plane Detail A (20X) (4.16) (7.72) (1.78) (0.42) (0.65) All Measurements Are Typical X4163, X4165

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8120.0 April 13, 2005

Ordering Information

(Active LOW) Part Number RESET (Active HIGH) -40°C - 85°C X4163S8I–4.5A X4165S8I–4.5A 8L TSSOP 0°C - 70°C X4163V8–4.5A X4165V8–4.5A -40°C - 85°C X4163V8I–4.5A X4165V8I–4.5A 4.5-5.5V 4.25-4.5 8L SOIC 0°C - 70°C X4163S8 X4165S8 -40°C - 85°C X4163S8I X4165S8I 8L TSSOP 0°C - 70°C X4163V8 X4165V8 -40°C - 85°C X4163V8I X4165V8I -40°C - 85°C X4163S8I–2.7A X4165S8I–2.7A 8LTSSOP 0°C - 70°C X4163V8–2.7A X4165V8–2.7A -40°C - 85°C X4163V8I–2.7A X4165V8I–2.7A -40°C - 85°C X4163S8I–2.7 X4165S8I–2.7 8L TSSOP 0°C - 70°C X4163V8–2.7 X4165V8–2.7 -40°C - 85°C X4163V8I–2.7 X4165V8I–2.7 8-Lead TSSOP EYWW XXXXX 8-Lead SOIC X4163/5 X XX Blank = 8-Lead SOIC ADB/ADK = -4.5A (0 to +70°C) ADD/ADM = No Suffix (0 to +70°C) ADF/ADO = -2.7A (0 to +70°C) ADH/ADQ= -2.7 (0 to +70°C) Blank = No Suffix (0 to +70°C) I = No Suffix (-40 to +85°C) AN = -2.7A (0 to +70°C) AL = -4.5A (0 to +70°C) X4163, X4165