ISL8225MEVAL4Z INTERSIL | Alldatasheet

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1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright Intersil Americas Inc. 2012. All Rights Reserved. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. design to a component layer and a simple ground layer.

  • 0V to 20V power supply with at least 5A source current capability
  • Electronic load capable of sinking current up to 30A
  • Digital multimeters (DMMs)
  • 100MHz quad-trace oscilloscope Quick Start For dual output operation, the inputs are BA7 (VIN1), BA8 (GND), BA3 (VIN2) and BA4 (GND). The outputs are BA5 (VOUT1), BA6 (GND), BA1 (VOUT2) and BA2 (GND). For paralleled single output operation, the inputs are BA7 (VIN1) and BA8 (GND). The outputs are BA5 (VOUT1) and BA6 (GND) with BA5 and BA1 shorted. Dual Output Mode 1. Connect a power supply capable of sourcing at least 5A to the inputs BA7 (VIN1), BA8 (GND), BA3 (VIN2) and BA4 (GND) of the ISL8225MEVAL4Z evaluation board, with a voltage between 4.5V to 20V. VIN1 and VIN2 can be different with R18 and R19 open. 2. Connect an electronic load or the device to be powered to the outputs BA5 (VOUT1) and BA6 (GND), BA1 (VOUT2) and BA2 (GND) of the board. All connections, especially the low voltage, high current V OUT lines, should be able to carry the desired load current and should be made as short as possible. See how-to video at intersil.com/ evid03

FIGURE 1. ISL8225MEVAL4Z BOARD IMAGE

  1. Make sure that the setup is connected correctly. Turn on the
  2. If different output voltages are desired, board resistors can be

curves in the ISL8225M datasheet.

  1. To set up the parallel mode, short JP1 (ENC), JP2 (VMON) and
  2. Remove R9 and R13. Change R14 to 0 Ω. Change R18 and

straps. Add C2 for a 470pF capacitor.

  1. Connect a power supply capable of sourcing at least 5A to the
  2. Connect an electronic load or the device to be powered to the

should be made as short as possible.

  1. Make sure the setup is connected correctly prior to applying any

OUT1, which should be at 1.2V.

  1. Apply any load that is less th an 30A for normal steady state
  2. In order to generate CLKOUT at a shifted phase clock signal,
  3. Program MODE and VSEN2+ pin voltages to set the CLKOUT
  4. Use a coaxial cable to connect CLKOUT (J5) to SYNC (J2) of the
  5. If the second board is programed for parallel use, the ISHARE

pins of the first and second boards need to be tied together. capacitors of C14 for different boards to decouple the noise.

  1. If the third board is used in cascadable mode, the second

CLKOUT signal for the SYNC pin on the third board.

  1. Follow the instructions from Steps 1 through 5 for more

solder attachment, are lead-free. temperature without additional cooling systems needed. TABLE 1. VALUE OF BOTTOM RESISTOR (TOP RESISTOR R1, TABLE 2. BOARD CONFIGURATION FOR SINGLE OUTPUT 30A

3 AN1793.1 December 6, 2012 However, if the output voltage is increased or the board is operated at elevated temperatures, then the available current is derated. Refer to the derated current curves in the datasheet to determine the output current available. For layout of designs using the ISL8225M, the thermal performance can be improved by adhering to the following design tips: 1. Use the top and bottom layers to carry the large current. VOUT1, VOUT2, Phase 1, Phase 2, PGND, VIN1 and VIN2 should have large, solid planes. Place enough thermal vias to connect the power planes in different layers under and around the module. 2. Phase 1 and Phase 2 pads are switching nodes that generate switching noise. Keep these pads under the module. For noise-sensitive applications, it is recommended to keep phase pads only on the top and inner layers of the PCB; do not place phase pads exposed to the outside on the bottom layer of the PCB. To improve the thermal performance, the phase pads can be extended in the inner layer, as shown in Phase 1 and Phase 2 pads on layer 2 (Figure 5) for this dual 15A evaluation board. Make sure that layer 1 and layer 3 have the GND layers to cover the extended areas of phase pads at layer 2 to avoid noise coupling. 3. Place the modules evenly on the board and leave enough space between modules. If the board space is limited, try to put the modules with low power loss closely together (i.e. low V OUT or IOUT) while still separating the module with high power loss. 4. If the ambient temperature is high or the board space is limited, airflow is needed to dissipate more heat from the modules. A heat sink can also be applied to the top side of the module to further improve the thermal performance (heat sink recommendation: Aavid Thermalloy, part number 375424B00034G, www.aavid.com

4 AN1793.1 December 6, 2012 TABLE 3. ISL8225M OPERATION MODES

DESCRIPTION

FOR DETAILS) OPERATION MODE OF 2ND MODULE OPERATION MODE OF 3RD MODULEMODE EN1/FF1 (I) EN2/FF2 (I) VSEN2- (I) MODE (I) VSEN2+ (I) CLKOUT/REFIN WRT 1ST (I OR O) VMON2 (Note 2) VMON1 OF 2ND MODULE (Note 2) 2ND CHANNEL WRT 1ST (O) (NOTE 1) 10 0 - - - -- - - - - D i s a b l e d 2A 0 1 Active Active Active - Active - VMON1 = VMON2 to Keep PGOOD Valid -- S i n g l e P h a s e VMON2 to Keep PGOOD Valid -- S i n g l e P h a s e 3A 1 1 <V CC -0.7V Active Active 29% to 45% of VCC (I) Active - 0° - - Dual Regulator 3B 1 1 <V CC -0.7V Active Active 45% to 62% of VCC (I) Active - 90° - - Dual Regulator 3C 1 1 <V CC -0.7V Active Active >62% of V CC (I) Active - 180° - - Dual Regulator 41 1 < V CC -0.7V Active Active <29% of V CC (I) Active - -60° - - DDR Mode 5A 1 1 V CC GND - 60° VMON1 or Divider - 180° - - 2-Phase 5B 1 1 V CC GND - 60° Divider Divider 180° 5B 5B 6-Phase 5C 1 1 V CC GND - 60° VMON1 or Divider Active 180° 5C 5C 3 Outputs 61 1 V CC VCC GND 120° 1k Ω Active 240° 2B - 3-Phase 7A 1 1 V CC VCC VCC 90° 1k Ω Divider 180° 7A - 4-Phase 7B 1 1 V CC VCC VCC 90° 1k Ω Active 180° 7B - 2 Outputs (1st module in Mode 7A) 7C 1 1 V CC VCC VCC 90° 1k Ω Active 180° 3, 4 - 3 Outputs (1st module in Mode 7A)

8 Cascaded Module Operation MODEs 5B+5B+7A+5B+5B +5B/7A, No External Clock Required 12-Phase

9 External Clock or External Logic Circuits Requir ed for Equal Phase Interval 5, 7, 8, 9, 10, 11,

(PHASE >12) NOTE: 1. “2 ND CHANNEL WRT 1ST” means “second channel with respect to first;” in other words, Channel 2 lags Channel 1 by the degrees specified in this column. For example, 90° means Channel 2 lags Channel 1 by 90°; -60° means Channel 2 leads Channel 1 by 60°. 2. “VMON1” means that the pin is tied to the VMON1 pin of the same module. “Divider” means that there is a resistor divider from VOUT to SGND; refer to Figure 24 in the ISL8225M datasheet. “1kΩ” means that there is a 1kΩ resistor connecting the pin to SGND; refer to Figure 22 in the ISL8225M datasheet.

FIGURE 2. ISL8225MEVAL4Z BOARD SCHEMATIC GROUND AND GROUND ARE TIED TOGETHER AT PIN 6 OF U1.

FIGURE 7. BOTTOM LAYER SOLDER SIDE FIGURE 8. BOTTOM SILK SCREEN

8 AN1793.1 December 6, 2012 Bill of Materials PART NUMBER REF DES QTY VALUE TOL. VOLTAGE POWER PAC KAGE TYPE JEDEC TYPE MANUFACTURER DESCRIPTION 10TPB330M C04, C08 2 330µF 20% 10V SMD CAP_7343_149 131-4353-00 J1, J4 2 CONN TEK131-4353-00 2N7002-7-F Q1 1 SOT23 SOT23 31-5329-52RFX J2, J5 2 CONN CON_BNC_31_5329_52RFX

5002 P1-P8 8 THOLE MTP500X

575-4 BA1-BA8 8 CONN CON_BAN_575 EEVHA1E331UP CIN1, CIN4 2 330µF 20% 25V SMD CAPAE_315X402 GRM21BR71C475KA73L C1 1 4.7µF 10% 16V 805 CAP_0805 Murata Ceramic Capacitor GRM32ER71A476KE15L C01, C03, C05, C07 4 47µF 10% 10V 1210 CAP_1210 Murata Ceramic Chip Capacitor H1045-OPEN C2, C3, C6, C7 4 OPEN 5% OPEN 603 CAP_0603 Generic Multilayer Capacitor H1045-00102-16V10 C15, C16 2 1000pF 10% 16V 603 CAP_0603 Generic Multilayer Capacitor H1045-00102-50V10 C4, C5, C8, C9 4 1000pF 10% 50V 603 CAP_0603 Generic Multilayer Capacitor H1045-OPEN C10, C11, C12, C14 6 OPEN 5% OPEN 603 CAP_0603 Generic Multilayer Capacitor H1082-OPEN C02, C06, C09, C010 4 OPEN 10% OPEN 1210 CAP_1210 Generic Ceramic Chip Capacitor H2505-DNP-DNP-1 R14-R16, R21, RFSET 5 DNP 1% DNP 603 RES_0603 H2511-00R00-1/16W1 R9, R10, R13, R17, R20 5 0 Ω 1% 1/16W 603 RES_0603 H2511-01001-1/16W1 R1, R2, R3, R6, R8 4 1k Ω 1% 1/16W 603 RES_0603 H2511-03321-1/16W1 R11, R12 2 3.32k Ω 1% 1/16W 603 RES_0603 H2511-16501-1/16W1 R5, R7 2 16.5k Ω 1% 1/16W 603 RES_0603 H2511-04121-1/16W1 R6, R8 2 4.12k Ω 1% 1/16W 603 RES_0603 H2511-06650-1/16W1 R4 1 665 Ω 1% 1/16W 603 RES_0603 H2512-OPEN R18, R19 2 OPEN 0% 1/10W 805 RES_0805 ISL8225MIRZ U1 1 QFN QFN26_670X670_ISL8225M JUMPER2_100 JP1-JP7 7 THOLE JUMPER-1 SSL-LXA3025IGC LED1 1 SMD LED_3X2_5MM TMK325B7226MM-TR CIN2, CIN3, CIN5, CIN6 4 22µF 20% 25V 12 10 CAP_1210 Taiyo Yuden Ceramic Chip Capacitor

cautioned to verify that the Application Note or Technical Brief is current before proceeding. FIGURE 9. EFFICIENCY vs LOAD CURRENT (5V IN AT 500kHz) FIGURE 10. EFFICIENCY vs LOAD CURRENT (12V IN)