RFFC5071A QORVO | Alldatasheet

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WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 1 of 27 www.qorvo.com Package: QFN, 32-Pin, 5mm x 5mm Product Overview The RFFC5071A and RFFC5072A are re -configurable frequency conversion devices with integrated fractional -N phased locked loop (PLL) synthesizer, voltage controlled oscillator (VCO) and either one or two high linearity mixers. The fractional -N synthesizer takes advantage of an advanced sigma -delta modulator that delivers ultra-fine step sizes and low spurious products. The VCO features temperature compensation circuits that deliver stable performance across the operating temperature range of - 40 °C to +85 °C. The PLL/VCO engine combined with an external loop filter allows the user to generate local oscillator (LO) signals from 85 MHz to 4200 MHz. The LO signal is buffered and routed to the integrated RF mixers which are used to up/down -convert frequencies ranging from 30 MHz to 6000 MHz. The mixer bias current is programmable and can be reduced for applications requiring lower power consumption. Both devices can be configured to work as signal sources by bypassing the integrated mixers. Device programming is achieved via a simple 3 -wire serial interface. In addition, a unique programming mode allows up to four devices to be controlled from a common serial bus. This eliminates the need for separate chip -select control lines between each device and the host controller. Up to six general purpose outputs are provided, which can be used to access internal signals (the LOCK signal, for example) or to control front end components. Both devices operate with a 2.7 V to 3.3 V power supply. Functional Block Diagram Functional Block Diagram – Top View Key Features

  • 85 MHz to 4200 MHz LO Frequency Range
  • Fractional-N Synthesizer with Very Low Spurious Levels
  • Typical Step Size 1.5 Hz
  • Fully Integrated Low Phase Noise VCO and LO Buffers
  • Integrated Phase Noise − 0.18° rms at 1 GHz − 0.52° rms at 3 GHz
  • High Linearity RF Mixer(s)
  • 30 MHz to 6000 MHz Mixer Frequency Range
  • Input IP3 +23 dBm
  • Mixer Bias Adjustable for Low Power Operation
  • Full Duplex Mode (RFFC5071A)
  • 2.7 V to 3.3 V Power Supply
  • Low Current Consumption
  • 3- or 4-Wire Serial Interface

Applications

  • Wideband Radios
  • Distributed Antenna Systems
  • Diversity Receivers
  • Software Defined Radios
  • Frequency Band Shifters
  • Point-to-Point Radios
  • WiMax/LTE Infrastructure
  • Satellite Communications
  • Wideband Jammers
  • Remote Radio Heads RFFC5071A Synth Ref. divider Phase det. RFFC5072A Synth Ref. divider Phase det.

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 2 of 27 www.qorvo.com

Ordering Information

Part No. Description Devices/Container RFFC5071A RFFC5071ASB 32-pin QFN 5-Piece sample bag RFFC5071ASQ 32-pin QFN 25-Piece sample bag RFFC5071ASR 32-pin QFN 100-Piece reel RFFC5071ATR7 32-pin QFN 750-Piece reel RFFC5071ATR13 32-pin QFN 2500-Piece reel DKFC5071A Complete Design Kit (3.7 GHz Baluns) 1 Box RFFC5072A RFFC5072ASB 32-pin QFN 5-Piece sample bag RFFC5072ASQ 32-pin QFN 25-Piece sample bag RFFC5072ASR 32-pin QFN 100-Piece reel RFFC5072ATR7 32-pin QFN 750-Piece reel RFFC5072ATR13 32-pin QFN 2500-Piece reel DKFC5072A Complete Design Kit (3.7 GHz Baluns) 1 Box Absolute Maximum Ratings Parameter Rating Unit Supply Voltage (VDD) -0.5 to +3.6 V Input Voltage (VIN) any pin -0.3 to VDD + 0.3 V RF/IF mixer input power +15 dBm Operating Temperature Range -40 to +85 °C Storage Temperature Range -65 to +150 °C Caution! ESD sensitive device. Exceeding any one or a combination of the Absolute Maximum Rating conditions may cause permanent damage to the device. Extend ed application of Absolute Maximum Rating conditions to the device may reduce device reliability. Specified typical performance or functional operation of the device under Absolute Maxi mum Rating conditions is not implied. Exceeding any one or a combination of the Absolute Maximum Rating conditions may cause perman ent damage to the device. Extended application of Absolute Maximum Rating conditions to the device may reduce device reliability.

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 3 of 27 www.qorvo.com Electrical Specifications Parameter Condition Min Typ. Max Units Operating Conditions Supply Voltage (VDD) 2.7 3.0 3.3 V Temperature (TOP) -40 +85 °C Logic Inputs/Outputs (VDD = Supply to DIG_VDD pin) Input Low Voltage -0.3 +0.5 V Input High Voltage VDD / 1.5 VDD V Input Low Current Input = 0 V -10 +10 A Input High Current Input = VDD -10 +10 A Output Low Voltage 0 0.2*VDD V Output High Voltage 0.8*VDD VDD V Load Resistance 10 kΩ Load Capacitance 20 pF GPO Drive Capability Sink Current At VOL = +0.6 V 20 mA Source Current At VOL = +2.4 V 20 mA Output Impedance 25 Ω Static Supply Current (IDD) with

1 GHz LO

Low current, MIX_IDD = 1, one mixer enabled. 106 mA High linearity, MIX_IDD = 6, one mixer enabled. 132 mA Standby Reference oscillator and bandgap only. 2 mA Power Down Current ENBL = 0 and REF_STBY = 0 300 A Mixer 1/2 (Mixer output driving 4:1 balun) Gain Not including balun losses -2 dB Noise Figure <3000 MHz Low current setting 10 dB High linearity setting 13 dB Noise Figure <4000 MHz Low current setting 11 dB High linearity setting 15 dB IIP3 Low current setting +10 dBm High linearity setting +23 dBm Input Port Frequency Range 30 6000 MHz Mixer Input Return Loss 100 Ω differential 10 dB Output Port Frequency Range 30 4500 MHz Mixer 1/2 (Mixer output driving 1:1 balun) Output Port Frequency Range 30 6000 MHz Gain Not including balun losses -7 dB

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 4 of 27 www.qorvo.com Electrical Specifications Parameter Condition Min Typ Max Units Reference Oscillator External Reference Frequency 10 104 MHz Reference Divider Ratio 1 7 External Reference Input Level AC-Coupled 500 800 1500 mVp-p Synthesizer (PLL Closed Loop, 52 MHz Reference) Synthesizer Output Frequency 85 4200 MHz Phase Detector Frequency 52 MHz Phase Noise (LO = 1 GHz) 10 kHz offset -108 dBc/Hz 100 kHz offset -107 dBc/Hz

1 MHz offset -135 dBc/Hz

RMS integrated from 1 kHz to 40 MHz 0.18 ° Phase Noise (LO = 2 GHz) 10 kHz offset -102 dBc/Hz 100 kHz offset -101 dBc/Hz

1 MHz offset -130 dBc/Hz

RMS integrated from 1 kHz to 40 MHz 0.33 ° Phase Noise (LO = 3 GHz) 10 kHz offset -98 dBc/Hz 100 kHz offset -98 dBc/Hz

1 MHz offset -125 dBc/Hz

RMS integrated from 1 kHz to 40 MHz 0.52 ° Phase Noise (LO = 4 GHz) 10 kHz offset -96 dBc/Hz 100 kHz offset -95 dBc/Hz

1 MHz offset -124 dBc/Hz

RMS integrated from 1 kHz to 40 MHz 0.67 ° Normalized Phase Noise Floor Measured at 20 kHz to 30 kHz offset -214 dBc/Hz Voltage Controlled Oscillator Open Loop Phase Noise at

1 MHz offset

2.5 GHz LO Frequency VCO3, LO Divide by 2 -133 dBc/Hz

2.0 GHz LO Frequency VCO2, LO Divide by 2 -134 dBc/Hz

1.5 GHz LO Frequency VCO1, LO Divide by 2 -136 dBc/Hz

10 MHz offset

2.5 GHz LO Frequency VCO3, LO Divide by 2 -149 dBc/Hz

2.0 GHz LO Frequency VCO2, LO Divide by 2 -150 dBc/Hz

1.5 GHz LO Frequency VCO1, LO Divide by 2 -151 dBc/Hz

LO Input Frequency Range LO Divide by 1 85 4200 MHz LO Input Frequency Range LO Divide by 2 85 5400 MHz External LO Input Level Driven from 50 Source Via a 1:1 Balun 0 dBm

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 5 of 27 www.qorvo.com Pin Names and Descriptions Pin Name Description 1 ENBL/GPO5 Device Enable pin (see note 1 and 2).

2 EXT_LO External local oscillator input (See note 4)

3 EXT_LO_DEC Decoupling pin for external local oscillator (See note 4). 4 REXT External bandgap bias resistor (See note 3). 5 ANA_VDD1 Analog supply. Use good RF decoupling. 6 LFILT1 Phase detector output. Low-frequency noise-sensitive node. 7 LFILT2 Loop filter op-amp output. Low-frequency noise-sensitive node. 8 LFILT3 VCO control input. Low-frequency noise-sensitive node. 9 MODE/GPO6 Mode select pin (See note 1 and 2). 10 REF_IN Reference input. Use AC coupling capacitor. 11 NC 12 TM Connect to ground. 13 MIX1_IPN Differential input 1 (see note 4). On RFFC5072A this pin is NC. 14 MIX1_IPP Differential input 1 (see note 4). On RFFC5072A this pin is NC. 15 GPO1/ADD1 General purpose output / MultiSlice address bit. 16 GPO2/ADD2 General purpose output / MultiSlice address bit. 17 MIX1_OPN Differential output 1 (see note 5). On RFFC5072A this pin is NC. 18 MIX1_OPP Differential output 1 (see note 5). On RFFC5072A this pin is NC. 19 DIG_VDD Digital supply. Should be decoupled as close to the pin as possible. 20 NC Leave circuit open. 21 NC 22 ANA_VDD2 Analog supply. Use good RF decoupling. 23 MIX2_IPP Differential input 2 (see note 4). 24 MIX2_IPN Differential input 2 (see note 4). 25 GPO3/FM General purpose output / frequency control input. 26 GPO4/LD/DO General purpose output / Lock detect output / serial data out. 27 MIX2_OPN Differential output 2. (see note 5). 28 MIX2_OPP Differential output 2. (see note 5). 29 RESETX Chip reset (active low). Connect to DIG_VDD if asynchronous reset is not required. 30 ENX Serial interface select (active low) (See note 1). 31 SCLK Serial interface clock (see note 1). 32 SDATA Serial interface data (see note 1). Exposed Paddle Ground reference, should be connected to PCB ground through a low impedance path. Notes: 1. An RC low-pass filter could be used on this line to reduce digital noise. 2. If the device is under software control this input can be configured as a general purpose output (GPO). 3. Connect a 51 k resistor from this pin to ground. This pin is sensitive to low frequency noise injection. 4. DC voltage should not be applied to this pin. Use either an AC coupling capacitor as part of lumped element matching network or a transformer (see application schematic). 5. This pin must be connected to ANA_VDD2 using an RF choke or transformer (see application schematic).

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 6 of 27 www.qorvo.com Theory of Operation The RFFC5071A and RFFC5072A are wideband RF frequency converter chips which include a fractional-N synthesizer and a low noise VCO core. The RFFC5071A has an LO signal multiplexer, two LO buffer circuits, and two RF mixers. The RFFC5072A has a single LO buffer circuit and one RF mixer. Both devices have an integrated voltage reference and low drop out regulators supplying critical circuit blocks such as the VCOs and synthesizer. Synthesizer programming, device configuration and control are achieved through a mixture of hardware and software controls. All on-chip registers are programmed through a simple 3-wire serial interface. VCO The VCO core in the RFFC5071A and RFFC5072A consists of three VCOs which, in conjunction with the integrated LO dividers of /2 to /32, cover the LO range of 85MHz to 4200 MHz. Each VCO has 128 overlapping bands which are used to achieve low VCO gain and optimal phase noise performance across the whole tuning range. The chip automatically selects the correct VCO (VCO auto-select) and VCO band (VCO coarse tuning) to generate the desired LO frequency based on the values programmed into the PLL1 and PLL2 registers banks. The VCO auto select and VCO coarse tuning are triggered every t ime ENBL is taken high, or if the PLL re -lock self-clearing bit is programmed high. Once the correct VCO and band have been selected the PLL will lock onto the correct frequency. During the band selection process, fixed capacitance elements are progressive ly connected to the VCO resonant circuit until the VCO is oscillating approximately at the correct frequency. The output of this band selection, CT_CAL, is made available in the readback register. A value of 127 or 0 in this register indicates that the coa rse tuning was unsuccessful, and this will also be indicated by the CT_FAILED flag also available in the read -back register. A CT_CAL value between 1 and 126 indicates a successful calibration, the actual value being dependent on the desired frequency as well as process variation for a particular device. The band select process will center the VCO tuning voltage at about 0.8 V, compensating for manufacturing tolerances and process variation as well as environmental factors including temperature. The VCOs have temperature compensation circuits so the PLL will hold lock over the entire operating temperature range of -40 °C to +85 °C. This is true regardless of the temperature at which the VCO band selection is performed. The VCO gain is also held stable across temperature, maintaining consistent loop bandwidth and synthesizer phase noise. The RFFC5071A and RFFC5072A feature a differential LO input to allow the mixer to be driven from an external LO source. The fractional- N PLL can be used with an external VCO driven into this LO input, which may be useful to reduce phase noise in some applications. This may also require an external op-amp, dependent on the tuning voltage required by the external VCO. In the RFFC5071A the LO signal is ro uted to mixer 1, mixer 2, or both mixers depending on the state of the MODE pin (or MODE bit if under software control) and the value of the FULLD bit. Setting FULLD high puts the device into Full Duplex mode and b oth mixers are enabled. Fractional-N PLL The RFFC5071A and RFFC5072A contain a charge pump -based fractional-N phase locked loop (PLL) for controlling the three VCOs. The PLL includes automatic calibration systems to counteract the effects of process and environmental variations, ensuring repeatable loop response and phase noise performance. As well as the VCO auto -select and coarse tuning, there is a loop filter calibration mechanism which can be enabled if required. This operates by adjusting the charge pump current to maintain loop bandwidth. This can be useful for applications where the LO is tuned over a wide frequency range. The PLL has been designed to use a reference frequency of between 10 MHz and 104 MHz from an external source, which is typically a temperature controlled crystal oscillator (TCXO). A reference divider (divide by 1 to divide by 7) is supplied and should be programmed to limit the frequency at the phase detector to a maximum of 52 MHz. Two PLL programming banks are provided, the first bank is preceded by the label PLL1 and the second bank is preceded by the label PLL2. For the RFFC5071A these banks are used to program mixer 1 and mixer 2 respectively,and are selected automatically as the mixer is selected using MODE. For the RFFC5072A mixer 2 and register bank PLL2 are normally used.

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 7 of 27 www.qorvo.com The VCO outputs are first divided down in a high frequency prescalar. The output of this high frequency prescalar then enters the N divider, which is a fractional divider containing a dual -modulus prescaler and a digitally spur -compensated fractional sequence generator. This allows very fine frequency steps and minimizes fractional spurs. The fractional energy is randomized and appears as fractional noise at frequency offsets above 10 0 kHz which will be attenuated by the loop filter. An external loop filter is used, giving flexibility in setting loop bandwidth for optimizing phase noise and lock time, for example. The synthesizer step size is typically 1.5 Hz when using a 26 MHz reference frequency. The exact step size for any reference and LO frequency can be calculated using the following formula: (FREF * P) / (R * 224 * LO_DIV) Where F REF is the reference frequency, R is the reference division ratio, P is the prescalar divisi on ratio, and LO_DIV is the LO divider value. Pin 26 (GPO4) can be configured as a lock detect pin. The lock status is also available in the read-back register. The lock detect function is a window detector on the VCO tuning voltage. The lock flag will be high to show PLL lock which corresponds to the VCO tuning voltage being within the specified range, typically 0.30 V to 1.25 V. The lock time of the PLL will depend on a number of factors; including the loop bandwidth and the reference frequency a t the phase detector. This clock frequency determines the speed at which the state machine and internal calibrations run. A 52 MHz phase detector frequency will give fastest lock times, of typically <50 secs when using the PLL re-lock bit. Phase Detector and Charge Pump The phase detector provides a current output to drive an active loop filter. The charge pump output current is set by the val ue contained in the P1_CP_DEF and P2_CP_DEF fields in the loop filter configuration register. The charge pump current is given by approximately 3 A/bit, and the fields are 6 bits long. This gives default value (31) of 93 A and maximum value (63) of 189 A. If the automatic loop bandwidth calibration is enabled the charge pump current is set by the calibration algorithm based upon the VCO gain. The phase detector will operate with a maximum input frequency of 52 MHz. Loop Filter The active loop filter is implemented using the on-chip low noise op-amp with external resistors and capacitors. The internal configuration of the chip is shown below with the recommended active loop filter. The op -amp gives a tuning voltage range of typically +0.1 V to +2.4 V. The recommended loop filter shown is designed to give the lowest integrated phase noise for r eference frequencies of between 26 MHz and 52 MHz. The external loop filter gives the flexibility to optimize the loop response for any particular application and combination of reference and VCO frequencies.

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 8 of 27 www.qorvo.com 1pF 0.5nH 0.5nH RFFC507xA Mixer Output External Reference The RFFC5071A and RFFC5072A have been designed to use an external reference such as a TCXO. The typical input will be a 0.8 Vp-p clipped sine wave, which should be AC-coupled into the reference input. When the PLL is not in use, it may be desirable to turn off the internal reference circuits, by setting the REFSTBY bit low, to minimize current draw while in standby mode. On cold start, or if REFSTBY is programmed low, the reference circuits will need a warm -up period. This is set by the SU_WAIT bits. This will allow the clock to be stable and immediately available when the ENBL bit is asserted high, allowing the PLL to assume normal operation. If the current consumption of the reference circuits in standby mode, typically 2 mA, is not critical, then the REFSTBY bit can be set high. This allows the fastest startup and lock time after ENBL is taken high. Wideband Mixer The mixers are wideband, double-balanced Gilbert cells. They support RF/IF frequencies from 30 MHz up to 6000 MHz. Each mixer has an input port and an output port that can be used for either IF or RF (in other words, for up - or down-conversion). The mixer current can be programmed to between about 15 mA and 45 mA depending on linearity requirements. The majority of the mixer current is sourced through the output pins via either a center-tapped balun or an RF choke in the external matching circuitry to the supply. The RF mixer input and output ports are differential and require baluns and simple matching circuits optimized to the specific application frequencies. A conversion gain of approximately -2 dB (not including balun losses) is achieved with 100  differential input impedance, and the outputs driving 200  differential load impedance. Increasing the mixer output load increases the conversion gain. The mixer has a broadband common gate input. The input impedance is dominated by the resistance set by the mixer 1/gm term, which is inversely proportional to the mixer current setting. The resistance will be approximately 85  at the default mixer current setting (100). There is also some shunt capacitance at the mixer input, and the inductance of the bond wires (about 0.5 nH on each pin) to consider at higher frequencies. The following diagram is a simple model of the mixer input impedance: The mixer output is high impedance, consisting of approximately 2 k resistance in parallel with some capacitance, approximately 1 pF dependent on PCB layout. The mixer output does not require a conjugate matching network. It is a constant curr ent output which will drive a real differential load of between 50 Ω and 500 Ω, typically 200 Ω. Since the mixer output is a constant current source, a higher resistance load will give higher output voltage and gain. A shunt inductor can be used to resonat e with the mixer output capacitance at the frequency of interest. This inductor may not be required at lower frequencies where the impedance of the output capacitance is less significant. At higher output frequencies the inductance of the bond wires (about 0.5 nH on each pin) becomes more significant. Above about 4500 MHz, it is beneficial to lower the output load to 50  to minimize the effect of the output capacitance. The following diagram is a simple model of the mixer output: 0.5pF Rin Typ 85 0.5nH 0.5nH RFFC507xA Mixer Input

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 9 of 27 www.qorvo.com The RFFC5071A mixer layout and pin placement has been optimized for high mixer-to-mixer isolation of greater than 60 dB. The mixers can be set up to operate in half duplex mode (1 mixer active) or full duplex mode (both mixers active). This selection is done via control of MODE and by setting the FULLD bit. When in full duplex mode, either PLL register bank can be used, the LO signal is routed to both mixers. Mode FULLD Active PLL Register Bank Active Mixer Low 0 1 1 High 0 2 2 Low 1 1 1 and 2 High 1 2 1 and 2 Serial Interface All on-chip registers in the RFFC5071A and RFFC5072A are programmed using a proprietary 3-wire serial bus which supports both write and read operations. Synthesizer programming, device configuration, and control are achieved through a mixture of hardware and software controls. Certain functions and operations require the use of hardware controls via the ENBL, MODE, and RESETB pins in addition to programming via the serial bus. Alternatively, there is the option to control the chip completely via the serial bus The serial data interface can be configured for 4 -wire operation by setting the 4WIRE bit in the SDI_CTRL register high. Then pin 26 is used as the data out pin, and pin 32 is the serial data in pin. Hardware Control Three hardware control pins are provided: ENBL, MODE, and RESETB. The ENBL pin has two functions: to enable the analog circuits in the chip and to trigger the VCO auto -selection and coarse tuning mechanisms. The VCO auto-selection and coarse tuning is initiated when the ENBL pin is taken high. Every time the frequency of the synthesizer is reprogrammed, ENBL has to be asserted high to initiate these mechanisms and then to initiate the PLL locking. Alternatively following the programming of a new frequency, the PLL re-lock self-clearing bit could be used. The RESETB pin is a hardware reset control that will reset all digital circuits to their startup state when asserted low. The device includes a power-on-reset function, so this pin should not normally be required, in which case it should be connected to the positive supply. The MODE pin controls which mixer(s) and PLL programming register bank is active. Serial Data Interface Control The normal mode of operation uses the 3 -wire serial data interface to program the device registers, and three extra hardware control lines: MODE, ENBL and RESETB. When the device is under software control, achieved by setting the SIPIN bit in the SDI_CTRL register high, then the hardware can be controlled via the SDI_CTRL register. When this is the case, the three hardware control lines are not required. If the device is under software control, pins 1 and 9 can be configured as general purpose outputs (GPO).

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 10 of 27 www.qorvo.com Multi-Slice Mode The Multi -Slice mode of operation allows up to four chips to be controlled from a common serial bus. The device address pins (15 and 16) ADD1 and ADD2 are used to set the address of each part. On power up, and after a reset, the devices ignore the address pins ADD1 and ADD2 and any data presented to the serial bus will be programmed into all the devices. However, once the ADDR bit in the SDI_CTRL register is set, each device then adopts an address according to the state of the address pins on the device. General Purpose Outputs The general purpose outputs (GPOs) can be controlled via the GPO register and will depend on the state of MODE since they can be set in different states corresponding to either mixer path 1 or 2. For example, the GPOs can be used to drive LEDs or to control external circuitry such as switches or low power LNAs. Each GPO pin can supply approximately 20 mA load current. The output voltage of the GPO high state will drop with increased current drive by approximately 25 mV/mA. Similarly, the output voltage of the GPO low state will rise with increased current, again by approximately 25 mV/mA. External Modulation The RFFC5071A and RFFC5072A fractional-N synthesizer can be used to modulate the frequency of the VCO. There are two dedicated registers, EXT_MOD and FMOD, which can be used to configure the device as a modulator. It is possible to modulate the VCO in two ways: 1.Binary FSK The MODSETUP bits in the EXT_MOD register are set to 11. GPO 3 is then configured as an input and used to control the signal frequency. The frequency deviation is set by the MODSTEP and MODULATION bits in the EXT_MOD and FMOD registers respectively. The modulation frequency is calculated according to the following formula: FMOD = 2MODSTEP  FPD  (MODULATION)  216 Where MODULATION is a 2's complement number and FPD is the phase detector frequency 2.Continuous Modulation The MODSETUP bits in the EXT_MOD register are set to 01. The frequency deviation is set by the MODSTEP and MODULATION bits in the EXT_MOD and FMOD registers respectively. The VCO frequency is then changed by writing a new value into the MODULATION bits, the VCO frequency is instantly updated. An arbitrary frequency modulation can then be perform ed dependent only on the rate at which values are written into the FMOD register. Slice 2 (0) Slice 2 (1) A1 A2 A1 A2 Vdd Slice 2 (2) A2A1 Vdd Slice 2 (3) A2A1 Vdd Vdd ENX SDATA SCLK

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 11 of 27 www.qorvo.com The modulation frequency is calculated according to the following formula: FMOD = 2MODSTEP  FPD  (MODULATION)  216 Where MODULATION is a 2's complement number and FPD is the phase detector frequency Programming Information The RFFC5071A and RFFC5072A share a common serial interface and control block. Please refer to the Register Maps and Programming Guide which are available for download from https://www.qorvo.com/products/d/da000718. Evaluation Boards Evaluation boards for RFFC5071A and RFFC5072A are provided as part of a design kit, along with the necessary cables and programming software tool to enable full evaluation of the device. Design kits can be ordered from www. qorvo.com or from local Qorvo sales offices and authorized sales channels. For ordering codes please see “Ordering Information” on page 2. For further details on how to set up the design kits go to https://www.qorvo.com/products/d/da000718. The standard evaluation boards are configured with 3.7 GHz ceramic baluns on the RF ports and wideband transformers on the IF ports. On the RFFC5071A evaluation board, mixer 1 is configured for down -conversion and mixer 2 is configured for up -conversion. On the RFFC5072A evaluation board, mixer 2 is configured for down conversion.

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 12 of 27 www.qorvo.com Detailed Functional Block Diagram Note: Wideband transmission line transformer baluns shown above for operation to ~2.5 GHz. Substitute baluns for higher frequency applications as required. RFFC5071A Only Ext LO Mux Pre- scaler N divider Reference divider Sequence generator Phase detector Charge pump Loop Filter MODE ENBL RESET ENX SDATA SCLK Control Control Lines 3-Wire Serial Bus GPO RFXF8553 4:1 Balun +3V OP2 RFXF9503 1:1 Balun IP2 /2n [n=1..5] Mixer 2 51K Biasing & LDOs +3V RFXF8553 4:1 Balun +3V OP1 Mixer 1 RFXF9503 1:1 Balun IP1 XO Lock Flag

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 13 of 27 www.qorvo.com RFFC5071A Pin Out RFFC5072A Pin Out Exposed paddle 2526283032 31 ENBL/GPO5 EXT_LO EXT_LO_DEC REXT ANA_VDD1 LFILT1 LFILT2 LFILT3 MIX2_IPN MIX2_IPP ANA_VDD2 NC NC DIG_VDD MIX1_OPP MIX1_OPN MODE/GPO6 5 20 2729 223 9 10 11 12 13 14 15 16 REF_IN NC TM MIX1_IPN MIX1_IPP GPO1/ADD1 GPO2/ADD2 SDATA SCLK ENX RESETX MIX2_OPP MIX2_OPN GPO4/LD/DO GPO3/FM

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 14 of 27 www.qorvo.com Wideband Application Schematic (<2.5 GHz) RFFC5071A Only ENBL EXT_LO EXT_LO_DEC RE XT ANA_VDD1 LFILT1 LFILT2 LFILT3 MIX2_IF_IO2N MIX2_IF_IO2P ANA_VDD2 NC NC DIG_VDD MIX1_IF_IO2P MIX1_IF_IO2N MODE XTALP XTALN TM MIX1_IO1N MIX1_IO1P GPIO1 GPIO2 GND RFFC5071A_RFFC5072A SDATA SCLK ENX RESETX MIX2_IO1N MIX2_IO1P GPIO4 GPIO31 LFILT1 LFILT2 LFILT3 C34 10nF 33pF VDD A1 C36 33nF 51K MODE 470R VCTCXO C44 10nF C43 10nF C16 1nF VDD A2 VDD A2 100pF C30 RF XF 9503 4RF_IP1_P RF_IP1_N 1 3 T4 GPIO2 GPIO1 +2.8V R31 120R 470 R R32 GND OUT VC VCC C35 33pF GPIO3 GPIO4 GREEN 100pF C29 50Ω RF_ IP1 LFILT1 LFILT2 22K 180pF C10 330pF C17 330pF R2 470R R6 470R LFILT3 8.2pF Loop Filter 33pF ENBL SDATA SCLK ENX RESETX RF_OP2_N RF_OP2_P R25 220R D1 LOCK DETECT LED C23 100pF 100pF VDD A2 C21 100pF RF XF 9503 3 T2 C21 100pF 50Ω 50Ω RF_OP2 RF_IP2 RF_OP2 33pF VDD A2 C18 10nF 33pF VDD D C19 10nF T3 C27 100pFVDD A2 RF_OP1_P RF_OP1_N C26 100pF RF XF 8553 50Ω RF_IP2 RF_OP1 1RF_OP1 RF_IP1 C13 33pF C14 33pF C15 33pF C20 100pF RF_IP2_N RF_IP2_P C28 100pF RF XF 8553

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 15 of 27 www.qorvo.com Narrowband 3.7 GHz Application Schematic RFFC5071A Only ENBL EXT_LO EXT_LO_DEC RE XT ANA_VDD1 LFILT1 LFILT2 LFILT3 MIX2_IF_IO2N MIX2_IF_IO2P ANA_VDD2 NC NC DIG_VDD MIX1_IF_IO2P MIX1_IF_IO2N MODE XTALP XTALN TM MIX1_IO1N MIX1_IO1P GPIO1 GPIO2 GND RFFC5071A_RFFC5072A SDATA SCLK ENX RESETX MIX2_IO1N MIX2_IO1P GPIO4 GPIO31 LFILT1 LFILT2 LFILT3 C34 10nF 33pF VDD A1 C36 33nF 51K MODE 470R VCTCXO C44 10nF C43 10nF C16 1nF VDD A2 VDD A2 RF_IP1_P RF_IP1_N GPIO2 GPIO1 +2.8V R31 120R 470 R R32 GND OUT VC VCC C35 33pF GPIO3 GPIO4 GREEN 50Ω RF_ IP1 LFILT1 LFILT2 22K 180pF C10 330pF C17 330pF R2 470R R6 470R LFILT3 8.2pF Loop Filter 33pF ENBL SDATA SCLK ENX RESETX RF_OP2_N RF_OP2_P R25 220R D1 LOCK DETECT LED C23 100pF RF XF 9503 3 T2 C21 100pF 50Ω 33pF VDD A2 C18 10nF 33pF VDD D C19 10nF T3 C27 100pFVDD A2 IF_OP1_P IF_OP1_N C26 100pF 50Ω IF_OP1 1IF_OP1 RF_IP1 C13 33pF C14 33pF C15 33pF IF_IP2_N IF_IP2_P C28 100pF RF XF 8553 JOHNSON 3700BL1 5B050 Mixer 1 Down Conversion Circuit C29 15pF C30 15pF 50Ω JOHNSON 3700BL1 5B200 Mixer 2 Up Conversion Circuit IF_IP2 J2 IF_IP2 RF_OP2 J1 RF_OP2 L 3.3nH VDD A2

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 16 of 27 www.qorvo.com Typical Synthesizer Performance Characteristics VDD = +3 V and TA = +27 °C unless stated.

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 17 of 27 www.qorvo.com Typical Synthesizer Performance Characteristics VDD = +3 V and TA = +27 °C unless stated. Notes: 1. 26 MHz Crystal Oscillator: NDK ENA3523A 2. 52 MHz Crystal Oscillator: NDK ENA3560A

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 18 of 27 www.qorvo.com Typical VCO Performance Characteristics VDD = +3 V and TA = +27 °C unless stated.

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 19 of 27 www.qorvo.com Typical Supply Current Performance Characteristics VDD = +3 V and TA = +27 °C unless stated. RFFC5071A Typical Operating Current in mA in Full Duplex Mode Both mixers enabled, LO Frequency of 1000 MHz, +3 V supply MIX2_IDD MIX1_IDD 1 2 3 4 5 6 7 1 129 134 139 144 149 154 159 2 134 139 144 150 155 160 165 3 139 144 150 155 160 165 170 4 144 150 155 160 165 170 175 5 149 155 160 165 170 175 180 6 154 160 165 170 175 180 185 7 159 164 170 175 180 185 190

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 20 of 27 www.qorvo.com Typical RF Mixer 1 Performance Characteristics VDD = +3 V and TA = +27 °C unless stated. As measured on RFFC5071A wideband evaluation board. See application schematic on page 14.

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 21 of 27 www.qorvo.com Typical RF Mixer 2 Performance Characteristics VDD = +3 V and TA = +27 °C unless stated. As measured on RFFC5071A wideband evaluation board. See application schematic on page 14.

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 22 of 27 www.qorvo.com Typical Performance Characteristics of Both RF Mixers VDD = +3 V and TA = +27 °C unless stated. As measured on RFFC5071A wideband evaluation board. See application schematic on page 14.

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 23 of 27 www.qorvo.com Typical Performance Characteristics at 3.7 GHz VDD = +3 V and TA = +27 °C unless stated. As measured on RFFC5071A 3.7 GHz narrowband evaluation board. Down conversion. See application schematic on page 15.

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 24 of 27 www.qorvo.com Typical Performance Characteristics at 3.7 GHz VDD = +3 V and TA = +27 °C unless stated. As measured on RFFC5071A 3.7 GHz narrowband evaluation board. Up conversion. See application schematic on page 15, L1 = 3.3 nH.

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 25 of 27 www.qorvo.com Typical Performance Characteristics at 3.7 GHz VDD = +3 V and TA = +27 °C unless stated. As measured on RFFC5071A 3.7 GHz narrowband evaluation board. Up conversion. See application schematic on page 15, L1 = 3.9 nH.

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 26 of 27 www.qorvo.com Package Drawing QFN, 32-pin, 5 mm x 5 mm Package Drawing QFN, 32-pin, 5 mm x 5 mm Top View

WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6 GHz MIXER Data Sheet Rev. D, August 22, 2019 | Subject to change without notice 27 of 27 www.qorvo.com Handling Precautions Parameter Rating Standard Caution! ESD-Sensitive Device ESD – Human Body Model (HBM) Class 1C ESDA / JEDEC JS-001-2012 ESD – Charged Device Model (CDM) Class C4 JEDEC JESD22-C101C MSL – Moisture Sensitivity Level Level 2 IPC/JEDEC J-STD-020 Solderability Solder profiles available upon request. Contact plating: NiPdAu RoHS Compliance This part is compliant with 2011/65/EU RoHS directive (Restrictions on the Use of Certain Hazardous Substances in Electr ical and Electronic Equipment) as amended by Directive 2015/863/EU. This product also has the following attributes:

  • Lead Free
  • Halogen Free (Chlorine, Bromine)
  • Antimony Free
  • TBBP-A (C15H12Br402) Free
  • PFOS Free
  • SVHC Free Contact Information For the latest specifications, additional product information, worldwide sales and distribution locations: Web: www.qorvo.com Tel: 1-844-890-8163 Email: customer.support@qorvo.com Important Notice The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information con tained herein and assumes no responsibility or liability whatsoever for the use of the information contained herein. All informatio n contained herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for Qorvo products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anythin g described by such information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED HEREIN, AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PERFORMANCE, USAGE OF TRADE OR OTHERWISE, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death. Copyright 2019 © Qorvo, Inc. | Qorvo is a registered trademark of Qorvo, Inc. Pb