Power Management

ACT43750

Qorvo, Inc

RF POL Drain-Switch Driver / Gate-bias Regulator Rev. F, February 10, 2025

Manufacturer: Qorvo, Inc

Document: 43 Pages / 2Mb

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RF POL Drain-Switch Driver / Gate-bias Regulator Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 1 of 43 www.qorvo.com © 2024 Qorvo US, Inc. All rights reserved. BENEFITS and FEATURES

Wide Operating Range
Vin = 10V to 55V
Vgate = -6V to -1.5V
RF PA Biasing Solution
Turn on and off sequencing
Negative gate voltage supply
Supports GaN and Silicon FETs
High-speed drain switching
Autonomous Bias Point Calibration
Autonomous IDQ(DRAIN) calibration
Resistor Setpoint Range: 10mA to 2A
Digitally adjustable ±31% of setpoint in 1% steps
Space and Cost savings
Fully integrated gate drive voltage
High switching frequency: 2.05 MHz
Integrated FETs and small chip inductor
37-pin, 5 mm x 5 mm, 0.4-mm pitch QFN package
High-Performance Negative Gate Drive Supply
REGG input voltage: +12V (TYP)
REGG output voltage: -6V to -1.5V by 732µV step
REGG output source current: 300mA
REGG output sink current: -100mA
REGG output noise: <200µVRMS
Protection
UVLO, OVLO, OVP, UVP, OCP, TSD

APPLICATIONS

Military Radar System
Civilian Radar System
RF GaN / GaAs PA Power Supply GENERAL DESCRIPTION The ACT43750, part of Qorvo’s RF POL regulator family, is the last stage of a three -chip radar power supply so- lution. This three -stage solution, developed with the ACT43950, ACT43850, and ACT43750, forms a com- pact, complete power supply system for radio frequency (RF) power amplifiers (PAs) that demand fast transient, high current pulse loads. The first stage, ACT43950 converts a high voltage dc input voltage into a regulated dc constant-current (CC) to charge bulk capacitor. The second stage, ACT43850, regulates the capacitor volt- age into a tightly regulated DC volta ge to power the drain for GaN RF power amplifiers. The third stage, ACT43750, provides several functions specifically designed to optimize GaN performance. It operates either standalone or as the third stage in a multiple stage power solution. It provides the RF PA negative gate voltage using an ultra-low noise inverting buck dc-to-dc regulator with integrated FETs and pro- grammable voltage reference. It provides the required GaN power up and power down sequencing between the drain and gate voltages. All GaN RF PAs require calibrating the gate voltage to set the desired operating point. The ACT43750 automatically calibrates and stores the optimal gate voltage. This operating point changes with time and temperature. The IC can recal- culate and adjust the optimal gate voltage in the field without waiting for a maintenance cycle. The ACT43750 also enables drain switching in pulsed radar applica- tions. The ACT43750 is available in a 37 -pin, 5 mm x 5 mm, 0.4 mm pitch QFN package.

ORDERING INFORMATION

(LSR regulator) Targeted Qorvo RFPA ACT43750-101T -4.5V -1.5V GaN 5V Generic Use ACT43750-102T (proposed functions) -4.5V -1.5V Si 10V Generic Use ACT 43750 -xxx T CMI Option Product Number Tape and Reel Note 1: Standard product options are identified in this table. Contact the factory for custom options, a minimum order quantity is required. Note 2: “xxx” represents the CMI (Code Matrix Index) option The CMI identifies the IC’s default register settings.

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 5 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator PIN CONFIGURATION (pin removed) V50 1 PGND 2 AGND 3 XINT 4 V5 5 SDA 6

11 ENCAL

12 SYNC

13 CONF

25 LSR

24 V12

23 GSW

35 HSGU

36 CSPA

33 BT50

34 HSGD15 REFIN

21 COMP

32 VD16 NTC

17 ENG

27 LSGD

26 LSGU

28 PGND

10 ENTX

19 GV5

20 GREF

29 CPL

30 CPH

31 CALG

37 CSCAL

(pin removed) SCL 7 (pin removed) Figure 3: Pin Configuration – Top View – 37 pin QFN, 5 mm x 5mm, 0.4 mm pitch

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 6 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator PIN DESCRIPTIONS Pin NAME DESCRIPTION 1 V50 Input power to the DSW50 control section of the IC. 2, 28 PGND Dedicated power ground for the DSW50 gate drive. Connect to AGND with a Kelvin connection. 3 AGND Ground pin for the analog blocks. Connect to PGND with a Kelvin connection. 4 XINT Interrupt output. Open drain. Connect it through a pull-up resistor to V5. 5 V5 5V Bias regulator output. Requires a 2.2uF capacitor to AGND

6 SDA I2C Data Pin for Slave mode

7 SCL I2C Clock Pin for Slave mode

8 SCL50 I2C Data Pin for Master mode

9 SDA50 I2C Clock Pin for Master mode

10 ENTX Enable input for the DSW50 block. Don't float this pin. Connect it through a 100kΩ resistor to AGND. ENTX pin needs to be logic low when startup. 11 ENCAL Enable input to start an autocalibration routine. Don't float this pin. Connect it through a 100kΩ resistor to AGND.

12 SYNC External clock synchronization input

13 CONF External configuration resistor input. Connect a resistor between CONF and V5 and between CONF and AGND to configure IC settings. 14 RT Sets the negative gate voltage switching frequency. Connect a resistor between RT and AGND. 15 REFIN External voltage reference input. Leave open if not used. 16 NTC Negative temperature coefficient resistor input. 17 ENG Enable input for the REGG block (negative voltage regulator). Don't float this pin. Connect it through a 100kΩ resistor to AGND. 18 PG Power good output. Open drain. Connect it through a pull-up resistor to V5. 19 GV5 Floating negative gate voltage output. Connect a 2.2uF capacitor between GV5 and VG. 20 GREF The local voltage reference for the REGG output. Connect a 100nF capacitor between GREF and VG. 21 COMP Compensation input. Connect a 470pF capacitor between COMP and VG. 22 VG Feedback input for the REGG output. Connect a 10nF capacitor between VG and V12. 23 GSW REGG switching node. 24 V12 External 12V bias input pin. Connect a 10uF capacitor between V12 and PGND. Connect a 10nF capaci- tor between V12 and VG. 25 LSR Low-side gate drive regulator for the DSW50 block. Connect a 2.2uF capacitor between LSR and PGND. 26 LSGU Pullup output for the low-side FET gate. 27 LSGD Pulldown output for the low-side FET gate. 29 CPL High-side gate drive regulator flying capacitor terminal. Connect a 47nF capacitor and a 33Ω resistor in series between CPL and CPH. 30 CPH High-side gate drive regulator flying capacitor terminal. Connect a 47nF capacitor and a 33Ω resistor in series between CPH and CPL. 31 CALG Calibration FET gate output. 32 VD DSW50 output voltage for the high side FET. Connect a 10uF capacitor between VD and BT50. 33 BT50 High-side gate drive regulator bootstrap output. Connect a 10uF capacitor between BT50 and VD. 34 HSGD Pulldown output for the high-side FET gate. 35 HSGU Pullup output for the high-side FET gate.

36 CSPA Overcurrent sense resistor input for the drain FET

37 CSCAL Calibration current sense resistor input for the calibration FET. - Exposed PAD Exposed thermal pad. Connect directly to PGND.

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 7 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator ABSOLUTE MAXIMUM RATINGS (NOTE 1) (NOTE 2) Parameter Value Unit V50 -0.3 to +65 V VCSPA, VCSCAL (Referenced to V50) -5 to +0.3 V VBT50 (Referenced to VD) -0.3 to +10 V VD -0.3 to (V50 + 0.3) V V12 -0.3 to +15.0 V VSDA, VSCL, VSCL50, VSDA50, VENCAL, VENG, VPG, VXINT, VENTX, VSYNC, VNTC, VREFIN, VCONF ‒0.3 to +6.0 V VG ‒10.0 to +0.3 V VGSW – with respect to VG ‒0.3 to (|V12 ‒ VPGND| + 0.3) V VAGND to VPGND ‒0.3 to +0.3 Junction to Case Thermal Resistance (Note 3) 6.03 oC/W Junction to Ambient Thermal Resistance (Note 3) 24.37 oC/W Operating Junction temperature -40 to 125 oC Storage temperature -55 to 150 oC V_ESD_HBM (All pins) (Human body model per JEDEC JS-001) 2500 V V_ESD_CDM (All pins) (Charged device model JEDEC JS-002) 1250 V MSL MSL3 Note 1: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: All voltages with respect to PGND unless otherwise noted. Note 3: Measured on Qorvo Evaluation board, which has 1oz copper and 163.5mm x 229mm board area.

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 8 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator RECOMMENDED OPERATING CONDITIONS Parameter Min. Typ. Max. Units V12: Supply voltage +10.8 +12.0 +13.2 V V50: Supply voltage +10.0 +55 V VCSPA, VCSCAL, VD: DSW50 block voltage 0 V50 IO(V5): V5 bias output current 20 mA VREFIN, VNTC, VCONF: Analog input voltage 0 +5.0 V VENCAL, VENG, VENTX, VSYNC: Logic input voltage 0 +5.5 V VSDA, VSCL, VPG, VXINT: Open-drain pull-up voltage +3.3 +5.5 V IOL(SDA), IOL(SDA50), IOL(SCL50), IOL(PG), IOL(XINT): Current into open-drain pins +1 mA L1: REGG output filter coil value 6.8 µH CGATE: REGG output filter capacitor value 22 µF CCOMP: REGG loop compensation capacitance 470 pF RRT: REGG switching frequency programming resistance 120 kΩ CTOTAL(SCL50), CTOTAL(SDA50): Total bus-node capacitance 400 pF All voltage values are to ground unless otherwise specified. The AGND and PGND pins are shorted together with the shortest PCB traces.

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 9 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator ELECTRICAL SPECIFICATIONS VD = V50 = 50V, V12 = 12V, VG = ‒2.5V, VBT50 = 55.2V, VSCL = VSDA = VENCAL = VENG = VENTX = VSCL50 = VSDA50 = VNTC = 5V, VREFIN = 0V, TA = ‒40 to +125 °C, unless otherwise specified Parameter Conditions Min Typ Max Units Supply Rails, System Main IQ(V12) V12 Standby Current VSDA=VSCL=VENTX=VENCAL=VENG=0V 1.5 mA II(V12) V12 Consumption Current 4 mA VIT+(OV12) V12 Input Over Voltage 14 V VIT-(UV12) V12 Input Under Voltage 10 V II(V50,H) V50 Consumption Current VD = 50V 200 µA II(V50,L) V50 Consumption Current VD = 0V 200 µA VIT+(OV50) V50 Input Over Voltage 65 V VIT+(UV50) V50 Input Under Voltage 10 V TSD Thermal Shutdown TJ, die temperature rising to disable 160 oC TSD(OFF) Thermal Shutdown Release TJ, die temperature falling to enable 145 oC TWARN Thermal Warning TJ, die temperature warning 140 oC REFERENCE SYSTEM V5 V5 Bias Regulator Output Voltage IO(V5) = 0 to 20 mA 4.85 5 5.15 V RPD(REFIN) REFIN Input Pull-down Resistance REFIN to AGND 100 kΩ VGREF/VREFIN REFIN to GREF Conversion Ratio (ratio of the floating reference voltage to the external reference voltage) (VGREF - VG)/(VREFIN – VAGND), external reference level-shift gain Δ(VGREF/VREFIN) REFIN to GREF Conversion Ratio (VGREF - VG)/(VREFIN – VAGND), VREFIN = 0.75 V and 3.0 V 99% 101% VGREF/VDACG VDACG to GREF Conversion Ratio (ratio of the floating reference voltage to the DAC voltage) (VGREF - VG)/(VDACG – VAGND), internal DAC level- shift gain VREFIN(MAX) REFIN Window-comparator Threshold High-side valid input window 3.0 V VREFIN(MIN) REFIN Window-comparator Threshold Low-side valid input window, Below device-internal DACG value VDACG ΔVGREF, DAC DACG Reference Accuracy VGREF difference DACG[12:0] code from “N-1” to “N” 0 + 366 µV

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 10 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator Parameter Conditions Min Typ Max Units VT+(GREF,chg) GREF Io(GREF) Fast-Charge Upper Threshold ((Internal reference) – VGREF) threshold to use Io(GREF) fast-charging. And hysteresis points to exit. See Reference Voltage Noise Reduction. > +35 mV VT+(GREF, hys) GREF Io(GREF) Fast-Charge Upper Hysteresis <+20 mV VT-(GREF, chg) GREF Io(GREF) Fast-Charge Lower Threshold <-35 mV VT-(GREF, hys) GREF Io(GREF) Fast-Charge Lower Hysteresis >-20 mV Ro(GREF, chg) GREF Io(GREF) Fast-Charge Output Resistance During Io(GREF) fast-charging 480 Ω Ro(GREF) GREF Output Resistance 0xEh [3:2] = 00 0.5 kΩ 0xEh [3:2] = 01 4.5 kΩ 0xEh [3:2] = 10 25 kΩ 0xEh [3:2] = 11 250 kΩ IO(GREF) GREF Pre-Charge Current 0xEh [1:0] = 00 5 µA 0xEh [1:0] = 01 10 µA 0xEh [1:0] = 10 100 µA 0xEh [1:0] = 11 200 µA VLSR LSR Voltage Reference All 0x0Fh [3:0] options -5% +5% V I2C Slave for MCUs/Controllers VIT+(SCL),VIT+(SDA) SCL, SDA Input Threshold Falling edge for HLOGIC 0.55 V VIT-(SCL),VIT-(SDA) Rising edge for HLOGIC 1.25 V ILKG(SDA) SDA Leakage Current VSDA = 5V 1 µA VOL(SDA) SDA Output Voltage 5mA Current into SDA pin 0.35 V CI(SCL), CI(SDA) SCL, SDA Terminal Capacitance 10 pF I2C Master for ACT43850 and External Memory VIT+(SDA50) SDA50 Input Threshold Falling edge for HLOGIC 0.55 V VIT-(SDA50) Rising edge for HLOGIC 1.25 V ILKG(SCL50) ILKG(SDA50) SCL50, SDA50 Leakage Current VSCL50 = VSDA50 = 5 V 1 µA VOL(SCL50) VOL(SDA50) SCL50, SDA50 Output Voltage 5mA Current into SDA50 and SCL50 pins 0.35 V CI(SCL50), CI(SDA50) SCL50, SDA50 Terminal Capacitance 10 pF RPU(SDA50),RPU(SCL50) SDA50, SCL50 Pull-up Resistance Internal pull-up 3.3 kΩ

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 11 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator Parameter Conditions Min Typ Max Units Logic I/O VOL(PG),VOL(XINT) PG, XINT Output Voltage 1 mA Current into the device from the PG, XINT pin 0.4 V VIT+(SYNC) SYNC Input Threshold VSYNC rising edge detection 1.425 1.5 1.575 V VHYS(SYNC) SYNC Input Hysteresis VSYNC falling edge detection -0.1 V VIT+ ENCAL, ENG, ENTX, PG Input Threshold Rising edge for HLOGIC 1.25 V VIT- ENCAL, ENG, ENTX, PG Input Threshold Falling edge for HLOGIC 0.55 V Signal Pin I/O VIT-(NTC) NTC Input Threshold Falling to detect over temp, ratio to VV5 28%*VV5 30%*VV5 32%*VV5 V VIT+(NTC) NTC Input Threshold Rising to recover, hysteresis 0.1 V VIT+(CSCAL) CSCAL Comparator Threshold Voltage IDQAdj[5:0]=0x00h, (V50-VCSCAL), TA = 25 oC -1% 1.5 +1% V IDQAdj[5:0]=0x00h, (V50-VCSCAL) -2% 1.5 +2% V ΔVCSCAL CSCAL Threshold Programming Resolution 15 mV/Step NCSCAL CSCAL Threshold Programming Steps -31 +31 Steps VDIS(V50) V50 Discharge Detection Threshold (V50 – VCSCAL) 0.4 V VIT+(CSPA) CSPA Input Threshold Rising to detect PA drain over current 30 35 40 mV VHYS(CSPA) CSPA input hysteresis Falling to release -20 mV DSW50 Gate Drivers RPU(HSGU) HSGU High-side Driver Pull- up Output Resistance 2 4 Ω RPD(HSGD) HSGD High-side Driver Pull- down Output Resistance 1 2 Ω RPU(LSGU) LSGU Low-side Driver Pull-up Output Resistance 2 4 Ω RPD(LSGD) LSGD Low-side Driver Pull- down Output Resistance 1 2 Ω REGG Regulator System VG/VGREF GREF to VG Conversion Ratio (ratio of the gate voltage to the floating reference voltage) (VG – VPGND) / (VGREF – VG) gain of REGG as VG floating circuit. VG is referenced to PGND and VGREF is referenced to VG. VG VG Feedback Voltage Accuracy -1% +1% V VIT-(PG) PG Detection Threshold Ratio of (VG – VPGND) / (VGREF – VG) 89.5 92 % VHYS(PG) PG Detection Hysteresis 0.8 % IOCP REGG Over Current Protection 1 A VIT-(OVP) VG Over Voltage Protection Ratio of (VG – VPGND) / (VGREF – VG) 106.5 109.5 % VIT+(UVP) VG Under Voltage Protection Ratio of (VG – VPGND) / (VGREF – VG) 89 91 %

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 12 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator Note 1, Operating below the minimum pulse width moves the IC to the Error Bias State. To return to normal operation, turn off the drain supply voltage and bias voltage, then power up normally. Parameter Conditions Min Typ Max Units Clock System fSYNC SYNC Clock Input Frequency Range Difference from the target set by RRT -20 +20 % DSYNC SYNC Clock Input Pulse Duty Cycle 60 % I2C Slave for MCUs/Controllers fSCL SCL Clock Frequency (no internal time out) 0 1000 kHZ tLOW(SCL) SCL Pulse Width, Low 0.5 µs tHIGH(SCL) SCL Pulse Width, High 0.26 µs tSU(SDA) SDA Set-up Time 50 ns tH(SDA) SDA Hold Time 0 ns tFALL(SDA) SDA Fall Time SDA pull-up to 5V source via 10kΩ 120 ns tSU(START) I2C START Set-up Time 260 ns tSU(STOP) I2C STOP Set-up Time 260 ns I2C Master for ACT43850 and external I2C Memory tFALL(SDA50) SDA50 Fall Time Slave devices (ACT43850 and external I2C memory) driving SDA50 120 ns Logic I/F tL(Logic) (Note 1) ENCAL, ENG, ENTX, PG Pulse Width, Low Minimum pulse width 40 µs tH(ENTX) (Note 1) ENTX Pulse Width, High Minimum pulse width 12 µs

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 13 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator VD = V50 = 50V, V12 = 12V, VG = ‒2.5V, VBT50 = 55.2V, VSCL = VSDA = VENCAL = VENG = VENTX = VSCL50 = VSDA50 = VNTC = 5V, VREFIN = 0V, TA = ‒40 to +125 °C, unless otherwise specified Parameter Conditions Min Typ Max Units I2C Master for ACT43850 and external I2C memory fSCL50 SCL50 Output Clock Frequency 0x17h [3:2] = 00 100 kHz 0x17h [3:2] = 01 200 kHz 0x17h [3:2] = 10 333 kHz 0x17h [3:2] = 11 1000 kHz tLOW(SCL50) SCL50 Pulse Width, Low 50% x (1/fSCL50) µs tHIGH(SCL50) SCL50 Pulse Width, High 50% x (1/fSCL50) µs tSU(SDA) SDA50 Set-up Time 25% x (1/fSCL50) ns tH(SDA) SDA50 Hold Time 25% x (1/fSCL50) ns tSU(START50) I2C START Set-up Time 50% x (1/fSCL50) ns tSU(STOP50) I2C STOP Set-up Time 50% x (1/fSCL50) ns IDRAIN Calibrator NAUTOCal Delta-calibration Automatic Re-Calibration Cycles 100 cycle DSW50 Gate Drivers tDEAD Deadtime range (note 1) -30 100 ns tR(HSGU) HSGU Turn ON Time 10% to 90%, no gate resistor CGATE(FET) = 1.3nF 15 ns tF(HSGD) HSGD Turn OFF Time 90% to 10%, no gate resistor, CGATE(FET) = 1.3nF 8 ns tR(LSGU) LSGU Turn ON Time 10% to 90%, no gate resistor CGATE(FET) = 1.3nF 15 ns tF(LSGD) LSGD Turn Off Time 90% to 10%, no gate resistor, CGATE(FET) = 1.3nF 8 ns tD(CAL-TX) Wait Time before ENTX Ready (Internal calibration comp) to ENTX ready 10 ms tD(HSGU) HSGU Propagation Delay ENTX ↑ to HSGU = H 100 ns tD(LSGU) LSGU Propagation Delay ENTX ↓ to LSGU = L 100 ns tD(PG, Rise) PG Propagation Delay From internal PG detection to VPG up 5 µs tD(PG, Fall) PG Propagation Delay From internal PG detection to VPG down 0.2 µs

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 14 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator VD = V50 = 50V, V12 = 12V, VG = ‒2.5V, VBT50 = 55.2V, VSCL = VSDA = VENCAL = VENG = VENTX = VSCL50 = VSDA50 = VNTC = 5V, VREFIN = 0V, TA = ‒40 to +125 °C, unless otherwise specified Note 1:Specified as a device internal logic delay, not an actual dead time at the VD pin REGG Regulator System fsw(MIN) REGG Minimum Switching Frequency RRT = 215kΩ -5% 1080 +5% kHz fsw(MAX) REGG Maximum Switching Frequency RRT = 115kΩ -10% 2050 +10% kHz fSPSP REGG Spread-Spectrum Dithering Range +/-7 % NSPSP REGG Spread-Spectrum Cycle 64 cycle tMIN(GSW) GSW Output Pulse, MIN 50 ns tMAX(GSW) GSW Output Pulse, Max 50% x (1/fSW) tH(GREF) GREF Holding Time Operation change from IO(GREF) to RO(GREF) 5 ms fC Unity Gain Frequency/Loop Bandwidth 10% fsw Hz PM Phase Margin 45o Gain 100 Hz Gain 60 dB

© 202 Qorvo US, Inc. All rights reserved. quencing solution for RF GaN FET radar applications. ogy to support fast drain-switching radar applications. power, bias power, and current faults. ments in the Electrical Characteristics Table. more details about each register’s function. shows all available I2C slave address options. Table 1. ACT43750 I2C Addresses

Scans to check if companion devices are on the Master I2C bus.
Enable and disable the ACT43850 companion IC.
Provide bypass control from a system-host, through the ACT43750 to the ACT43850.
Program or adjust the ACT43850 output voltage. This is the RF PA drain voltage.
Read an external I2C memory IC to set the ACT43850 output voltage.
Read an external I2C memory IC to set the ACT43750 Idq calibration current.
Read an external I2C memory IC to set the ACT43750 negative gate voltage. A system host, via the I 2C Slave, can turn ON or OFF the I2C master block using register 0x17h [1]. The host can also change the I2C master clock speed using reg- ister 0x17h [3:2]. Scanning for I2C Companion Devices The IC automatically scans for I2C slave devices on the Master bus when the state machine enters the REG50 Ramp state. Th e Master bus can only have a single ACT43850 connected. It can also have a single I 2C memory device connected. If an ACT43850 slave de- vice is found, the IC sets register 0x99h [0] = 1 and stores the slave’s I 2C address in register 0x9 8 [7:1]. If an I2C memory device is found, the ACT43750 sets reg- ister 0x99h [1] to 0. I2C Bypass The ACT43750 provides an I 2C bridge logic between the I2C Slave and the I2C Master blocks. A system host can turn on the bypass function by setting register 0x17h [0] = 1. In bypass mode, the ACT43750 will pass- through commands from the system host on the Slave bus (SDA, SCL), to the ACT43850 on the Master bus(SDA50, SCL50). It also transfers the ACT43850 re- sponses back to the system host. To avoid communication issues, when the ACT43750 executes I2C on the Master bus, it sets register 0x99h [2] = 1 to let the system host know that it must wait until the Master bus communication is complete. When the Master bus communication is complete, the IC clears this bit. Device initialization /configuration The ACT43750 provides multiple layers/steps to select its configuration and operation modes. At startup, the IC reads internal I2C registers and external component val- ues to configure its operation. After startup, users can change functionality by changing the internal register settings with standard I2C commands. Factory Programming Options / CMI I2C Regis- ters The ACT43750 contains several 8-bit registers that are preprogrammed at the factory. The default register val- ues are set at the factory. These default values are re- ferred to as the CMI (Code Matrix Index) , and they are stored in non-volatile memory (NVM). Each different CMI is referred to by a three-digit number which results in a unique orderable part number. The I 2C registers can be changed via the I 2C Slave bus. Refer to the ACT43750 Register Definition Application Note for more details about the available register settings. Ex- amples of functionality that can be changed via I 2C are below. Refer to the Register Map Application Note for more details.

Table 2. ACT43750 I2C Functions

© 202 Qorvo US, Inc. All rights reserved. Table 5. Register-wise RCONF[4:0] assignments, RCNFT & RCNFB and 7-bit I2C Slave Address Note 3: External Configuration resistors never override the reg11[3] bit, always factory code used. All the other registers are initialized only by the Factory Programming Options.

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 20 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator Figure 5 shows the ACT43750 detailed functional blocks. The ACT43750 provides the following three (3) major functions. 1. REGG: generates the negative gate voltage 2. DSW50: generates the RF PA drain voltage 3. IDRAIN Calibrator: calibrates the RF PA’s gate voltage to optimize the RF PA performance. To support these 3 blocks, the device integrates the following supporting function blocks.

Logic Interface o I2C Slave o I2C Master o I2C Bypass
Finite State Machine
Device Initialization / Configuration o External Configuration Resistors o Factory Programming Defaults o I2C Registers
Device Bias / Reference System o 5-V Bias Regulator o Floating 5-V Bias Regulator o Low-side Gate Drive Regulator o High-side Gate Drive Regulator o Switching Clock Generator o DACG
Protection Circuitry State Machine The ACT43750 integrates a state machine to control the overall IC behavior and operation. The following section describes each state. No Power The IC starts up in this state and remains there until the V12 input bias voltage goes above its UVLO, typically 10V. Bias Ramp When the V12 bias voltage goes above ULVO, the state machine moves to the Bias Ramp stage. In this state, the IC initializes and loads the default CMI values from NVM into working memory. It reads the voltage on CONF and loads the resulting value into register 0x11h. It reads bit 0x 11h [6] and decides to use the internal clock, which is set b y the RRT resistor, or synchronize with the external clock . It loads the REGG voltage ref- erence to set the default negative gate voltage. After these steps are complete and the bias voltages are ready, the IC moves to the Bias Ready state. Bias Ready In the Bias Read state, the IC waits for an input trigger to turn on the negative gate voltage, REGG. REGG Ramp When a REGG enable event is triggered, the device starts up the REGG negative gate drive voltage. REG50 Ramp When the REGG voltage is ready, the V PG pin goes open drain. This allows the IC to enable an external drain voltage regulator if available. This state is in- tended to enable the ACT43850 via I2C. It does this by automatically using the Master I 2C bus to write a 1 to the ACT43850 register 0x08 bit[0]. TX Ready When both the REGG and REG50 are ready, the IC en- ters this state and waits for a command to enter one of the following states: DSW50 ON, RSCAL CAL, REGG to MIN, and REGG Programming. DSW50 ON In this state, the drain FET is turned on, and the drain voltage is applied to the RF PA . Before the IC enters this state, it must have entered either the RSCAL CAL, REGG to MIN, or REGG Programming states. RSCAL CAL In this state, an autocalibration routine is performed to find the proper gate voltage to bias the RF PA at the desired drain current, Idq. REGG to MIN In this state, the REGG gate voltage slews to the mini- mum programmed value to turn off the RF PA. REGG Programming The IC enters this state when an I2C command changes the DACG register value. This value sets the REGG negative gate voltage to the RF PA. The gate voltage can only be changed when ENTX is low. That means the IC can only enter this state when the drain voltage is off. Error REGG MIN The IC enters this state when it detects an overcurrent or over-temperature on the RF PA. The device turns off the drain voltage and drives the REGG gate voltage to the minimum programmed voltage.

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 21 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator V50 Discharge The IC only enters this state when the system uses Qorvo’s ACT43850 to generate the RF PA drain voltage. When the IC receives a command to disable REGG, it moves to this state to activate the IDRAIN Calibrator block to discharge the drain supply voltage node before it dis- ables REGG. REGG Shutdown As a result of the REGG disable event, the IC drives the DACG toward 0 V (zero). This state does the opposite of the soft start. Bias Error When the IC detects an error, it immediately turns off REGG and turns off the external RF PA drain FET. The IC turns off the RFPA drain voltage and then turn s off the REGG gate voltage. It stays in this state until the 12V bias voltage at V12 is cycled off and back on. I2C is still active in this state. The following faults force the IC into this state: 5V Bias Regulator under-voltage V12 under-voltage V12 over-voltage Floating 5V Bias Regulator under-voltage Low-side Gate Drive Regulator under-voltage High-side Gate Drive Regulator under-voltage Thermal shutdown, TSD External Clock Synchronization error REGG under-voltage REGG over-current 5-bit ADC read error Operation Frequency Selection / RRT read error

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 23 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator PIN DESCRIPTIONS This section describes the ACT43750 pins and their functionality. V50 The V50 pin is the power input for the IC’s DSW50 block. It is also used as the positive input reference for both the RF PA overcurrent and calibration current inputs. V50 requires a 0.1uF ceramic capacitor to ground. PGND PGND is the ground pin for the DSW50 block. It must be directly connected to the exposed pad. PGND and AGND should be connected with a Kelvin connection to separate the power ground currents from the analog ground currents. AGND AGND is the analog ground reference for the internal ADC, voltage reference, DAC, etc. This “quiet” ground reference is kept separate from the higher current power grounds. AGND and PGND should be connected with a Kelvin connection to separate the analog ground currents from the power ground currents. XINT XINT is the open drain interrupt output pin. It should be connected to a pull-up resistor to a proper logic voltage source. V5 is the 5V internal bias voltage output pin. It requires a 2.2µF ceramic capacitor to AGND. V5 is not intended to power any external circuitry. SCL, SDA These are the IC’s I 2C clock and data pins. They have standard I 2C functionality. If I 2C is not needed, these pins should be tied to either ground or V5. See the Sys- tem Control section for the IC’s available slave ad- dresses. Note that SCL and SDA do not have internal pullup resistors. ENTX ENTX is a digital input that enables the transmit function in RF PA applications. When using the ENTX pin to en- able the DSW50 drain voltage to the RF PA, pull the ENTX pin high. Pull it low to disable the drain voltage. Note that even if ENTX is low, the drain voltage can still be enabled by I 2C. Refer to the DSW50 Enable Input Logic paragraph for the detailed conditions to enable and disable the drain voltage. ENTX is a digital input and must be actively terminated high or low. To ensure ENTX is low by default at turnon, connect a 100kΩ resistor from this pin to the ground. Don’t float this pin. The REGG block can only be enabled when ENTX is low. In other words, the RF PA REGG gate voltage can only be changed when ENTX is low. ENCAL ENCAL is a digital input that initiates the RF PA Idq cal- ibration routine. ENCAL is a digital input and must be actively terminated high or low. To ensure ENCAL is low by default at turnon, connect a 100kΩ resistor from this pin to ground. Don’t float this pin. SYNC SYNC is the synchronization pin. It operates as either a master sync output or a slave sync input. See Table 3 for details on programming the SYNC pin functionality. CONF CONF uses two resistors to configure additional IC functionality. RT RT uses a resistor to AGND to set the oscillator fre- quency. It is only functional when the CONF pin pro- grams the oscillator as a Master. REFIN External reference voltage input. An external reference can be used to provide a low noise reference voltage for the REGG block for the negative gate drive. Register 0x0F bit 6 must be set to 0 to use an external reference. NTC RF PA over temperature protection input. NTC typically uses a thermistor and a resistor to set the over-temper- ature threshold. It also accepts digital logic input from another IC. If not used, connect NTC to V5. ENG ENG is the enable pin for the REGG block. When using the ENG pin to enable the REGG block, pull ENG high enable REGG and pull the ENG pin low to disable the REGG block. Note that even if ENG is low, the REG G block can still be enabled by I 2C. Refer to the REGG Enable Input Logic paragraph for the detailed condi- tions to enable and disable the REGG block. Note that ENG must be low when bias power is applied to the IC. To ensure ENG is low by default at turnon , connect a 100kΩ resistor from this pin to the ground. Do not float this pin.

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 24 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator PG PG is an open drain power good output for the REGG block. It should be connected to a pull -up resistor to a proper logic voltage source. PG is pulled high when the REGG power is good. PG can also be connected to other devices’ power good outputs. It has an input mon- itor that detects if an external device pulls PG low. If PG is pulled low, the ACT43750 finite state machine is no longer in the power-good status, and it moves to the one of error states. GV5 GV5 is the REGG 5V reference voltage output. The GV5 output voltage is referenced to the VG output volt- age. GV5 requires a 2.2µF capacitor to VG. GREF GREF is the reference voltage for the REGG power supply. The GREF voltage is referenced to the VG out- put voltage. GREF requires a 100nF capacitor to VG. COMP COMP is the loop compensation capacitor input pin for the REGG power supply. The REGG power supply is designed to use a single capacitor value for all operat- ing conditions. COMP requires a 470pF capacitor to VG. VG VG is the REGG output voltage pin. This is the negative gate voltage output pin that connects directly to the RF PA gate. A 22uF capacitor is needed between this pin and PGND. GSW GSW is the REGG switching node. The GSW pin re- quires an LC filter connected between GSW and VG. The REGG inverting buck topology requires a 6.8µH in- ductor between GSW and PGND. It then requires a 22µF ceramic capacitor connected between PGND and VG. The capacitor must be connected directly between the inductor and the VG pin. V12 V12 is the external 12V bias supply input to the IC. Con- nect a 10µF ceramic capacitor between V12 and PGND. It also requires a 10nF ceramic capacitor between V12 and VG. LSR Low-side gate drive regulator. Connect a good quality 2.2µF or higher ceramic capacitor between this pin and the PGND pin. LSGU DSW50 pull-up output pin for the low-side gate. LSGD DSW50 pull-down input pin for the low-side gate. CPL High-side gate drive regulator flying capacitor terminal . Connect a good quality 47nF CCP capacitor and a 33Ω RCP resistor, in series, between this pin and the CPH pin. CPH High-side gate drive regulator flying capacitor terminal. Connect a good quality 47nF CCP capacitor and a 33Ω RCP resistor, in series, between this pin and the CPL pin. CALG IDRAIN calibrator external FET gate drive output. VD DSW50 output voltage node. Connect a good quality 10µF or higher capacitor CBT50 between this pin and the BT50 pin. BT50 High-side gate drive regulator output, bootstrap for the DSW50. Connect a good quality 10µF or higher capac- itor CBT50 between this and the VD pin. HSGD DSW50 pull-down input pin for the high-side gate. HSGU DSW50 pull-up output pin for the high-side gate. CSPA IDRAIN over current protection current -sense input pin. Connect a 3mΩ (TYP) sense resistor RSPA between the drain of high-side FET and the V50 pin. Connect an RC filter to this pin. Refer to the ACT43750 EVK for the val- ues and connection details. CSCAL IDRAIN calibration current-sense input pin. Connect a RSCAL sense resistor between the calibration FET drain and V50. Connect RC filter RCAL and CCAL to this pin. PGND Ground terminal for power blocks.

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 25 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator IC BIAS CIRCUITRY The ACT43750 supports both controlled positive and negative output voltage s. This requires multiple refer- ence voltage and ground references. V12 Bias Regulator The IC requires an external 12V bias input. This bias voltage is applied to the V12 pin, which requires at least a 10µF X5R or X7R ceramic capacitor, CV12, to AGND. The 12V bias voltage should be relatively clean with less than 100mV of ripple. This voltage powers the ICs and generates the other reference voltages and the negative gate voltage. 5V Bias Regulator An internal linear regulator provides a 5V bias at the V5 pin. This bias voltage directly powers most of the inter- nal circuitry. The 5V bias voltage should be relatively clean with less than 50mV of ripple. It requires a 2.2µF X5R or X7R ceramic capacitor, CV5, to AGND Floating 5V Bias Regulator Because the ACT43750 provides a negative gate volt- age, it needs a 5V bias that is referenced to the negative gate voltage, VG. The ACT43750 generates this float- ing 5V bias with a linear regulator output at the GV5 pin. This regulator biases all circuitry that is referenced to the VG voltage. It requires a 2.2µF X5R or X7R ceramic capacitor, CGV5, to the VG pin. Low-side Gate Drive Regulator The ACT43750 provides a linear regulator to power the low-side gate driver at the LSR pin. This allows the user to optimize the gate drive voltage for the specific FETs used in the design. Note that the voltage on LSR is used for both the low-side and high-side FETs. The VoLSR[3:0] bits in r egister 0x0Fh [3:0] set the default gate drive voltage. The default LDO voltage is set at the factory. This voltage cannot be changed on the fly. Con- tact Qorvo if a different default voltage is needed. The low-side gate drive regulator requires a 2.2µF ceramic capacitor to PGND. High-side Gate Drive Regulator Note that the high-side FET gate voltage is the same as the low-side FET. The ACT43750 provides a charge - pump regulator to power the high-side gate driver at the BT50 pin. This charge pump transfers the LSR voltage, referenced to PGND, to the CBT50 capacitor, refer- enced to VD, the drain voltage. The high side gate drive regulator requires a 47nF capacitor (CCP) in series with a 33ohm resistor (RCP) between the CPL and CPH pins. The charge pump resistor R CP power dissipation is a function of drain voltage, frequency, and capacitance. Use the following equation to c alculate the RCP power dissipation. Where: P – power loss of charge pump resistor, unit Watt. C – charge capacitance, the unit is F. F – drain voltage switching frequency, the unit is Hz. V – drain voltage, the unit is Volt. The RCP resistor power rating should be higher than power loss and have at least a 50% margin. PMIC OPERATION The following sections describe the available ACT43750 functionality. The detailed functional dia- gram is shown in Figure 5. DSW50 Drain Voltage The DSW50 block provides drain switch control for RF PA GaN FETs. It does this by driving two separate FETs to apply the drain voltage to the RF PA and remove the drain voltage from the RF PA. This block supports both enhanced-mode power GaN and traditional Si (silicon) power FETs. High-Side Driver: The high-side FET driver has two separate output pins that provide a push -pull output to drive the drain FET. The HSGU pin turns the drain FET on by applying a floating voltage to the FET gate refer- enced to the VD pin's drain voltage . The HSGD pin turns the drain FET off by pulling the gate to the VD voltage. Low-Side Driver: The low-side FET driver also has two separate output pins that provide a push -pull output to drive the bottom FET. The LSGU pin turns the bottom FET on by applying the gate voltage to the FET gate . This voltage is ground-referenced. The LSGD pin turns the bottom FET off by pulling the gate to the ground.

© 202 Qorvo US, Inc. All rights reserved. able DSW50 by applying a logic low to ENTX. two bits always returns a 0. before the IC enters the DSW50 ON state. pin voltage is logic L, the power is not good. Figure 7. Power Good Logic acts accordingly as if the ACT43750 had pulled PG low. panion chip to provide system-level fault tolerance.

DACG: 13-bit DAC with output voltage from 0.75 V to 3.00 V. Note that the resulting gate voltage is scaled to -2x the DACG voltage.
External reference input at the REFIN pin . The user can supply an external reference voltage to replace the internal DAC reference voltage.
DACG Digital Servo that controls the gate voltage slew rate when changing from one voltage to another.
Soft-start control by adjusting charge current to capac- itor CGREF.
Reference voltage noise reduction circuits to minimize noise applied to the RF PA gate. DACG The ACT43750 provides multiple methods of program- ming the 13 -bit DAC between 0.75 V to 3.00 V. The DACG block contains several registers that set the DACG voltage. The actual DAC output voltage is set by the 13 bits in registers 0x07h [7:0] and 0x06h [4:0]. Reg- ister 0x07h contains the upper 8 msb and register 0x06h[4:0] contains the lower 5 msb. These two regis- ters are combined to create a 13-bit register, DACG. The DAC G register sets the DACG output voltage, which can be programmed between 0. 75V and 3.0V in 366.2µV steps. Setting DACG below 0.75V is not al- lowed. DACG Voltage = DACG * 366.2µV Where DACG is the decimal equivalent of the 13 bits in the hex-based register. Table 6 shows several example DACG register values converted to the DACG voltage and the resulting gate drive voltage. Note that the re- sulting gate drive voltage is -2 times the DACG voltage. DACGMIN and DACGMAX are 8-bit registers that pro- gram the minimum and maximum DACG clamp voltage. These two registers define the starting and stopping points in the autocalibration routine and provide safety clamps to place known limits on the RF PA gate voltage. DACGMIN is in register 0x14h and DACGMAX is in reg- ister 0x15h. These registers correspond to the 8 most significant bits of DACG.

Table 6. DACG Register Values There are multiple ways to program the DACG bits.

At startup, the State Machine automatically loads the
When the autocalibration routine is run, the algorithm
The user can directly set the DACG value via the I2C
The user can use I 2C to write a DACG Adjust value

isting value in the DACG registers.

Use the I2C Master and Delta-Calibration to follow an

external I2C memory bank to set the DACG value. and DACGMAX register values. times based on these two register settings. Table 7. DACG Digital Servo Step Times ister 0x04h[0]. This does not require user intervention.

GREFSel bit in Register 0x0Fh [6] = 0
The external reference voltage at the VREFIN

is between VREFIN(MIN) and VREFIN(MAX) range. the 13-bit DACG register. VREFIN(MAX) = 3.0V. necting a bypass capacitor , CGREF, to the GREF pin.

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 29 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator REGG Enable Input Logic external The ACT43750 provides two methods to turn the REGG block ON and OFF. Hardware Enable Pin. Enable the REGG block by ap- plying a logic H to the ENG pin (enable gate). Disable REGG by applying a logic low to ENG. I2C Slave Bus. Enable the REGG block by w riting a 1 into the EN_REGG bit in register 0x08h [7]. Disable REGG by writing a 1 into the DIS_REGG bit in register 0x08h [6]. Note that the EN_REGG and DIS_REGG bits are auto- matically cleared after the I2C write. Reading these two bits always returns a 0. The IC uses the logic OR of the ENG pin and the I 2C registers to enable the IC. Pulling the ENG pin high or writing 1 to EN_REGG enables the REGG block. Pull- ing the ENG pin low disables the REGG block. Writing a 1 into DIS_REGG disable s the REGG block , even if ENG is high. REGG Soft start The REGG soft start is controlled by the CGREF capacitor on the GREF pin by applying a constant current output to this capacitor at startup. The soft start time can be increased or decreased by adjusting the C GREF capaci- tor value or by adjusting the constant current output. The constant current output is controlled to 5µA, 10µA, 100µA, or 200µA by the IchgGREF bits in register 0x0Eh. Reducing the soft start time requires higher out- put current and a higher peak current in the gate drive supply inductor. Qorvo recommends keeping the gate current below 500mA during softstart. Idq Bias Point Calibration The ACT43750 provides a calibration routine that cali- brates the proper RF PA gate voltage bias point. The calibration routine operates in the RSCAL State. The typical RF PA datasheet provides an Idq value that de- fines the proper drain current with no RF applied. This drain current is achieved by properly controlling the RF PA gate voltage. The ACT43750 autocalibration routine sweeps the negative gate voltage while measuring Idq. When the RF PA sinks the proper Idq, the IC saves the resulting gate voltage in registers 0x06h and 0x07h and uses that value to bias the RF PA. The bias point calibration routine utilizes a dedicated FET and current sense resistor that is sized for the re- quired Idq current. When the routine is enabled, the IC turns off the main drain FET, TRHS. The actual autocali- bration routine depends on the previous state of the system. The following equation calculates the correct calibration resistor value to bias the RF PA to the cor- rect Idq. 𝑅𝑠𝑐𝑎𝑙 = 1.5𝑉 𝐼𝑑𝑞 (2) Where: Idq – RFPA dc bias current, unit A Rscal- Calibration resistor, unit Ω Initial Calibration Routine. For the first calibration rou- tine after power up, the IC sets the DACG voltage to the value defined by DACG MAX, which sets the gate volt- age, VG, to the farthest negative value. This ensures that the RF PA is in pinch-off when the drain voltage is applied. At this time, no current flows through the FET or current sense resistor. It then turns on the smaller calibration FET, TRSMALL, and starts sweeping the DACG voltage lower, which makes the V G gate voltage go higher (more positive). Note that gate voltage is nega- tive two times the DAC voltage. This starts increasing the Idq to the desired setpoint. The IC decreases DACG voltage one step at a time with the delay time between steps set by the DACG Servo settings. When the cor- rect Idq current is reached, the REGG voltage is held constant and the corresponding DACG value is saved in registers 0x06h and 0 x07h. The IC automatically moves to the TX Ready State. The ACT43750 measures the Idq current by sensing the voltage across the current sense calibration resistor, RSCAL. It compares this voltage to a 1.5V internal refer- ence threshold, VIT+(CSCAL). Note that the current sense voltage is measured between the V50 and CSCAL pins. Qorvo recommends connecting a 20kΩ Rcal resistor between CSCAL and the T RSMALL FET. Connect a 100nF filter capacitor across RSCAL and the filter capac- itor as shown in Figure 8. The calibration routine can be started by either applying a logic H to the ENCAL pin or by writing a 1 into the RunCal bit in register 0x08h [3]. The RunCal bit is auto- matically cleared back to a 0 when the calibration rou- tine starts. The typical auto calibration time is approxi- mately 30ms. This can be increased or decreased by changing the starting gate voltage and by adjusting DAC servo speed control. The actual calibration time depends on the bias voltage starting point and the DACG digital servo speed control. Register 0x10h pro- grams DACG voltage transition time, which will make the calibration time shorter or longer.

© 202 Qorvo US, Inc. All rights reserved. Figure 8. RC filter for Calibration Current Sense same procedure as when starting the initial calibration. moves to the REGG shutdown state, setting VG = 0V. clamp values and can turn off the gate voltage. 1.5V nominal value in 1% increments. quencer must send a command to register 0x97h bit 5. brate Idq without having to turn on the calibration FET. itive or negative sign bit is stored in register 0x96h bit 0. digitizing errors, so the actual IQ(DRAIN) may off the target. tion routing to correlate the IQ(DRAIN) and VG values. and disable this auto-re-calibration function. bits are read and the fault is cleared. When the XINT pin is logic H, there are no interrupts.

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 31 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator I2C Master The ACT43750 operates as a master on the SDA50 and SCL50 pins. These pins connect to companion devices like the ACT43850 and to an external EEPROM. The ACT43750 operates as a master to read from and write to the registers in these slave devices. I2C Broadcasting Address The ACT43750 supports an I2C slave broadcasting ad- dress of 0x20h. This becomes 0x41h when writing to the ACT43750 ICs. This allows the I2C master con- nected to the SCL and SDA pins to configure and con- trol multiple ACT43750 ICs simultaneously. Only use this broadcasting address for "write" com- mands. Any "read" command should be issued to an individual I2C address. I2C Master Interface to a Host I2C registers at 0x90h to 0x9Fh control the I 2C Master functions (below). Scans to check for any companion devices on this sub- I2C bus like the ACT43850 or an external EEPROM.

Enables and disables the ACT43850.
Provides bypass control from a system -host to the ACT43850.
(Re-)Programs the drain rail target voltage at the ACT43850.
Reads target drain voltage from the external I2C memory.
Reads target drain bias current from the exter- nal I2C memory.
Reads target gate voltage from the external I2C memory. The system host can turn the I2C master bus on and off by writing into register bit 0x17h [1]. When 0x17h [1] = 0, the master function is enabled. When 0x17h [1] = 1, the master function is disabled. Also, the host can change the I2C master clock speed using 0x17h [3:2]. Scanning for Companion Devices The IC automatically scans the master I2C bus for com- panion devices when the IC enters the REG50 Ramp state. The IC only supports two external components on this bus, one ACT43850 and one external EEPROM. If a device is found, the ACT43750 sets register 0x99h [0] = 1 to indicate there’s an ACT43850 device on the sub- I2C bus and its I2C address gets stored in 0x98h [7:1]. If an external EEPROM is found, the IC sets bit 0x99h [1] = 1. I2C Bypass The ACT43750 provides an I 2C bridge logic between the I2C Slave and the I 2C Master blocks. The system host can enable the bypass function by setting 0x17h [0] = 1. Wh en in bypass mode, th e ACT43750 will pass - through commands from the system host at (SDA, SCL) port, to the ACT43850 on the SDA50/SCL50 pins. It also transfers responses back to the main SCL/SDA I2C bus. Note that when the ACT43750 executes its own auto- matic communication procedures on the I 2C Master block, the flag bit 0x99h [2] indicates the master block is busy and the system host needs to wait until this flag bit is cleared.

© 202 Qorvo US, Inc. All rights reserved. equation (3). Table 8 provides some example values. Table 8. Resistor value vs. Switching Frequency and operates in stand-alone operation. spread spectrum, and the output clock is fixed / steady. quency, and repeats the dithering every 64 cycles. chronizes to an external clock input at the SYNC pin. ±20% from the target switching frequency set by RT . choose one of the seven RT values in Table 8.

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 33 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator PROTECTION The ACT43750 IC provides extensive IC and system- level protection mechanisms. Startup Sequencing GaN RF PAs require very specific startup and shutdown sequencing. The ACT43750 provides the required se- quencing between the DSW50 and VG voltages. Be- cause GaN RF PAs are depletion mode devices, at turn on, the negative gate voltage must be applied before the drain voltage is applied. The gate is pulled low (the lowest negative voltage) to put the GaN FET in pinch- off before the drain voltage is applied. After the drain voltage is applied, the gate voltage is slewed positively to properly bias the GaN FET. A t turn-off, the gate is pulled to the most negative voltage again to put the GaN FET back into pinch-off. Any fault conditions move the IC to the Bias Error state. IDRAIN Over Current Protection The IDRAIN Over Current Protection block is an over-cur- rent protection of RF PA drain. By utilizing a small val- ued current sense resistor RSPA, the DSW50 block pro- tects the system from over -current conditions. This over-current protection is optimized to be fast acting to shut down the power supply to the RF PA devices. This protection is activated when the ENTX input is a logic H. PA Over Temperature Protection The PA Over Temperature Protection block is an over - temperature protection of RF PA. The device monitors the NTC pin voltage for over -temperature conditions. When V NTC goes below the V IT-(NTC) target, the device shuts down the power supply to the RF PA. The VIT-(NTC) threshold is 30% of the voltage at the V5 pin. The input circuit block at the NTC is designed to accept regular logic signals too. When using a logic signal for the over- temperature input to NTC, a logic L indicates an over- temperature. Thermal Warning (TWARN) and Shutdown - TSD The IC provides an internal temperature sensor that monitors the IC’s internal junction temperature, T J. When TJ exceeds the TWARN threshold, typically 140 deg C, 0x02h [0] = 1. When TJ exceeds the T SD threshold, typically 160 deg C, the IC detects a thermal fault and shuts down the DSW50 block. The drain voltage for the RF PA is turned off and the IC moves into the Bias Error state and sets 0x02h [1] = 1. After shutting down, the IC can restart when TJ drops below 145 deg C. OVLO The IC provides overvoltage protection on both the V50 and V12 input voltages. If V50 or V12 exceed 65V or 14V respectively, the IC locks out, registers an overvolt- age condition, and moves to the Error Bias state. UVLO The IC provides undervoltage protection on both the V50 and V12 input voltages. If V50 or V12 is under 10V, the IC locks out, registers an Undervoltage condition, and moves to the Error Bias state. VG OVP The IC provides overvoltage protection for the VG out- put. If VG exceeds 106.5% of the setpoint, the IC shuts down, registers an OVP fault , and moves to the Error Bias state. VG UVP The IC provides undervoltage protection for the VG out- put. If VG drops below 91% of the setpoint, the IC shuts down, registers a UVP fault , and moves to the Error Bias state. OCP – Gate Current The IC provides overcurrent protection on the VG out- put. If the gate current exceeds 1A, the IC shuts down, registers an OCP fault , and moves to the Error Bias state. OCP – Drain Current The IC provides overcurrent protection for the RF PA Drain current by monitoring the voltage across the cur- rent sense resistor connected to the drain side of the drain FET. OCP monitors the voltage difference be- tween the V50 and CSPA pins. Use a Kelvin connection across the sense resistor to ensure an accurate meas- urement. The overcurrent threshold voltage is 35mV. The current sense resistor can be adjusted to configure any desired overcurrent setting. If the measured current exceeds the fault threshold, the IC shuts down, regis- ters an OCP fault, and moves to the Error Bias state. The following equation calculates the correct overcur- rent resistor value for the desired overcurrent threshold. 𝑅𝑆𝑃𝐴 = 35𝑚𝑉 𝐼𝐷 (4) Where: ID - RFPA drain current, unit A RSPA – Current limit sense resistor, unit mΩ Bias Error State As a reminder, when the IC enters the Bias Error State, it turns off all blocks and waits for the user to cy- cle V12 off and back on to clear the faults.

APPLICATION INFORMATION

The CV12 capacitor is connected between the V12 and AGND pins. This capacitor must be at least 10µF and should be a high-quality ceramic capacitor like X7R. CV5 The C V5 capacitor is connected between the V5 and AGND pins. This capacitor must be at least 2.2µF and should be a high-quality ceramic capacitor like X7R. CGV5 The CGV5 capacitor is connected between the GV5 and VG pins. This capacitor must be at least 2.2µF and should be a high-quality ceramic capacitor like X7R. CG12 The CG12 capacitor is connected between the V 12 and VG pins. This capacitor must be at least 10nF and should be a high-quality ceramic capacitor like X7R. Bootstrap Capacitor CBT50 The CBT50 capacitor is connected between the BT50 and VD pins . This capacitor must be at least 10µF and should be a high-quality ceramic capacitor like X7R. Configuration Resistors RCNFT and RCNFB. The RCNFT and RCNFB form a voltage bias network be- tween the V5 and AGND pins . Its center tap is con- nected to the CONF pin. See External Configuration Resistors in Table 5 for the detail s on how to choose these resistors. RRT The R RT resistor is connected between the R T and AGND pins. See the Internal Clock Oscillator section for the details. Pull-up Resistors RSCL RSCL is a pull-up resistor of an I2C slave clock port. Con- nect this pull-up resistor at the SCL pin to a proper logic interface voltage source. RSDA RSDA is a pull-up resistor of an I2C slave data bus. Con- nect this pull-up resistor to the SDA pin to a proper logic interface voltage source. RPG RPG is a pull -up resistor for the power-good indicator , PG. Co nnect this pull -up resistor to the PG pin to a proper logic interface voltage source. RXINT RXINT is a pull-up resistor for the interrupt indicator. Con- nect this pull-up resistor to the XINT pin to a proper logic interface voltage source. REGG Output Filter L1 is the inductor for the gate drive inverting buck con- verter’s LC filter. Connect a good quality 6.8µH inductor between the GSW and PGND pins . The inductor satu- ration current should be more than the IC current limit setting. The following equations (5 – 7) can calculate the induc- tor saturation current: The inductor ripple current: 𝛥𝐼 = (𝑉12−𝑉𝐺)∗𝑇𝑜𝑛 𝐿1 (5) Where: ΔI – Inductor ripple current (A) L1 – Output inductance (H) V12 – 12V bias voltage (V) VG – Gate voltage (V) fsw – Switching Frequency of REGG (Hz) Ton – On time (s) 𝑇𝑜𝑛 = 𝑉𝐺 ∗ −1 𝑉12−𝑉𝐺 ∗ 𝑓𝑠𝑤 (6) 𝐼𝑝𝑒𝑎𝑘 = 𝛥𝐼 + 𝐼𝐺 (7) IG – Output current of the gate (A) Choose an inductor with a saturation current higher than the Ipeak calculation above. Also take the induc- tor’s RMS rating into account. CGATE CGATE is the capacitor for the gate drive inverting buck - boost converter’s LC filter. Connect a good quality 22µF capacitor between the VG and PGND pins. This capac- itor must be a high-quality ceramic capacitor like X7R.

The ENTX, ENCAL, and ENG digital input sig-
The RT, NTC, and CONF resistors must be
Apply the V12 bias voltage and the V50 drain

voltage. These can be applied in any order.

Enable the gate voltage by driving the ENG pin

tive value as defined by register 15.

Momentarily drive the ENCAL pin high to initi-

tions on the RF PA drain capacitance.

For systems with drain switching, drive the
If a calibration routine is needed at any time

tion routing by toggling the ENCAL pin high. The typical turnoff procedure is outlined below.

Turn off the drain switch by pulling the ENTX

clicking Disable Vdrain in GUI.

Adjust the gate voltage to the minimum pro-
Power off the drain power supply.
After the drain voltage decays to less than 10V,

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 37 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator TYPICAL OPERATIONAL CHRACTERISTICS 2V / div 10ms / div Gate Voltage Start Up VGSW Vgate 10V / div 5V / div VENG 2V / div 2ms / div Gate Voltage Shut Down VGSW Vgate 10V / div 5V / div VENG 20mV / div 400ns / div Gate Ripple Voltage w/no Load VGSW Vgate 10V / div 20mV / div 400ns / div Gate Ripple Voltage w/300mA Load VGSW Vgate 10V / div 2V / div 80us / div Transmit w/Resistive Load ENTX Vgate 5V / div 5A / divIdrain Vdrain 20V / div 2V / div 20ns / div Transmit w/Rising Edge ENTX Vgate 5V / div 5A / divIdrain Vdrain 20V / div

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 38 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator 2V / div 20ns / div Transmit w/falling edge ENTX Vgat e 5V / div 5A / divIdrain Vdrain 20V / div 20V / div 80us / div Transmit w/Hgate, Lgate ENTX VHgate 5V / div 5V / divVLgate Vdrain 20V / div 20V / div 20ns / div Transmit w/Rising Hgate, Lgate Edge ENTX VHgate 5V / div 5V / divVLgat e Vdrain 20V / div 20V / div 40ns / div Transmit w/Falling Hgate, Lgate Edge ENTX VHgat e 5V / div 5V / div VLgat e Vdrain 20V / div 1V / div 10ms / div QPD1004 Initial Calibration ENCAL Vgate 5V / div 50mA / divIdrain Vdrain 20V / div 1V / div 2ms / div QPD1004 Initial Calibration (zoomed) ENCAL Vgate 5V / div 50mA / div Idrain Vdrain 20V / divIdq=50mA

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 39 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator 1V / div 10ms / div QPD1028 Calibration Vgate 500mA / div Idrain Vdrain 20V / div ENCAL 5V / div 1V / div 2ms / div QPD1028 Calibration (zoomed) Vgate 500mA / divIdrain Vdrain 20V / div ENCAL 5V / div Idq=750mA 1V / div 10ms / div Calibration Failure ENCAL Vgate 5V / div 50mA / divIdrain Vdrain 20V / div 2V / div 10ms / div Power Down - Remove Bias Vbias Vgate 10V / div 20V / div Vdrain 20V / div 200ms / div Power Down - Remove Input Voltage Vinput Vgate 20V / div 5V / divVdrain PG 5V / div 20V / div 10ms / div Power Down - Remove Input Voltage (Zoomed) Vinput Vgat e 20V / div 5V / div Vdrain PG 5V / div

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 40 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator 5V / div 10us / div OCP w/PG (I_limit=11A) PG VG 5V / div 20V / divVdrain Idrain 5A / div 5V / div 10us / div OCP w/XINT (I_limit=11A) XINT VG 5V / div 20V / divVdrain Idrain 5A / div 10V / div 400ns / div Sync w/Ext Signal Falling Edge VG Vgsw 5V / div 5V / divSync 10V / div 400ns / div Sync Out Clock VG Vgsw 5V / div 5V / divSync

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 41 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator PACKAGE OUTLINE AND DIMENSIONS PART MARKING

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 42 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator Handling Precautions [1] Refer to the chapter "10 Recommendations for a New ESD Target Level" in the JEDEC document Recommended ESD Target Level for HBM Qualification (JEP155B) [2] Refer to the chapter "9 Recommendations for Realistic CDM Target Levels for the Present and an Outlook for the Future" in the JEDEC document Recommended ESD-CDM Target Levels (JEP157) Solderability Compatible with both lead-free (260 °C max. reflow temperature) and tin/lead (245 °C max. reflow temperature) soldering processes.

Data Sheet Rev. F, February 10, 2025 | Subject to change without notice 43 of 43 www.qorvo.com © 202 Qorvo US, Inc. All rights reserved. ACT43750 RF POL Drain-Switch Driver / Gate-bias Regulator Product Compliance This part complies with RoHS directive 2011/65/EU as amended by (EU) 2015/863. This part also has the following attributes:

Lead Free
Halogen Free (Chlorine, Bromine)
SVHC Free
PFOS Free
Antimony Free
TBBP-A (C15H12Br402) Free Contact Information For the latest specifications, additional product information, worldwide sales and distribution locations: Web: www.qorvo.com Tel: 1-844-890-8163 Email: customer.support@qorvo.com For technical questions and application information: Email: appsupport@qorvo.com Important Notice The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained herein and assumes no responsibility or liability whatsoever for the use of the information contained herein. All information contained herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for Qorvo products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED HEREIN, AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PERFORMANCE, USAGE OF TRADE OR OTHERWISE, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical componen ts in medical, life-saving, or life -sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death. Copyright 2023 © Qorvo, Inc. | Qorvo®, Active-Semi®, Power Application Controller®, Solutions for Sustainability™, Micro Application Controller™, Multi -Mode Power Manager ™, Configurable Analog Front End ™ and Application Specific Power Drivers ™ are trademarks of Qorvo, Inc. ARM® is a registered trademark and Cortex™ is a trademark of ARM Limited. All referenced brands and trademarks are the property of their respective owners. Pb

Product Information

ACT43750 specifications and overview.

Summary

RF POL Drain-Switch Driver / Gate-bias Regulator Rev. F, February 10, 2025

Description

RF POL Drain-Switch Driver / Gate-bias Regulator Rev. F, February 10, 2025

Source title ACT43750 Datasheet(PDF) - Qorvo, Inc

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