PCI9080 PLX | Alldatasheet
Document overview
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Technical content
Features
n PCI Version 2.1 compliant Bus Master interface chip for adapters and embedded systems n Programmable local bus supports nonmultiplexed 32-bit address/data, multi- plexed 32- or 16-bit, and accesses of 32-, 16-, or 8-bit local bus devices n I2O compatible messaging unit n 3.3 or 5 volt PCI signaling, 5 volt core, low-power CMOS in 208-pin PQFP n Two independent program- mable DMA channels for local bus memory to/from PCI host bus data transfers n Eight programmable FIFOs for zero wait state burst operation n PCI to/from local data transfers up to 133MB/sec n Local bus runs asynchro- nously to the PCI bus n Eight 32-bit mailbox and two 32-bit doorbell registers n Performs Big Endian/Little Endian conversion n Upward compatibility with PCI 9060, 9060ES, 9060SD
T E C H N O L O G Y ® PLX Technology, Inc. 390 Potrero Ave. Sunnyvale, CA 94086 USA Tel: 1-800-759-3735 Fax: 1-408-774-2169 Email: info@plxtech.com Web Site: www.plxtech.com PFQP nip-802egakcaP 1.2 .v ,noitacificeps sub lacol ICPecnailpmoc ICP I2O messaging unit PCI extension of the I2O speci/f_ication v.1.5 Interface protocol Direct bus master v5 ro v3.3gnilangis ICP Local bus speed 0-40MHz Big/Little Endian conversion Dynamic switching for direct slave, direct master, DMA, and the internal register accesses on the local side xam zHM33deepS suB ICP PCI host capability Type 0 or Type 1 PCI con/f_iguration cycles in direct master mode Mailbox registers Eight 32-bit, accessed from PCI or local bus Doorbell registers Two 32-bit, one from PCI to local bus, one from local bus to PCI bus Unaligned DMA transfer support From any byte boundary Programmable local bus modes Selected through mode pins Mode C 32-bit address/32-bit data, non multiplexed Mode J 32-bit address/32-bit data, multiplexed Mode S 32-bit address/16-bit data, non multiplexed Serial EEPROM interface Supported T echnical Spe ci /f_ic a t i o ns Dir. Master Write FIFOs Dir. Master Read Dir. Slave Write Dir. Slave Read DMA1 PCI/Loc DMA1 Loc/PCI DMA0 PCI/Loc DMA0 Loc/PCI PCI Initiator (For Direct Master Xfers) PCI Bus State Machines PCI Target (for Direct Slave Xfers) PCI Initiator (For Ch 1 DMA Xfers) PCI Initiator (For Ch 0 DMA Xfers) EEPROM Initialization Internal Registers PCI Con/f_ig Local Con/f_ig Run-Time DMA I2O Messaging Local Slave (for Direct Master Xfers) Local Bus State Machines Local Master (for Direct Master Xfers) Local Master (for Ch 1 DMA Xfers) Local Master (for Ch 0 DMA Xfers) Local Bus Interface – Select Bus Width 8,16 or 32 bit – Endian Conversion – Select Muxe or non-Muxe Addr/Data PCI Bus Interface & Arbiter Control Logic PCI Bus Local Bus I20 Messaging DMA DMA Chaining Unaligned Xfer PCI 9080 Internal Block Diagram Pr o duc t Or d e rin g I n f o r m a tion pihC retsaM suB lacoL ot ICP0809 ICP I2 IKDS O 2O Software Development Kit for Motorola MPC860 CPU, Intel i960 CPU, IBM PPC 401 CPU ,UPC 068CPM alorotoM rof tiK tnempoleveD erawtfoS ICPKDS ICP Intel i960 CPU, IBM PPC 401 CPU *See PLX web site for latest version and product support information © 1998 by PLX Technology, Inc. All rights reserved. PLX and PLXMon 98 are trademarks of PLX Technology, Inc. which may be regis tered in some jurisdictions. All other product names that appear in this material are for identi/f_ication purposes only and are acknowledged to be trademarks or regist ered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX Technology reserves the right, without notice, to make changes in product design or speci/f_ication. 9080-PB-010 9/98 5K