PEX8696 PLX | Alldatasheet

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Technical content

9 Read Pacing (bandwidth throttling)

9 Multicast

9 Dynamic Buffer/FC Credit Pool

9 Per Port Performance Monitoring

9 SerDes Eye Capture

9 Error Injection and Loopback

well suited for fan-out, aggregation, and peer-to-peer applications. enabling the user to achieve even higher throughput. throughout the internal data paths as packets pass through the switch. Figure 1. Common Port Configurations

PEX 8696, PCI Express Gen 2 Switch, 96 Lanes, 24 Ports performancePAKTM Exclusive to PLX, performancePAK is a suite of unique and innovative performance features which allows PLX’s Gen 2 switches to be the highest performing Gen 2 switches in the market today. The performancePAK features consists of the Read Pacing, Multicast, and Dynamic Buffer Pool. Read Pacing The Read Pacing feature allows users to throttle the amount of read requests being made by downstream devices. When a downstream device requests several long reads back-to-back, the Root Complex gets tied up in serving that downstream port. If that port has a narrow link and is therefore slow in receiving these read packets from the Root Complex, then other downstream ports may become starved – thus, impacting performance. The Read Pacing feature enhances performances by allowing for the adequate servicing of all downstream devices. Multicast The Multicast feature enables the copying of data (packets) from one ingress port to multiple (up to 23) egress ports in one transaction allowing for higher performance in dual-graphics, storage, security, and redundant applications, among others. Multicast relieves the CPU from having to conduct multiple redundant transactions, resulting in higher system performance. Dynamic Buffer Pool The PEX 8696 employs a dynamic buffer pool for Flow Control (FC) management. As opposed to a static buffer scheme which assigns fixed, static buffers to each port, PLX’s dynamic buffer allocation scheme utilizes a common pool of FC Credits which are shared by other ports. This shared buffer pool is fully programmable by the user, so FC credits can be allocated among the ports as needed. Not only does this prevent wasted buffers and inappropriate buffer assignments, any unallocated buffers remain in the common buffer pool and can then be used for faster FC credit updates. visionPAKTM Another PLX exclusive, visionPAK is a debug diagnostics suite of integrated hardware and software instruments that users can use to help bring their systems to market faster. visionPAK features consist of Performance Monitoring, SerDes Eye Capture, Error Injection, SerDes Loopback, and more. Performance Monitoring The PEX 8696’s real time performance monitoring allows users to literally “see” ingress and egress performance on each port as traffic passes through the switch using PLX’s Software Development Kit (SDK). The monitoring is completely passive and therefore has no affect on overall system performance. Internal counters provide extensive granularity down to traffic & packet type and even allows for the filtering of traffic (i.e. count only Memory Writes). SerDes Eye Capture Users can evaluate their system’s signal integrity at the physical layer using the PEX 8696’s SerDes Eye Capture feature. Using PLX’s SDK, users can view the receiver eye of any lane on the switch. Users can then modify SerDes settings and see the impact on the receiver eye. Figure 5 shows a screenshot of the SerDes Eye Capture feature in the SDK. Figure 5. SerDes Eye Capture Recovered Data Loopback modes.

Applications

Suitable for host-centric as well as peer-to-peer traffic patterns, the PEX 8696 can be configured for a wide variety of form factors and applications. Host Centric Fan-out The PEX 8696, with its symmetric or asymmetric lane configuration capability, allows user-specific tuning to a © PLX Technology, www.plxtech.com Page 3 of 3 5/14/2009, Version 1.1

or Message Signaled Interrupts (MSI) when enabled. and advanced error reporting. Figure 10. PEX8696-16U8D BB RDK

8696 RDK provides everything that a user needs to get

their hardware and software development started. hardware- and software-development kits. product design or specification.