PEX8664 PLX | Alldatasheet
Document overview
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Technical content
Features
PEX 8664 General Features o 64-lane, 16-port PCIe Gen2 switch - Integrated 5.0 GT/s SerDes o 35 x 35mm2, 1156-ball FCBGA package o Typical Power: 7.9 Watts PEX 8664 Key Features o Standards Compliant - PCI Express Base Specification, r2.0 (backwards compatible w/ PCIe r1.0a/1.1) - PCI Power Management Spec, r1.2 - Microsoft Vista Compliant - Supports Access Control Services - Dynamic link-width control - Dynamic SerDes speed control o High Performance ♦ performancePAK
9 Read Pacing (bandwidth throttling)
9 Multicast
9 Dynamic Buffer/FC Credit Pool
- Non-blocking switch fabric - Full line rate on all ports - Packet Cut-Thru with 176ns max packet latency (x16 to x16) - 2KB Max Payload Size o Flexible Configuration - Ports configurable as x1, x2, x4, x8, x16 - Registers configurable with strapping pins, EEPROM, I2C, or host software - Lane and polarity reversal - Compatible with PCIe 1.0a PM o Multi-Host & Fail-Over Support - Configurable Non-Transparent (NT) port - Failover with NT port - Up to Five upstream/Host ports with 1+1 or N+1 failover to other upstream ports o Quality of Service (QoS) - Eight traffic classes per port - Weighted round-robin source port arbitration o Reliability, Availability, Serviceability ♦ visionPAK
9 Per Port Performance Monitoring
Per port payload & header counters
9 SerDes Eye Capture
9 Error Injection and Loopback
- 4 Hot Plug Ports with native HP Signals - All ports hot plug capable thru I (Hot Plug Controller on every port) - ECRC and Poison bit support - Data Path parity - Memory (RAM) Error Correction - INTA# and FATAL_ERR# signals - Advanced Error Reporting - Port Status bits and GPIO available - Per port error diagnostics - JTAG AC/DC boundary scan The ExpressLaneTM PEX 8664 device offers Multi-Host PCI Express switching capability enabling users to connect multiple hosts to their respective endpoints via scalable, high bandwidth, non-blocking interconnection to a wide variety of applications including servers, storage systems, and communications platforms. The PEX 8664 is well suited for fan-out, aggregation, and peer-to-peer applications. Multi-Host Architecture The PEX 8664 employs an enhanced version of PLX’s field tested PEX 8648 PCIe switch architecture, which allows users to configure the device in legacy single-host mode or multi-host mode with up to five host ports capable of 1+1 (one active & one backup) or N+1 (N active & one backup) host failover. This powerful architectural enhancement enables users to build PCIe based systems to support high-availability, failover, redundant and clustered systems. High Performance & Low Packet Latency The PEX 8664 architecture supports packet cut-thru with a maximum latency of 176ns (x16 to x16). This, combined with large packet memory, flexible common buffer/FC credit pool and non-blocking internal switch architecture, provides full line rate on all ports for performance-hungry applications such as servers and switch fabrics. The low latency enables applications to achieve high throughput and performance. In addition to low latency, the device supports a packet payload size of up to 2048 bytes, enabling the user to achieve even higher throughput. Data Integrity The PEX 8664 provides end-to-end CRC (ECRC) protection and Poison bit support to enable designs that require end-to-end data integrity. PLX also supports data path parity and memory (RAM) error correction circuitry throughout the internal data paths as packets pass through the switch. Flexible Configuration The PEX 8664’s 16 ports can be configured to lane widths of x1, x2, x4, x8, or x16. Flexible buffer allocation, along with the device's flexible packet flow control, maximizes throughput for applications where more traffic flows in the downstream, rather than upstream, direction. Any port can be designated as the upstream port, which can be changed dynamically. Figure 1 shows some of the PEX 8664’s common port configurations in legacy Single-Host mode.
Figure 1. Common Port Configurations
PEX 8664, PCI Express Gen 2 Switch, 64 Lanes, 16 Ports © PLX Technology, www.plxtech.com Page 3 of 3 5/14/2009, Version 1.1 performancePAKTM Exclusive to PLX, performancePAK is a suite of unique and innovative performance features which allows PLX’s Gen 2 switches to be the highest performing Gen 2 switches in the market today. The performancePAK features consists of the Read Pacing, Multicast, and Dynamic Buffer Pool. Read Pacing The Read Pacing feature allows users to throttle the amount of read requests being made by downstream devices. When a downstream device requests several long reads back-to-back, the Root Complex gets tied up in serving that downstream port. If that port has a narrow link and is therefore slow in receiving these read packets from the Root Complex, then other downstream ports may become starved – thus, impacting performance. The Read Pacing feature enhances performances by allowing for the adequate servicing of all downstream devices. Multicast The Multicast feature enables the copying of data (packets) from one ingress port to multiple (up to 15) egress ports in one transaction allowing for higher performance in dual-graphics, storage, security, and redundant applications, among others. Multicast relieves the CPU from having to conduct multiple redundant transactions, resulting in higher system performance. Dynamic Buffer Pool The PEX 8664 employs a dynamic buffer pool for Flow Control (FC) management. As opposed to a static buffer scheme which assigns fixed, static buffers to each port, PLX’s dynamic buffer allocation scheme utilizes a common pool of FC Credits which are shared by other ports. This shared buffer pool is fully programmable by the user, so FC credits can be allocated among the ports as needed. Not only does this prevent wasted buffers and inappropriate buffer assignments, any unallocated buffers remain in the common buffer pool and can then be used for faster FC credit updates. visionPAKTM Another PLX exclusive, visionPAK is a debug diagnostics suite of integrated hardware and software instruments that users can use to help bring their systems to market faster. visionPAK features consist of Performance Monitoring, SerDes Eye Capture, Error Injection, SerDes Loopback, and more. Performance Monitoring The PEX 8664’s real time performance monitoring allows users to literally “see” ingress and egress performance on each port as traffic passes through the switch using PLX’s Software Development Kit (SDK). The monitoring is completely passive and therefore has no affect on overall system performance. Internal counters provide extensive granularity down to traffic & packet type and even allows for the filtering of traffic (i.e. count only Memory Writes). SerDes Eye Capture Users can evaluate their system’s signal integrity at the physical layer using the PEX 8664’s SerDes Eye Capture feature. Using PLX’s SDK, users can view the receiver eye of any lane on the switch. Users can then modify SerDes settings and see the impact on the receiver eye. Figure 5 shows a screenshot of the SerDes Eye Capture feature in the SDK. Figure 5. SerDes Eye Capture Recovered Data Loopback modes.
Applications
Suitable for host-centric as well as peer-to-peer traffic patterns, the PEX 8664 can be configured for a wide variety of form factors and applications. Host Centric Fan-out The PEX 8664, with its symmetric or asymmetric lane configuration capability, allows user-specific tuning to a variety of host-centric applications. Figure 6 shows a
load balancing capability for higher performance. Figure 6. Host Centric Dual Upstream upstream link) manages them. endpoints already in its domain. Figure 8. Host Fail-Over other hosts while actively managing its own endpoints. if/when it gets triggered (see Figure 9).
8 Disk Chassis
Figure 9. N+1 Failover
or Message Signaled Interrupts (MSI) when enabled. and advanced error reporting. Figure 10. PEX8664-16U8D BB RDK
8664 RDK provides everything that a user needs to get
their hardware and software development started.
- For more information, please refer to the PEX
hardware- and software-development kits. product design or specification. Visit www.plxtech.com for more information.