PEX8680 PLX | Alldatasheet
Document overview
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Technical content
Features
PEX 8680 General Features o 80-lane, 20-port PCIe Gen2 switch - Integrated 5.0 GT/s SerDes o 35 x 35mm2, 1156-ball FCBGA package o Typical Power: 9.0 Watts PEX 8680 Key Features o Standards Compliant - PCI Express Base Specification, r2.0 (backwards compatible w/ PCIe r1.0a/1.1) - PCI Power Management Spec, r1.2 - Microsoft Vista Compliant - Supports Access Control Services - Dynamic link-width control - Dynamic SerDes speed control o High Performance ♦ performancePAK
9 Read Pacing (bandwidth throttling)
9 Multicast
9 Dynamic Buffer/FC Credit Pool
- Non-blocking switch fabric - Full line rate on all ports - Packet Cut-Thru with 176ns max packet latency (x16 to x16) - 2KB Max Payload Size o Flexible Configuration - Ports configurable as x1, x2, x4, x8, x16 - Registers configurable with strapping pins, EEPROM, I2C, or host software - Lane and polarity reversal - Compatible with PCIe 1.0a PM o Multi-Host & Fail-Over Support - Configurable Non-Transparent (NT) port - Failover with NT port - Up to Six upstream/Host ports with 1+1 or N+1 failover to other upstream ports o Quality of Service (QoS) - Eight traffic classes per port - Weighted round-robin source port arbitration o Reliability, Availability, Serviceability ♦ visionPAK
9 Per Port Performance Monitoring
Per port payload & header counters
9 SerDes Eye Capture
9 Error Injection and Loopback
- 4 Hot Plug Ports with native HP Signals - All ports hot plug capable thru I (Hot Plug Controller on every port) - ECRC and Poison bit support - Data Path parity - Memory (RAM) Error Correction - INTA# and FATAL_ERR# signals - Advanced Error Reporting - Port Status bits and GPIO available - Per port error diagnostics - JTAG AC/DC boundary scan The ExpressLaneTM PEX 8680 device offers Multi-Host PCI Express switching capability enabling users to connect multiple hosts to their respective endpoints via scalable, high bandwidth, non-blocking interconnection to a wide variety of applications including servers, storage systems, and communications platforms. The PEX 8680 is well suited for fan-out, aggregation, and peer-to-peer applications. Multi-Host Architecture The PEX 8680 employs an enhanced version of PLX’s field tested PEX 8648 PCIe switch architecture, which allows users to configure the device in legacy single-host mode or multi-host mode with up to six host ports capable of 1+1 (one active & one backup) or N+1 (N active & one backup) host failover. This powerful architectural enhancement enables users to build PCIe based systems to support high-availability, failover, redundant and clustered systems. High Performance & Low Packet Latency The PEX 8680 architecture supports packet cut-thru with a maximum latency of 176ns (x16 to x16). This, combined with large packet memory, flexible common buffer/FC credit pool and non-blocking internal switch architecture, provides full line rate on all ports for performance-hungry applications such as servers and switch fabrics. The low latency enables applications to achieve high throughput and performance. In addition to low latency, the device supports a packet payload size of up to 2048 bytes, enabling the user to achieve even higher throughput. Data Integrity The PEX 8680 provides end-to-end CRC (ECRC) protection and Poison bit support to enable designs that require end-to-end data integrity. PLX also supports data path parity and memory (RAM) error correction circuitry throughout the internal data paths as packets pass through the switch. Flexible Configuration The PEX 8680’s 20 ports can be configured to lane widths of x1, x2, x4, x8, or x16. Flexible buffer allocation, along with the device's flexible packet flow control, maximizes throughput for applications where more traffic flows in the downstream, rather than upstream, direction. Any port can be designated as the upstream port, which can be changed dynamically. Figure 1 shows some of the PEX 8680’s common port configurations in legacy Single-Host mode.
Figure 1. Common Port Configurations
for the adequate servicing of all downstream devices. transactions, resulting in higher system performance. be used for faster FC credit updates. Injection, SerDes Loopback, and more. switch using PLX’s Software Development Kit (SDK). (i.e. count only Memory Writes). Eye Capture feature in the SDK. Figure 5. SerDes Eye Capture Recovered Data Loopback modes.
PEX 8680, PCI Express Gen 2 Switch, 80 Lanes, 20 Ports © PLX Technology, www.plxtech.com Page 4 of 4 5/14/2009, Version 1.1
Applications
Suitable for host-centric as well as peer-to-peer traffic patterns, the PEX 8680 can be configured for a wide variety of form factors and applications. Host Centric Fan-out The PEX 8680, with its symmetric or asymmetric lane configuration capability, allows user-specific tuning to a variety of host-centric applications. Figure 6 shows a server design where, in a quad or multi processor system, users can assign endpoints/slots to CPU cores to distribute the system load. The packets directed to different CPUs will go to different (user assigned) PEX 8680 upstream ports, allowing better queuing and load balancing capability for higher performance. CPU CPU CPU CPU CPU CPU CPU CPU x4s MemoryMemory MemoryMemory x8s x16 EndpointEndpoint EndpointEndpoint EndpointEndpoint EndpointEndpoint PCIe Gen1 or PCIe Gen2 slots PEX 8680PEX 8680 PEX 8680PEX 8680 ChipsetChipset ChipsetChipset Figure 6. Host Centric Dual Upstream assigned to the CPU core of the same color. Figure 7. Multi-Host System via a x16 upstream link) manages them. a set of storage devices independent of others (Figure 9). failover event if/when it gets triggered.
8 Disk Chassis
Figure 9. N+1 Failover
or Message Signaled Interrupts (MSI) when enabled. and advanced error reporting. Figure 10. PEX8680-16U8D BB RDK
8680 RDK provides everything that a user needs to get
their hardware and software development started.
- For more information, please refer to the PEX
hardware- and software-development kits. product design or specification. Visit www.plxtech.com for more information.