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PEX 8713, PCI Express Gen 3 Switch, 12 Lanes, 10 Ports © PLX Technology, www.plxtech.com Page 1 of 5 8/1/2011, Version 1.0 Highlights PEX 8713 General Features o 12-lane, 10-port PCIe Gen 3 switch Integrated 8.0 GT/s SerDes o 19 x 19mm2, 324-pin FCBGA package o Typical Power: 4.7 Watts o Native x2 support PEX 8713 Key Features o Standards Compliant PCI Express Base Specification, r3.0 (compatible w/ PCIe r1.0a/1.1 & 2.0) PCI Power Management Spec, r1.2 Microsoft Vista Compliant Supports Access Control Services Dynamic link-width control Dynamic SerDes speed control o High Performance performancePAK Read Pacing (bandwidth throttling) Multicast Dynamic Buffer/FC Credit Pool Non-blocking switch fabric Full line rate on all ports Packet Cut-Thru with 138ns max packet latency (x4 to x4) 2KB Max Payload Size o Integrated DMA Engine Four DMA Channels Internal Descriptor Support DMA function independent from transparent switch function 64-bit Addressing Pre-fetch Descriptor Mode Stride Mode o Multi-Host & Fail-Over Support 2 Configurable Non-Transparent ports Failover with Non-Transparent port Up to 2 upstream/Host ports with 1+1 failover to other upstream port o Quality of Service (QoS) Two Virtual Channels Eight traffic classes per port Weighted round-robin source port arbitration o Reliability, Availability, Serviceability visionPAK Per Port Performance Monitoring SerDes Eye Capture PCIe Packet Generator Error Injection and Loopback 3 Hot Plug Ports with native HP Signals All ports hot plug capable thru I2C SSC Isolation on up to 3 ports ECRC and Poison bit support Data Path parity Memory (RAM) Error Correction Advanced Error Reporting Port Status bits and GPIO available JTAG AC/DC boundary scan The ExpressLane™ PEX 8713 device offers Multi -Host PCI Express switching capability enabling users to connect multiple hosts to their respective endpoints via scalable, high bandwidth, non -blocking interconnection to a wide variety of applications including servers, storage, communications, and graphics platforms. The PEX 8713 is well suited for fan-out, aggregation, and peer-to-peer traffic patterns. Multi-Host Architecture The PEX 8713 employs an enhanced version of PLX’s field tested PEX 8712 PCIe switch architecture, which allows users to configure the device in legacy single-host mode or multi-host mode with up to two host ports capable of 1+1 (one active & one backup) host failover. This powerful architectural enhancement enables users to build PCIe based systems to support high- availability, failover, redundant, or clustered systems. High Performance & Low Packet Latency The PEX 8713 architecture supports packet cut-thru with a maximum latency of 138ns (x4 to x4). This, combined with large packet memory, flexible common buffer/FC credit pool and non-blocking internal switch architecture, provides full line rate on all ports for performance-hungry applications such as servers and switch fabrics. The low latency enables applications to achieve high throughput and performance. In addition to low latency, the device supports a packet payload size of up to 2048 bytes, enabling the user to achieve even higher throughput. Integrated DMA Engine The PEX 8713 boasts a versatile and powerful built-in DMA engine. The DMA engine removes the burden of having to move data between devices away from the processor – allowing the processor to perform computational tasks instead. The four DMA channels can support high data rate transfers between I/O devices connected to any of the switch’s ports. Additionally, the DMA engine in the PEX 8713 can be used to complement the DMA engine in the processor by providing additional DMA channels for higher performance. Data Integrity The PEX 8713 provides end-to-end CRC (ECRC) protection and Poison bit support to enable designs that require end-to-end data integrity. PLX also supports data path parity and memory (RAM) error correction circuitry throughout the internal data paths as packets pass through the switch. Flexible Configuration The PEX 8713’s 10 ports can be configured to lane widths of x1, x2, x4, or x8. Flexible buffer allocation, along with the device's flexible packet flow control, maximizes throughput for applications where more traffic flows in the downstream, rather than upstream, direction. Any port can be designated as the upstream port, which can be changed dynamically. Figure 1 shows some of the PEX 8713’s common port configurations in legacy Single-Host mode.
PEX 8713, PCI Express Gen 3 Switch, 12 Lanes, 10 Ports © PLX Technology, www.plxtech.com Page 2 of 5 8/1/2011, Version 1.0 The PEX 8713 can also be configured in Multi-Host mode where users can choose up to two ports as host/upstream ports and assign a desired number of downstream ports to each host. In Multi-Host mode, a virtual switch is created for each host port and its associated downstream ports inside the device. The traffic between the ports of a virtual switch is completely isolated from the traffic in other virtual switches. Figure 2 illustrates some configurations of the PEX 8713 in Multi-Host mode where each ellipse represents a virtual switch inside the device. The PEX 8713 also provides several ways to configure its registers. The device can be configured through strapping pins, I2C interface, host software, or an optional serial EEPROM. This allows for easy debug during the development phase, performance monitoring during the operation phase, and driver or software upgrade. Dual-Host & Failover Support In Single-Host mode, the PEX 8713 supports 2 Non- Transparent (NT) Ports, which enables the implementation of dual-host systems for redundancy and host failover capability. The NT port allows systems to isolate host memory domains by presenting the processor subsystem as an endpoint rather than another memory system. Base address registers are used to translate addresses; doorbell registers are used to send interrupts between the address domains; and scratchpad registers (accessible by both CPUs) allow inter-processor communication (see Figure 3). Multi-Host & Failover Support In Multi-Host mode, PEX 8713 can be configured with up to two upstream host ports, each with its own dedicated downstream ports. The device can be configured for 1+1 redundancy. The PEX 8713 allows the hosts to communicate their status to each other via special door- bell registers. In failover mode, if a host fails, the host designated for failover will disable the upstream port attached to the failing host and program the downstream ports of that host to its own domain. Figure 4a shows a two host system in Multi-Host mode with two virtual switches inside the device and Figure 4b shows Host 1 disabled after failure and Host 2 having taken over all of Host 1’s end-points. Hot Plug for High Availability Hot plug capability allows users to replace hardware modules and perform maintenance without powering down the system. The PEX 8713 hot plug capability feature makes it suitable for High Availability (HA) applications. Three downstream ports include a Standard Hot Plug Controller. If the PEX 8713 is used in an application where one or more of its downstream ports connect to PCI Express slots, each port’s Hot Plug Controller can be used to manage the hot-plug event of its associated slot. Every port on the PEX 8713 is equipped with a hot-plug control/status register to support hot-plug capability through external logic via the I2C interface. SerDes Power and Signal Management The PEX 8713 provides low power capability that is fully compliant with the PCIe power management specification and supports software control of the SerDes outputs to allow optimization of power and signal strength in a system. Furthermore, the SerDes block supports loop-back modes and advanced reporting of error conditions, which enables efficient management of the entire system. Interoperability The PEX 8713 is designed to be fully compliant with the PCI Express Base Specification r3.0, and is backwards compatible to PCI Express Base Specification r2.0, r1.1,
Message Signaled Interrupts (MSI) when enabled. and advanced error reporting. Figure 10. PEX 8713 RDK Development Kit (also available at www.plxtech.com). hardware and software development started. hardware- and software-development kits. Visit www.plxtech.com for more information.