PEX8712 PLX | Alldatasheet

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Technical content

Figure 1. Common Port Configurations

9 Multicast

9 Per Port Performance Monitoring

9 SerDes Eye Capture

9 PCIe Packet Generator

9 Error Injection and Loopback

  • Per port error diagnostics - JTAG AC/DC boundary scan The ExpressLane™ PEX 8712 device of fers Multi-Host PCI Express switching capability enabling users to connect multiple hosts to their respective endpoints via scalabl e, high bandwidth, non-blocking interconnection to a wide variety of applications including servers, storage, communications, and graphics platforms. The PEX 8712 is well suited for fan-out, aggregation, and peer-to-peer traffic patterns. Multi-Host Architecture The PEX 8712 employs an enhanced version of PLX’s field tested PEX 8612 PCIe switch architecture, which allows users to configure the device in legacy single-host mode or multi-host mode with two host ports capable of 1+1 (one active & one backup) host failover. This powerful architectural enhancement enables users to build PCIe based systems to support high-availability, failover, redundant, or clustered systems. High Performance & Low Packet Latency The PEX 8712 architecture supports packet cut-thru with a maximum latency of 112ns (x4 to x4). This, combined with large packet memory, flexible common buffer/FC credit pool and non-blocking internal switch architecture, provides full line rate on all ports for performance-hungry applications such as servers and switch fabrics. The low latency enables applications to achieve high throughput and performance. In addition to low latency, the device supports a packet payload size of up to 2048 bytes, enabling the user to achieve even higher throughput. Data Integrity The PEX 8712 provides end-to-end CRC (ECRC) protection and Poison bit support to enable designs that require end-to-end data integrity. PLX also supports data path parity and memory (RAM) error correction circuitry throughout the internal data paths as packets pass through the switch. Flexible Configuration The PEX 8712’s 3 ports can be configured to lane widths of x1, x2, x4, or x8. Flexible buffer allocation, along with the device's flexible packet flow control, maximizes throughput for applications where more traffic flows in the downstream, rather than upstream, direction. Any port can be designated as the upstream port, which can be changed dynamically. Figure 1 shows some of the PEX 8712’s common port configurations in legacy Single-Host mode

PEX 8712, PCI Express Gen 3 Switch, 12 Lanes, 3 Ports © PLX Technology, www.plxtech.com Page 4 of 5 10/7/2010, Version 1.0 Memory CPU CPU CPU CPU x4x4 x1s SATA Endpoint PCIe Gen1, Gen2, or Gen3 slots PEX 8712 PCI PCH rror Injection & SerDes Loopback users can ts red

Applications

centric as well as peer-to-peer traffic metric or asymmetric lane -out t etwork Interface Cards lized in communications es. ntion or E Using the PEX 8712’s Error Injection feature, inject malformed packets and/or fatal errors into their system and evaluate a system’s ability to detect and recover from such errors. The PEX 8712 also suppor Internal Tx, External Tx, Recovered Clock, and Recove Data Loopback modes. Suitable for host- patterns, the PEX 8712 can be configured for a wide variety of form factors and applications. Host Centric Fan-out The PEX 8712, with its sym configuration capability, allows user-specific tuning to a variety of host-centric applications. Figure 6 shows a server design where the PEX 8712 is being used to fan to endpoints and PCI Express slots. Since the PEX 8712 is compliant with PCIe Gen 1 and Gen 2 devices, the PEX 8712 can also be used to bridge Gen 1and Gen 2 endpoints to Gen 3 chipsets and processors (and vice versa). Figure 6. Host Centric Fan-Ou applications such as Network Interface Cards (NICs). Figure 7. 10GE NIC Fan-Out utilizing a PEX 8612 to fan-out to two ASICs/FPGAs. Figure 8. Embedded Systems

8 Disk Chassis

Figure 9. Multicast in Storage Systems

hardware and software development started. hardware- and software-development kits. Message Signaled Interrupts (MSI) when enabled. and advanced error reporting. Visit www.plxtech.com for more information. Figure 10. PEX 8712 RDK Development Kit (also available at www.plxtech.com).