LSH32

LSH32 LODEV | Alldatasheet

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32-bit Cascadable Barrel Shifter Special Arithmetic Functions 08/16/2000–LDS.32-Q1 configured such that any contiguous 16-bit field (including wraparound of the 32 inputs) may be presented to the output pins under control of the shift code field (wrap mode). Alterna- tively, the wrap feature may be disabled, resulting in zero or sign bit fill, as appropriate (fill mode). The shift code control assignments and the resulting input to output mapping for the wrap mode are shown in Table 1. Essentially the LSH32 is configured as a left shift device. That is, a shift code of 00000 2 results in no shift of the input field. A code of 00001 2 provides an effective left shift of 1 position, etc. When viewed as a right shift, the shift code corresponds to the two’s com- plement of the shift distance, i.e., a shift code of 11111 2 (–110) results in a right shift of one position, etc. When not in the wrap mode, the LSH32 fills bit positions for which there is no corresponding input bit. The fill value and the positions filled depend on the RIGHT/LEFT (R/L) direction pin. This pin is a don’t care input when in wrap mode. For left shifts in fill mode, lower bits are filled with zero as shown in Table 2. For right shifts, however, the SIGN input is used as the fill value. Table 3 depicts the bits to be filled as a function of shift code for the right shift case. Note that the R/L input changes only the fill convention, and does not affect the definition of the shift code. In fill mode, as in wrap mode, the shift code input represents the number of shift positions directly for left shifts, but the two’s complement of the shift code results in the equivalent right shift. However, for fill mode the R/L input can be viewed as the most ❑❑❑❑❑ 32-bit Input, 32-bit Output Multi- plexed to 16 Lines ❑❑❑❑❑ Full 0-31 Position Barrel Shift Capability ❑❑❑❑❑ Integral Priority Encoder for 32-bit Floating Point Normalization ❑❑❑❑❑ Sign-Magnitude or Two’s Comple- ment Mantissa Representation ❑❑❑❑❑ 32-bit Linear Shifts with Sign or Zero Fill ❑❑❑❑❑ Independent Priority Encoder Outputs for Block Floating Point ❑❑❑❑❑ 68-pin PLCC, J-Lead FEATURES DESCRIPTION LSH32 32-bit Cascadable Barrel ShifterDEVICES INCORPORATED The LSH32 is a 32-bit high speed shifter designed for use in floating point normalization, word pack/ unpack, field extraction, and similar applications. It has 32 data inputs, and 16 output lines. Any shift configuration of the 32 inputs, includ- ing circular (barrel) shifting, left shifts with zero fill, and right shift with sign extend are possible. In addition, a built-in priority encoder is provided to aid floating point normalization. SHIFT ARRAY The 32 inputs to the LSH32 are applied to a 32-bit shift array. The 32 outputs of this array are multiplexed down to 16 lines for presentation at the device outputs. The array may be LSH32 B LOCK DIAGRAM OE MS/LS 32-bit BARREL SHIFT ARRAY 16 16 2:1 32:5 PRIORITY ENCODE 32 SIGN I31-I0 NORM RIGHT/LEFT FILL/WRAP 2:1 Y 15-Y0SO 4-SO 0 SI4-SI0

first non-zero bit in the input word. complement mantissa representation. function table is shown in Table 4. TABLE 1. W RAP MODE SHIFT CODE DEFINITIONS

00000 I31 I30 I29 • • • I16 I15 • • • I2 I1 I0

00001 I30 I29 I28 • • • I15 I14 • • • I1 I0 I31

00010 I29 I28 I27 • • • I14 I13 • • • I0 I31 I30

00011 I28 I27 I26 • • • I13 I12 • • • I31 I30 I29

01111 I16 I15 I14 • • • I1 I0• • • I19 I18 I17

10000 I15 I14 I13 • • • I0 I31 • • • I18 I17 I16

10001 I14 I13 I12 • • • I31 I30 • • • I17 I16 I15

10010 I13 I12 I11 • • • I30 I29 • • • I16 I15 I14

11100 I3 I2 I1• • • I20 I19 • • • I6 I5 I4

11101 I2 I1 I0• • • I19 I18 • • • I5 I4 I3

11110 I1 I0 I31 • • • I18 I17 • • • I4 I3 I2

11111 I0 I31 I30 • • • I17 I16 • • • I3 I2 I1

TABLE 2. FILL MODE SHIFT CODE DEFINITIONS — LEFT SHIFT

00001 I30 I29 I28 • • • I15 I14 • • • I1 I0 0

00010 I29 I28 I27 • • • I14 I13 • • • I0 00

00011 I28 I27 I26 • • • I13 I12 • • • 000

01111 I16 I15 I14 • • • I1 I0• • • 000

10000 I15 I14 I13 • • • I0 0 • • • 000

10001 I14 I13 I12 • • • 00 • • • 000

10010 I13 I12 I11 • • • 00 • • • 000

11100 I3 I2 I1• • • 00 • • • 000

11101 I2 I1 I0• • • 00 • • • 000

11110 I1 I0 0 • • • 00 • • • 000

11111 I0 00 • • • 00 • • • 000

with routing the shift code off chip. be available simultaneously. TABLE 3. FILL MODE SHIFT CODE DEFINITIONS — RIGHT SHIFT TABLE 4. PRIORITY ENCODER FUNCTION TABLE

00000 S S S • • • SS • • • SSS

00001 S S S • • • SS • • • SSI 31

00010 S S S • • • SS • • • SI 31 I30

00011 S S S • • • SS • • • I31 I30 I29

01111 S S S • • • SS • • • I19 I18 I17

10000 S S S • • • SI 31 • • • I18 I17 I16

10001 S S S • • • I31 I30 • • • I17 I16 I15

10010 S S S • • • I30 I29 • • • I16 I15 I14

11100 S S S • • • I20 I19 • • • I6 I5 I4

11101 S S S • • • I19 I18 • • • I5 I4 I3

11110 S S I31 • • • I18 I17 • • • I4 I3 I2

11111 S I31 I30 • • • I17 I16 • • • I3 I2 I1

32-bit Cascadable Barrel Shifter Special Arithmetic Functions 08/16/2000–LDS.32-Q5 tially the LSH32s are arranged in multiple rows or banks such that the inputs to successive rows are left- shifted by 16 positions. The outputs of each row are multiplexed onto a three-state bus. The normalization problem then reduces to selecting from among the several banks that one which has the first non-zero bit of the input value among its 16 most significant positions. If the most significant one in the input file was within the upper 16 locations of a given bank, the SO 4 output of the most significant slice in that bank will be low. Single clock normalization can thus be accomplished simply by enabling onto the three-state output bus the highest priority bank in which this condition is met. In this way the input word will be normalized regardless of the number of shift positions required to accomplish this. The number of shift positions can be determined simply by concatenation of the SO 3–SO0 outputs of the most significant slice in the selected row with the encoded Output Enable-bits determining the row number. Note that lower rows need not be fully populated. This is because they represent left shifts in multiples of 16 positions, and the lower bits of the output word will be zero filled. In order to accomplish this zero fill, the least significant device in each row is always enabled, and the row select is instead connected to the SI 4 input. This will force the shift length of the least significant device to a value greater than 15 whenever the row containing that device is not selected. This results in zero fill being accom- plished by the equivalently positioned slice in a higher bank, as shown in the diagram. BLOCK FLOATING POINT With a small amount of external logic, block floating point operations are easily accomplished by the LSH32. Data resulting from a vector operation are applied to the LSH32 with the NORM-input deasserted. The SO SO0 outputs fill then represent the normalization shift distance for each vector element in turn. By use of an external latch and comparator, the maximum shift distance encountered across all elements in the vector is saved for use in the next block opera- tion (or block normalization). During this subsequent pass through the data, the shift code saved from the previous pass is applied uniformly across all elements of the vector. Since the LSH32 is not used in the internal normalize mode, this operation can be pipelined, thereby obtaining the desired shift distance for the next pass while simultaneously applying the normalization required from the previous pass.

32-bit Cascadable Barrel Shifter Special Arithmetic Functions 08/16/2000–LDS.32-Qffs6 Symbol Parameter Test Condition Min Typ Max Unit VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.4 V VOL Output Low Voltage VCC = Min., IOL = 8.0 mA 0.4 V VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage (Note 3) 0.0 0.8 V IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±20 µA IOZ Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±20 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 10 30 mA ICC2 VCC Current, Quiescent (Note 7) 1.5 mA M AXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) O PERATING CONDITIONS To meet specified electrical and switching characteristics ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Mode Temperature Range (Ambient) Supply Voltage Active Operation, Commercial 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V Active Operation, Military –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V

32-bit Cascadable Barrel Shifter Special Arithmetic Functions 08/16/2000–LDS.32-Q7 1234567890123456 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1 23456789012345 6 1234567890123456 1234567890123456789012345678901212345678901234 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1 23456789012345678901234567890121234567890123 4 1234567890123456789012345678901212345678901234 LSH32– 42* 32 20 Symbol Parameter Min Max Min Max Min Max tIY I, SIGN Inputs to Y Outputs 42 32 20 tIYN I, SIGN Inputs to Y Outputs, Normalize Mode 75 60 20 tISO I, SIGN Inputs to SO Outputs 55 42 20 tSIY SI, RIGHT/LEFT to Y Outputs 52 40 20 tMSY MS/LS Select to Y Outputs 28 24 15 tDIS Three-State Output Disable Delay (Note 11) 20 20 15 tENA Three-State Output Enable Delay (Note 11) 20 20 15 SWITCHING CHARACTERISTICS C OMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) LSH32– 50* 40* 30* Symbol Parameter Min Max Min Max Min Max tIY I, SIGN Inputs to Y Outputs 50 40 30 tIYN I, SIGN Inputs to Y Outputs, Normalize Mode 85 75 58 tISO I, SIGN Inputs to SO Outputs 65 52 42 tSIY SI, RIGHT/LEFT to Y Outputs 62 52 40 tMSY MS/LS Select to Y Outputs 32 26 24 tDIS Three-State Output Disable Delay (Note 11) 22 20 17 tENA Three-State Output Enable Delay (Note 11) 22 20 17 M ILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 *DISCONTINUED SPEED GRADE HIGH IMPEDANCE SIGN tENAtDIS MS/LS OE tMSY tSIY tIY, tIYN tISO SI4-SI0 RIGHT/LEFT I31-I0 SO 4-SO0 Y31-Y0 Y31-Y0 SWITCHING WAVEFORMS

32-bit Cascadable Barrel Shifter Special Arithmetic Functions 08/16/2000–LDS.32-Qffs8 1. Maximum Ratings indicate stress specifications only. Functional oper- ation of these products at values beyond those indicated in the Operating Condi- tions table is not implied. Exposure to maximum rating conditions for ex- tended periods may affect reliability. 2. The products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. Neverthe- less, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. This device provides hard clamping of transient undershoot and overshoot. In- put levels below ground or above V CC will be clamped beginning at –0.6 V and VCC + 0.6 V. The device can withstand indefinite operation with inputs in the range of –0.5 V to +7.0 V. Device opera- tion will not be adversely affected, how- ever, input current levels will be well in excess of 100 mA. 4. Actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. Supply current for a given applica- tion can be accurately approximated by: where N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing ev- ery cycle and no load, at a 5 MHz clock rate. 7. Tested with all inputs within 0.1 V of V CC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. NCV F NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except t DIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed. This device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The following measures are recommended: a. A 0.1 µF ceramic capacitor should be installed between V CC and Ground leads as close to the Device Under Test (DUT) as possible. Similar capacitors should be installed between device VCC and the tester common, and device ground and tester common. b. Ground and VCC supply planes must be brought directly to the DUT socket or contactor fingers. c. Input voltages should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT input levels relative to the DUT ground pin. 10. Each parameter is shown as a min- imum or maximum value. Input re- quirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter- nal system must supply at least that much time to meet the worst-case re- quirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. For the t ENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing volt- age, V TH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Z- to-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. IOH IOL VTHC L DUT OE 0.2 V tDIStENA 0.2 V 1.5 V 1.5 V 3.5V Vth 1 Z 0 Z Z 1 Z 0 1.5 V 1.5 V 0V Vth VOL * VOH * VOL * VOH * Measured VOL with IOH = –10mA and IOL = 10mA Measured VOH with IOH = –10mA and IOL = 10mA FIGURE B. THRESHOLD LEVELS FIGURE A. OUTPUT LOADING CIRCUIT

32-bit Cascadable Barrel Shifter Special Arithmetic Functions 08/16/2000–LDS.32-Q9 1234567890123456789012345678901212345678901234567 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1 23456789012345678901234567890121234567890123456 7 1234567890123456789012345678901212345678901234567 Discontinued Package 68-pin

ORDERING INFORMATION

0°C to +70°C — COMMERCIAL SCREENING Plastic J-Lead Chip Carrier (J2) LSH32JC32 LSH32JC20 Speed 32 ns 20 ns Ceramic Pin Grid Array (G1) –55°C to +125°C — MIL-STD-883 COMPLIANT –55°C to +125°C — COMMERCIAL SCREENING A B C D E F G H J K L Top View Through Package (i.e., Component Side Pinout) 12345 6 7 8 9 10 11 I29 I30 SIGN SO 3 SO 1 NORM SI3 SI1 R/L Y30/14 Y29/13 I28 I27 Y28/12 Y27/11 I26 I25 Y26/10 Y25/9 I24 I23 Y24/8 Y23/7 I22 I21 Y22/6 Y21/5 I20 I19 Y20/4 Y19/3 I18 I17 Y18/2 Y17/1 I16 I15 Y16/0 OE I14 GND I12 I10 VCC MS/LS I31 SO 4 SO 2 SO 0 SI4 SI2 SI0 F/W Y31/15 GND I13 I11 VCC 6768 64 65 Top View 46 6 63 6212 27 32 33 34 35 36 37 38 39 40 41 42 43 586 7 28 29 30 31 GND I13 I12 I11 I10 VCC VCC I30 I31 SIGN SO 4 SO 3 SO 2 SO 1 SO 0 NORM SI4 SI3 SI2 SI1 SI0 R/L F/W Y31/15 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 GND Y30/14 Y29/13 Y28/12 Y27/11 Y26/10 Y25/9 Y24/8 Y23/7 Y22/6 Y21/5 Y20/4 Y19/3 Y18/2 Y17/1 Y16/0 OE MS/LS