LF2301 LODEV | Alldatasheet
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Image Resampling Sequencer 08/16/2000–LDS.2301-H ❑❑❑❑❑ High-Speed Image Manipulation ❑❑❑❑❑ Maximum Image Size: 4096 x 4096 Pixels ❑❑❑❑❑ Supports Following Interpolation Algorithms:
- Nearest-Neighbor
- Bilinear Interpolation
- Cubic Convolution
- Video Special-Effects
- Image Recognition
- High-Speed Data Encoding/ Decoding ❑❑❑❑❑ Replaces TRW/Raytheon/Fairchild TMC2301 ❑❑❑❑❑ 68-pin PLCC, J-Lead FEATURES DESCRIPTION LF2301 Image Resampling SequencerDEVICES INCORPORATED LF2301 BLOCK DIAGRAM SOURCE ADDRESS GENERATOR TARGET ADDRESS GENERATOR INPUT IMAGE BOUNDARY COMPARATOR ACC DONE WENLDR B 3-0 P11-0 INTER INITNOOP END PARAMETER STORAGE CONTROL INTEGERFRACTION CZERO U 11-0UWRIX11-0CA 7-0 WALK COUNT OETA The LF2301 is a self-sequencing address generator designed to filter a two-dimensional image or remap and resample it from one set of Cartesian coordinates (x,y) into a new set (u,v). The LF2301 can resample digitized images or perform such manipula- tions as rotation, panning, zooming, and warping as well as compression in real-time. By using two LF2301s in a Image Transformation System (ITS), nearest-neighbor, bilinear interpola- tion, and cubic convolution algo- rithms, with kernel sizes up to 4 x 4 pixels, are all possible (see Figure 1). This system can also implement simple static filters with kernel sizes up to 16 x 16 pixels. DETAILS OF OPERATION Most video applications use a pair of LF2301s in tandem to construct an ITS. One LF2301 is the row coordinate generator (x to u) and the other is the column generator (y to v). External RAM is needed for storage of the interpolation coeffi- cient lookup table, as well as for buffers of the source and destination images. An external Multiplier- Accumulator is required when performing interpolation or imple- menting static filters. The ITS is capable of performing the general second-order coordinate transformation of the form: x(u,v) = Au 2+Bu+Cuv+Dv 2+Ev+F y(u,v) = Gu2+Hu+Kuv+Lv2+Mv+N where parameters A through N of the transform are user-defined. The system steps sequentially through each pixel in the “target” image lying within a user-defined rectangle. For each “target” pixel at (u,v), the LF2301 points to a corresponding “source” pixel at (x,y).
latched on the rising edge of CLK. latched on the rising edge of CLK. Transformation Parameter Registers. loading in only the new first product. is forced to the high-impedance state. reset of the address counter. FIGURE 1. IMAGE TRANSFORMATION SYSTEM (ITS)
Image Resampling Sequencer 08/16/2000–LDS.2301-H impedance state. Users may then access external memory. Normal operation resumes on the next clock cycle after NOOP goes HIGH. NOOP is latched on the rising edge of CLK. OETA — Target Memory Output Enable When OETA is HIGH, UWRI and U 11-0 are forced to the high-impedance state. When OETA is LOW, UWRI and U11-0 are enabled on the next clock cycle. OETA is latched on the rising edge of CLK. Flags CZERO — Coefficient Zero If in a row device x<0, XMIN≤x≤XMAX, or x ≥4096, the registered CZERO flag goes HIGH . If 0≤x<XMIN or XMAX<x<4096, CZERO goes LOW. In an ITS, when the source address falls outside a rectangle with vertices (XMIN, YMIN), (XMAX, YMIN), (XMIN, YMAX), and (XMAX, YMAX), the logical AND of the CZERO flags from the row and column of the LF2301s will go LOW representing an invalid address. END — End of Row/Frame When two LF2301s are used to form an ITS, the END flag on each device is connected to INTER on the other device. The END flag from the row device indicates an “end of line” to the column device. The END flag from the column device indicates a “bottom of frame” to the row device, forcing a reset of the address counter. When Mode is set to “00” or “10” END goes HIGH on the row device for (K+1) x (K+1) clock cycles starting[2 x (K+1) x (K+1)] + 1 clock cycles before the last X address of a row. END goes HIGH on the column device for (K+1) 3 x (UMAX-UMIN) clock cycles starting at (K+1)3 x (UMAX-UMIN) + 1 clock cycles before the last X address of a frame. When Mode is set to “01” or “11” END goes HIGH on the row device for K+1 clock cycles starting at (K+1) + 2 clock cycles before the last X address of a row. END goes HIGH on the column device for (K+1) x (K+1) clock cycles starting at [(K+1) x (K+1)] + 1 clock cycles before the last X address of a frame. DONE — End of Transform In a two LF2301 system, after the last walk of the last row of an image, the registered DONE flag goes HIGH indicating the end of the transform. DONE goes HIGH one clock cycle before the last X address of a frame. If AIN is HIGH, DONE will remain HIGH for one clock cycle. If AIN is LOW, DONE will remain HIGH until a new transform begins. Transformation Control Parameters XMIN, XMAX, YMIN, YMAX XMIN, XMAX, YMIN, YMAX define the valid area in the source image from which pixels may be read. The CZERO flags will denote a valid memory read whenever the LF2301s generate an (x,y) address within this boundary. UMIN, UMAX, VMIN, VMAX UMIN, UMAX, VMIN, VMAX define the area in the destination image into which pixels will be written. (UMIN, VMIN) is the top left corner and (UMAX + 1, VMAX) is the bottom right corner. The following conditions must be met: UMAX>UMIN and VMAX>VMIN. x 0, y0 x0, y0 determine what the first pixel read out of the source image will be at the beginning of an image transformation. x 0, y0 will be the upper left corner of the original image in non-inverting, non- reversing applications. dx/du dx/du is the displacement along the x axis corresponding to a one-pixel movement along the u axis. dx/dv dx/dv is the displacement along the x axis corresponding to each one-pixel movement along the v axis. dy/du dy/du is the displacement along the y axis corresponding to each one-pixel movement along the u axis. dy/dv dy/dv is the displacement along the y axis corresponding to each one-pixel movement along the v axis. d 2x/du2 d2x/du2 determines the rate of change of dx/du with each step along a line in the output image. d 2x/dv2 d2x/dv2 determines the rate of change of dx/dv with each step down a column in the output image. d 2y/du2 d2y/du2 determines the rate of change of dy/du with each step along a line in the output image. d 2y/dv2 d2y/dv2 determines the rate of change of dy/dv with each step down a column in the output image. d 2x/dudv d2x/dudv determines the rate of change of dx/du while moving vertically through the output image. d 2x/dudv also determines the rate of change of dx/dv while moving horizontally through the output image. d 2y/dudv d2y/dudv determines the rate of change of dy/dv while moving horizontally through the output image. d 2y/dudv also determines the rate of change of dy/du while moving vertically through the output image.
TABLE 3. FIELD OF VIEW LF2301 functions as a column device. the counter clockwise direction. kernel in the vertical dimension. the final destination image. pixels (Kernel = 15) are possible. to the generation of the target address. rescaling, all at real-time video rates. convolutions, can also be performed. TABLE 1. MODE SELECTION TABLE 2. KERNEL
0011 ALR AIN PIPE R/C M1 M 0 –212 211 210 29 28 27 Controls, x0 (MS) Controls, y 0 (LS)
0101 TM F 2 F1 F0 –27 26 25 24 23 22 21 20 Controls, dx/du (MS) Controls, dy/du (MS)
0111 K 3 K2 K1 K0 –27 26 25 24 23 22 21 20 Kernel, dx/dv (MS) Kernel, dy/dv (MS)
TABLE 4. PARAMETER REGISTER FORMATS (ROW OR COLUMN MODE ) Parameters to be updated on-the-fly. Transformation Parameter Registers. FIGURE 4. LDR CONTROL FOR PARAMETER UPDATE
Figure 5. This mode is selected by completed was the last for that line). be 0 and dy/du is selected to be 1. filter and are therefore set to 0. outputs for the 3 x 3 static filter. TABLE 5. PARAMETER REGISTERS
0001 FFF FFF
2 = 1st pixel of 2nd spiral walk, etc. FIGURE 5. 3 ××××× 3 STATIC FILTER
TABLE 6. ITS OUTPUTS FOR 3 ××××× 3 STATIC FILTER
requires a kernel size of 2 x 2 pixels. TABLE 7. PARAMETER REGISTERS
0100 DDB 800
FIGURE 7. 30°°°°° IMAGE ROTATION 2 = 1st pixel of 2nd spiral walk, etc. FIGURE 8. 30°°°°° IMAGE ROTATION FIGURE 6. DIFFERENTIAL TERMS
TABLE 8. ITS OUTPUTS FOR 30°°°°° IMAGE ROTATION WITH BILINEAR INTERPOLATION
TABLE 10. ITS OUTPUTS FOR PASS 1 OF TWO -PASS TABLE 9. PARAMETER REGISTERS 2 = 1st pixel of 2nd walk, etc. FIGURE 9. PASS 1 OF TWO -PASS
TABLE 12. ITS OUTPUTS FOR PASS 2 OF TWO -PASS kernel size of 3 pixels is desired. in this filter and are therefore set to 0. TABLE 11. PARAMETER REGISTERS 2 = 1st pixel of 2nd walk, etc. FIGURE 10. PASS 2 OF TWO -PASS
Image Resampling Sequencer 08/16/2000–LDS.2301-H M AXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) O PERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Supply Voltage Active Operation, Commercial 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V Active Operation, Military –55°C to +125°C 4.50 V ≤ VCC ≤ 5.50 V Symbol Parameter Test Condition Min Typ Max Unit VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.4 V VOL Output Low Voltage VCC = Min., IOL = 4.0 mA 0.4 V VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage (Note 3) 0.0 0.8 V IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±10 µA IOZ Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±10 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 75 mA ICC2 VCC Current, Quiescent (Note 7) 5m A C IN Input Capacitance TA = 25°C, f = 1 MHz 10 pF C OUT Output Capacitance TA = 25°C, f = 1 MHz 10 pF ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Image Resampling Sequencer 2-14 08/16/2000–LDS.2301-H Video Imaging Products 1234567890123456789012345678901212345678901234 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 1234567890123456789012345678901212345678901234 1234567890123456 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 1234567890123456 LF2301– 66* 55 25 Symbol Parameter Min Max Min Max Min Max tCYC Cycle Time 66 55 25 tPW Clock Pulse Width 30 25 10 tS Input Setup Time 20 18 10 tH Input Hold Time 2 2 0 tHI Input Hold Time, INTER 10 10 5 tD Output Delay 35 27 18 tDE Output Delay, END 45 37 18 tENA Three-State Output Enable Delay (Note 11) 35 27 15 tDIS Three-State Output Disable Delay (Note 11) 20 18 15 C OMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING CHARACTERISTICS M ILITARY OPERATING RANGE (-55°C to +125°C) Notes 9, 10 (ns) 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 *DISCONTINUED SPEED GRADE LF2301– 66* 55* 30* Symbol Parameter Min Max Min Max Min Max tCYC Cycle Time 66 55 30 tPW Clock Pulse Width 30 25 10 tS Input Setup Time 20 18 12 tH Input Hold Time 2 2 0 tHI Input Hold Time, INTER 10 10 6 tD Output Delay 35 27 20 tDE Output Delay, END 45 37 20 tENA Three-State Output Enable Delay (Note 11) 35 27 18 tDIS Three-State Output Disable Delay (Note 11) 20 18 18
Image Resampling Sequencer 08/16/2000–LDS.2301-H SWITCHING WAVEFORMS : DATA OUTPUTS AND CONTROL LINES CLK tCYC tPWtPW tS tHI HIGH IMPEDANCE HIGH IMPEDANCE END UWRI CZERO, ACC, DONE X11-0, CA7-0 NOOP OETA INTER tENA tDIS tS tH tHtS tDE tENA HIGH IMPEDANCE U11-0 tDIStD tENA tDIS SWITCHING WAVEFORMS : DATA INPUTS (PARAMETER STORAGE ) CLK tCYC tPWtPW tS tH P11-0 LDR WEN B3-0
Image Resampling Sequencer 2-16 08/16/2000–LDS.2301-H Video Imaging Products 1. Maximum Ratings indicate stress specifications only. Functional oper- ation of these products at values beyond those indicated in the Operating Condi- tions table is not implied. Exposure to maximum rating conditions for ex- tended periods may affect reliability. 2. The products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. Neverthe- less, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. This device provides hard clamping of transient undershoot and overshoot. In- put levels below ground or above V CC will be clamped beginning at –0.6 V and VCC + 0.6 V. The device can withstand indefinite operation with inputs in the range of –0.5 V to +7.0 V. Device opera- tion will not be adversely affected, how- ever, input current levels will be well in excess of 100 mA. 4. Actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. Supply current for a given applica- tion can be accurately approximated by: where N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with no output load at 15 MHz clock rate. 7. Tested with all inputs within 0.1 V of V CC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. NCV F NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except t DIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed. This device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The following measures are recommended: a. A 0.1 µF ceramic capacitor should be installed between V CC and Ground leads as close to the Device Under Test (DUT) as possible. Similar capacitors should be installed between device VCC and the tester common, and device ground and tester common. b. Ground and VCC supply planes must be brought directly to the DUT socket or contactor fingers. c. Input voltages should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT in- put levels relative to the DUT ground pin. 10. Each parameter is shown as a mini- mum or maximum value. Input require- ments are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal cir- cuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst- case operation of any device always pro- vides data within that time. 11. For the t ENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing volt- age, V TH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Z- to-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. IOH IOL VTHC L DUT OE 0.2 V tDIStENA 0.2 V 1.5 V 1.5 V 3.5V Vth 1 Z 0 Z Z 1 Z 0 1.5 V 1.5 V 0V Vth VOL * VOH * VOL * VOH * Measured VOL with IOH = –10mA and IOL = 10mA Measured VOH with IOH = –10mA and IOL = 10mA FIGURE B. THRESHOLD LEVELS FIGURE A. OUTPUT LOADING CIRCUIT
Image Resampling Sequencer 08/16/2000–LDS.2301-H 1234567 68 67 66 65 64 63 3635 37 38 39 413029 31 32 33 34 Top View 896 2 6 1 2827 42 43 GND X10 X11 P11 P10 GND U U 8 U 7 U 6 U 5 U 4 U 3 GND U U 1 U 0 DONE END INTER OETA INIT CLK GND VCC NOOP LDR WEN GND XO CA 7 CA 6 CA 5 CA 4 CA 3 CA 2 GND V CC CA 1 CA 0 CZERO ACC UWRI U U 10
ORDERING INFORMATION
0°C to +70°C — COMMERCIAL SCREENING Speed 55 ns 25 ns Plastic J-Lead Chip Carrier (J2) LF2301JC55 LF2301JC25 68-pin
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–55°C to +125°C — MIL-STD-883 COMPLIANT –55°C to +125°C — COMMERCIAL SCREENING Ceramic Pin Grid Array (G1) 68-pin A B C D E F G H J K L Top View Through Package (i.e., Component Side Pinout) 12345 6 7 8 9 10 11 WEN INIT INTER DONE U 1 GND U 4 U 6 U 8 U 10 U 11 UWRI ACC CZERO CA 0 LDR NOOP CA 1 VCC VCC GND GND CA CLK CA 3 CA 4 CA 5 CA 6 CA 7 P11 X10 GND GND OETA END U 0 U 2 U 3 U 5 U 7 U 9 GND P10 X11 0°C to +70°C — COMMERCIAL SCREENING Discontinued Package