LF2242

LF2242 LODEV | Alldatasheet

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12/16-bit Half-Band Interpolating/ Decimating Digital Filter Video Imaging Products 1 08/16/2000–LDS.2242-K LF2242 12/16-bit Half-Band Interpolating/ Decimating Digital FilterDEVICES INCORPORATED ❑❑❑❑❑ Passband (0 to 0.22fS) Ripple: ±0.02 dB ❑❑❑❑❑ Stopband (0.28fS to 0.5fS) Rejection: 59.4 dB ❑❑❑❑❑ User-Selectable 2:1 Decimation or 1:2 Interpolation ❑❑❑❑❑ 12-bit Two’s Complement Input and 16-bit Output with User-Selectable Rounding, 8- to 16-Bits ❑❑❑❑❑ User-Selectable Two’s Complement or Inverted Offset Binary Output Formats ❑❑❑❑❑ Three-State Outputs ❑❑❑❑❑ Replaces TRW/ Raytheon/ Fairchild TMC2242 ❑❑❑❑❑ Package Styles Available:

• 44-pin PLCC, J-Lead
• 44-pin PQFP FEATURES DESCRIPTION The LF2242 is a linear-phase, half- band (low pass) interpolating/ decimating digital filter that, unlike intricate analog filters, requires no tuning. The LF2242 can also signifi- cantly reduce the complexity of traditional analog anti-aliasing pre- filters without compromising the signal bandwidth or attenuation. This can be achieved by using the LF2242 as a decimating post-filter with an A/D converter and by sampling the signal at twice the rate needed. Likewise, by using the LF2242 as an interpolating pre-filter with a D/A converter, the corresponding analog reconstruction post-filter circuitry can be simplified. The coefficients of the LF2242 are fixed, and the only user programming required is the selection of the mode (interpolate, decimate, or pass- through) and rounding. The asyn- chronous three-state output enable control simplifies interfacing to a bus. Data can be input into the LF2242 at a rate of up to 40 million samples per second. Within the 40 MHz I/O limit, the output sample rate can be one- half, equal to, or two times the input sample rate. Once data is clocked in, the 55-value output response begins after 7 clock cycles and ends after 61 clock cycles. The pipeline latency from the input of an impulse response to its corresponding output peak is 34 clock cycles. The output data may be in either two’s complement format or inverted offset binary format. To avoid truncation errors, the output data is always internally rounded before it is latched into the output register. Rounding is user-selectable, and the output data can be rounded from 16 bit values down to 8 bit values. DC gain of the LF2242 is 1.0015 (0.0126 dB) in pass-through and decimate modes and 0.5007 (–3.004 dB) in interpolate mode. Passband ripple does not exceed ±0.02 dB from 0 to 0.22f S with stopband attenuation greater than 59.4 dB from 0.28 fS to 0.5fS (Nyquist frequency). The response of the filter is –6 dB at 0.25 fS. Full compliance with CCIR Recom- mendation 601 (–12 dB at 0.25 f S) can be achieved by cascading two devices serially. LF2242 BLOCK DIAGRAM OETO ALL REGISTERS SI11–0 INTERPOLATION CIRCUIT 55-TAP FIR FILTER ROUND AND LIMIT CIRCUIT DECIMATION CIRCUIT RND 2–0TCO SO 15–0 SYNCINT DEC CLK 161212

data rate and the output amplitude. FIGURE 1. FREQUENCY RESPONSE OF FILTER enced to the rising edge of CLK. or it can be toggled at half the clock rate. and INT are equal (pass-through mode). TABLE 1. M ODE SELECTION

MSB — the MSB is unchanged). outputs are in a high-impedance state. FIGURE 2. INPUT AND OUTPUT FORMATS TABLE 2. ROUNDING FORMAT

12/16-bit Half-Band Interpolating/ Decimating Digital Filter Video Imaging Products 4 08/16/2000–LDS.2242-K M AXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) O PERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Supply Voltage Active Operation, Commercial 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V Active Operation, Industrial -40°C to +85°C 4.75 V ≤ VCC ≤ 5.25 V Symbol Parameter Test Condition Min Typ Max Unit VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.4 V VOL Output Low Voltage VCC = Min., IOL = 4.0 mA 0.4 V VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage (Note 3) 0.0 0.8 V IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±10 µA IOZ Output Leakage Current (Note 12) ±10 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 80 mA ICC2 VCC Current, Quiescent (Note 7) 10 mA C IN Input Capacitance TA = 25°C, f = 1 MHz 10 pF C OUT Output Capacitance TA = 25°C, f = 1 MHz 10 pF ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)

12/16-bit Half-Band Interpolating/ Decimating Digital Filter Video Imaging Products 5 08/16/2000–LDS.2242-K LF2242– 33 25 Symbol Parameter Min Max Min Max tCYC Cycle Time 33 25 tPW Clock Pulse Width 10 10 tS Input Setup Time 10 8 tH Input Hold Time 0 0 tD Output Delay 20 16 tDIS Three-State Output Disable Delay (Note 11) 15 15 tENA Three-State Output Enable Delay (Note 11) 15 15 SWITCHING CHARACTERISTICS C OMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING WAVEFORMS :P ASS -THROUGH MODE (INT = DEC) CLK tDIS SI11-0 SO 15-0 OE N tS tPW 123 7 SYNC N+1 N+2 tH 89 1 0 HIGH IMPEDANCE tENA tD f(N )f ( N+1 )f ( N+2 ) tPW

12/16-bit Half-Band Interpolating/ Decimating Digital Filter Video Imaging Products 6 08/16/2000–LDS.2242-K SWITCHING WAVEFORMS :I NTERPOLATE MODE (INT = 0, DEC = 1) CLK tDIS SI11-0 SO 15-0 OE N tS tPW 123 7 SYNC N+2 tH 89 1 0 HIGH IMPEDANCE tENA tD f(N )f ( N+1 )f ( N+2 ) tPW SWITCHING WAVEFORMS :D ECIMATE MODE (INT = 1, DEC = 0) CLK tDIS SI11-0 SO 15-0 OE tPW 123 7 SYNC N+1 N+2 89 1 0 HIGH IMPEDANCE tENA tD f(N )f ( N+2 ) N tH tS tPW

12/16-bit Half-Band Interpolating/ Decimating Digital Filter Video Imaging Products 7 08/16/2000–LDS.2242-K 1. Maximum Ratings indicate stress specifications only. Functional oper- ation of these products at values beyond those indicated in the Operating Condi- tions table is not implied. Exposure to maximum rating conditions for ex- tended periods may affect reliability. 2. The products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. Neverthe- less, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. This device provides hard clamping of transient undershoot and overshoot. In- put levels below ground or above V CC will be clamped beginning at –0.6 V and VCC + 0.6 V. The device can withstand indefinite operation with inputs in the range of –0.5 V to +7.0 V. Device opera- tion will not be adversely affected, how- ever, input current levels will be well in excess of 100 mA. 4. Actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. Supply current for a given applica- tion can be accurately approximated by: where N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing ev- ery cycle and no load, at a 20 MHz clock rate. 7. Tested with all inputs within 0.1 V of V CC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. NCV F NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except t DIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed. This device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The following measures are recommended: a. A 0.1 µF ceramic capacitor should be installed between V CC and Ground leads as close to the Device Under Test (DUT) as possible. Similar capacitors should be installed between device VCC and the tester common, and device ground and tester common. b. Ground and VCC supply planes must be brought directly to the DUT socket or contactor fingers. c. Input voltages should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT input levels relative to the DUT ground pin. 10. Each parameter is shown as a min- imum or maximum value. Input re- quirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter- nal system must supply at least that much time to meet the worst-case re- quirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. For the t ENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing volt- age, V TH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Z- to-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. IOH IOL VTHC L DUT OE 0.2 V tDIStENA 0.2 V 1.5 V 1.5 V 3.5V Vth 1 Z 0 Z Z 1 Z 0 1.5 V 1.5 V 0V Vth VOL * VOH * VOL * VOH * Measured VOL with IOH = –10mA and IOL = 10mA Measured VOH with IOH = –10mA and IOL = 10mA FIGURE B. THRESHOLD LEVELS FIGURE A. OUTPUT LOADING CIRCUIT

12/16-bit Half-Band Interpolating/ Decimating Digital Filter Video Imaging Products 8 08/16/2000–LDS.2242-K SO 12 SO 11 SO 10 SO 9 SO 8 GND VCC SO 7 SO 6 SO 5 SO 4 SO 13 SO 14 SO 15 OE TCO DEC INT SYNC CLK GND SI GND V CC SI10 SI9 SI8 SI7 SI6 SI5 SI4 SI3 VCC Top View SO 3 SO 2 SO 1 SO 0 RND 2 RND 1 RND 0 SI0 SI1 SI2 GND 44-pin

ORDERING INFORMATION

2524 26 27 281918 20 21 22 23 Top View SO 12 SO 11 SO 10 SO 9 SO 8 GND VCC SO 7 SO 6 SO 5 SO 4 GND V CC SI10 SI9 SI8 SI7 SI6 SI5 SI4 SI3 VCC SO 3 SO 2 SO 1 SO 0 RND 2 RND 1 RND 0 SI0 SI1 SI2 GND SO 13 SO 14 SO 15 OE TCO DEC INT SYNC CLK GND SI 44-pin Speed 33 ns 25 ns Plastic J-Lead Chip Carrier (J1) LF2242JC33 LF2242JC25 0°C to +70°C — COMMERCIAL SCREENING Plastic Quad Flatpack (Q4) LF2242QC33 LF2242QC25 –40°C to +85°C — COMMERCIAL SCREENING