LF3310 LODEV | Alldatasheet
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Horizontal / Vertical Digital Image Filter 11/08/2001-LDS.3310-H ❑❑❑❑❑ 12-bit Data and Coefficients ❑❑❑❑❑ On-board Memory for 256 Horizontal and Vertical Coefficient Sets ❑❑❑❑❑ LF InterfaceTM Allows All 512 Coefficient Sets to be Updated Within Vertical Blanking ❑❑❑❑❑ Selectable 12-bit Data Output with User-Defined Rounding and Limiting ❑❑❑❑❑ Seven 3K x 12-bit, Programmable Two-Mode Line Buffers ❑❑❑❑❑ 16 Horizontal Filter Taps ❑❑❑❑❑ 8 Vertical Filter Taps ❑❑❑❑❑ Two Operating Modes: Dimension- ally Separate and Orthogonal ❑❑❑❑❑ Supports Interleaved Data Streams ❑❑❑❑❑ Horizontal Filter Supports Decima- tion up to 16:1 for Increasing Number of Filter Taps ❑❑❑❑❑ 3.3 Volt Power Supply ❑❑❑❑❑ 5 Volt Tolerant I/O FEATURES DESCRIPTION The LF3310 is a two-dimensional digital image filter capable of filtering data at real-time video rates. The device contains both a horizontal and a vertical filter which may be cascaded or used concurrently for two-dimensional filtering. The input, coefficient, and output data are all 12-bits and in two’s complement format. The horizontal filter is designed to take advantage of symmetric coefficient sets. When symmetric coefficient sets are used, the horizontal filter can be configured as a 16-tap FIR filter. When asymmetric coefficient sets are used, it can be configured as an 8-tap FIR filter. The vertical filter is an 8-tap FIR filter with all required line buffers contained on-chip. The line buffers can store video lines with lengths from 4 to 3076 pixels. Horizontal filter Interleave/Decima- tion Registers (I/D Registers) and the vertical filter line buffers allow interleaved data to be fed directly into the device and filtered without separating the data into individual data streams. The horizontal filter can handle a maximum of sixteen data sets interleaved together. The vertical filter can handle interleaved video lines which contain 3076 or less data values. The I/D Registers and horizontal accumulator facilitate using decimation to increase the number of filter taps in the horizontal filter. Decimation of up to 16:1 is supported. The device has on-chip storage for 256 horizontal coefficient sets and 256 vertical coefficient sets. Each filter’s coefficients are loaded independently of each other allowing one filter’s coefficients to be updated without affecting the other filter’s coefficients. In addition, a horizontal or vertical coefficient set can be updated inde- pendently from the other coefficient sets in the same filter. LF3310 BLOCK DIAGRAM DIN11-0 3K LINE BUFFER DOUT 11-0
256 COEFFICIENT SET STORAGE
Horizontal / Vertical Digital Image FilterDEVICES INCORPORATED
FIGURE 1. LF3310 FUNCTIONAL BLOCK DIAGRAM
Configuration/Control Registers. Configuration/Control Registers. to the multipliers in the vertical filter. InterfaceTM on the rising edge of CLK. section for a full discussion). FIGURE 2. INPUT FORMATS FIGURE 3. HORIZONTAL AND VERTICAL ACCUMULATOR FORMATS TABLE 1. OUTPUT FORMATS
00000 F 11 F10 F9 · · · F6 F5 · · · F2 F1 F0
00001 F 12 F11 F10 · · · F7 F6 · · · F3 F2 F1
00010 F 13 F12 F11 · · · F8 F7 · · · F4 F3 F2
10010 F 29 F28 F27 · · · F24 F23 · · ·F20 F19 F18
10011 F 30 F29 F28 · · · F25 F24 · · ·F21 F20 F19
10100 F 31 F30 F29 · · · F26 F25 · · ·F22 F21 F20
Horizontal / Vertical Digital Image Filter Video Imaging Products 11/08/2001-LDS.3310-H HCEN — Horizontal Coefficient Address Enable When HCEN is LOW, data on HCA7-0 is latched into the Horizontal Coeffi- cient Address Register on the rising edge of CLK. When HCEN is HIGH, data on HCA 7-0 is not latched and the register’s contents will not be changed. VLD — Vertical Coefficient Load When VLD is LOW, data on VCF 11-0 is latched into the Vertical LF InterfaceTM on the rising edge of CLK. When VLD is HIGH, data can not be latched into the Vertical LF Interface TM. When enabling the LF InterfaceTM for data input, a HIGH to LOW transition of VLD is required in order for the input circuitry to func- tion properly. Therefore, VLD must be set HIGH immediately after power up to ensure proper operation of the input circuitry (see the LF Interface TM section for a full discussion). VCEN — Vertical Coefficient Address Enable When VCEN is LOW, data on VCA 7-0 is latched into the Vertical Coefficient Address Register on the rising edge of CLK. When VCEN is HIGH, data on VCA 7-0 is not latched and the register’s contents will not be changed. TXFR — Horizontal Filter LIFO Transfer Control TXFR is used to change which LIFO in the data reversal circuitry sends data to the reverse data path and which LIFO receives data from the forward data path. When TXFR goes LOW, the LIFO sending data to the reverse data path becomes the LIFO receiving data from the forward data path, and the LIFO receiving data from the forward data path becomes the LIFO sending data to the reverse data path. The device must see a HIGH to LOW transition of TXFR in order to switch LIFOs. HACC — Horizontal Accumulator Control When HACC is HIGH, the horizontal accumulator is enabled for accumula- tion and the accumulator output register is disabled for loading. When HACC is LOW, no accumulation is performed and the accumulator output register is enabled for loading. HACC is latched on the rising edge of CLK. VACC — Vertical Accumulator Control When VACC is HIGH, the vertical accumulator is enabled for accumula- tion and the accumulator output register is disabled for loading. When VACC is LOW, no accumulation is performed and the accumulator output register is enabled for loading. VACC is latched on the rising edge of CLK. HSHEN — Horizontal Shift Enable HSHEN enables or disables the loading of data into the forward and reverse I/D Registers in the horizon- tal filter when the device is in Dimen- sionally Separate Mode. If the device is configured such that the horizontal filter feeds the vertical filter, HSHEN also enables or disables the loading of data into the input register (DIN 11-0). If the device is configured such that the vertical filter feeds the horizontal filter and the vertical limit register is under shift control, HSHEN also enables or disables the loading of data into the vertical limit register in the vertical Round/Select/Limit circuitry. In Orthogonal Mode, HSHEN also enables or disables the loading of data into the input register (DIN 11-0) and the line buffers in the vertical filter. It is important to note that in Orthogo- nal Mode, either HSHEN or VSHEN can disable data loading. Both must be active to enable data loading in Orthogonal Mode. Also in Orthogo- nal Mode, the horizontal and vertical limit registers can not be disabled. When HSHEN is LOW, data is loaded into and shifted through the registers HSHEN controls and the forward and reverse I/D Registers on the rising edge of CLK. When HSHEN is HIGH, data is not loaded into or shifted through the registers HSHEN controls and the I/D Registers, and their contents will not be changed. HSHEN is latched on the rising edge of CLK. VSHEN — Vertical Shift Enable VSHEN enables or disables the loading of data into the line buffers in the vertical filter when the device is in Dimensionally Separate Mode. If the device is configured such that the vertical filter feeds the horizontal filter, VSHEN also enables or disables the loading of data into the input register (DIN 11-0). If the device is configured such that the horizontal filter feeds the vertical filter and the horizontal limit register is under shift control, VSHEN also enables or disables the loading of data into the horizontal limit register in the hori- zontal Round/Select/Limit circuitry. In Orthogonal Mode, VSHEN also enables or disables the loading of data into the input register (DIN 11-0) and the forward and reverse I/D Registers in the horizontal filter. It is important to note that in Orthogonal Mode, either HSHEN or VSHEN can disable data loading. Both must be active to enable data loading in Orthogonal Mode. Also in Orthogonal Mode, the horizontal and vertical limit registers can not be disabled. When VSHEN is LOW, data is loaded into and shifted through the registers VSHEN controls and the line buffers on the rising edge of CLK. When VSHEN is HIGH, data is not loaded into or shifted through the registers VSHEN controls and the line buffers, and their contents will not be changed. VSHEN is latched on the rising edge of CLK.
32-bits wide and user-programmable. rounded to any precision required. zontal round register 1 and so on. zontal select register 1 and so on. changed every clock cycle if desired.
0 ALU Mode 0 : A + B
1 Pass A 0 : ALU Input A = 0
2 Pass B 0 : ALU Input B = 0
TABLE 2. CONFIGURATION REGISTER 0 – ADDRESS 200H
0 Odd-Tap Interleave Mode 0 : Odd-Tap Interleave Mode Disabled
5 Horizontal Tap Number 0 : Even Number of Taps
6 Horizontal Data Reversal 0 : Data Reversal Enabled
TABLE 3. CONFIGURATION REGISTER 1 – ADDRESS 201H
configured to have as many as 8-taps. There are seven on-chip line buffers. greater than 3072 are not valid. takes to load a single line buffer. the forward and reverse I/D Registers. data sets are interleaved together. TABLE 4. CONFIGURATION REGISTER 2 – ADDRESS 202H
0 Line Buffer Mode 0 : Delay Mode
1 Line Buffer Load 0 : Normal Load
TABLE 5. CONFIGURATION REGISTER 3 – ADDRESS 203H
0 HV Filter Mode 0 : Orthogonal Mode
1 HV Direction 0 : Horizontal to Vertical
4 Limit Register Load Control 0 : Limit Registers Always Enabled
TABLE 6. CONFIGURATION REGISTER 4 – ADDRESS 204H
0 Vertical Limit Enable 0 : Vertical Limiting Disabled
1 Horizontal Limit Enable 0 : Horizontal Limiting Disabled
TABLE 7. CONFIGURATION REGISTER 5 – ADDRESS 205H
32-bits wide and user-programmable. rounded to any precision required. vertical round register 1 and so on. TABLE 9. HRZ . ROUND REGISTERS
0 C00
1 C01
14 C0E
15 C0F
TABLE 11. HRZ . LIMIT REGISTERS
0 A00
1 A01
14 A0E
15 A0F
TABLE 12. VRT . ROUND REGISTERS
0 E00
1 E01
14 E0E
15 E0F
TABLE 14. VRT . LIMIT REGISTERS
- A value of 1 selects vertical select
changed every clock cycle if desired. TABLE 8. HCF/VCF11-9 D ECODE
- A value of 1 selects vertical limit
limit value is passed as the filter output. range to be changed every clock cycle. TABLE 10. HRZ . SELECT REGISTERS TABLE 13. VRT . SELECT REGISTERS
all four data values are loaded. coefficient sets into the device. TABLE 16. CONFIGURATION REGISTER LOADING FORMAT TABLE 17. ROUND REGISTER LOADING FORMAT R = Reserved. Must be set to “0”.
- This bit represents the LSB of the Round Register.
** This bit represents the MSB of the Round Register.
zontal or Vertical LF Interfaces TM. tion as if the write occurred.
- This bit represents the MSB of the Lower Limit.
** This bit represents the MSB of the Upper Limit. TABLE 18. SELECT REGISTER LOADING FORMAT TABLE 19. LIMIT REGISTER LOADING FORMAT
Horizontal / Vertical Digital Image Filter 11/08/2001-LDS.3310-H M AXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Symbol Parameter Test Condition Min Typ Max Unit VOH Output High Voltage VCC = Min., IOH = –4 mA 2.4 V VOL Output Low Voltage VCC = Min., IOL = 8.0 mA 0.4 V VIH Input High Voltage 2.0 5.5 V VIL Input Low Voltage (Note 3) 0.0 0.8 V IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±10 µA IOZ Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±10 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 250 mA ICC2 VCC Current, Quiescent (Note 7) 2m A C IN Input Capacitance TA = 25°C, f = 1 MHz 10 pF C OUT Output Capacitance TA = 25°C, f = 1 MHz 10 pF ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) O PERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Supply Voltage Active Operation, Commercial 0 ºC to +70ºC 3.00 V ≤ VCC ≤ 3.60 V Active Operation, Military –55 ºC to +125ºC 3.00 V ≤ VCC ≤ 3.60 V
Horizontal / Vertical Digital Image Filter Video Imaging Products 11/08/2001-LDS.3310-H 12345678901234567890123456789 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 12345678901234567890123456789 LF3310– 25* 18* 15 12 Symbol Parameter Min Max Min Max Min Max Min Max tCYC Cycle Time 25 18 15 12 tPWL Clock Pulse Width Low 10 8 7 5 tPWH Clock Pulse Width High 10 8 7 5 tS0 Input Setup Time 8654 tS1 Input Setup Time (xCEN, xRSL)* 8654 tH0 Input Hold Time 1111 tH1 Input Hold Time (xCEN, xRSL)* 1.5 1.5 1.5 1.5 tD Output Delay 13 11 10 8 tDIS Three-State Output Disable Delay (Note 11) 15 13 12 10 tENA Three-State Output Enable Delay (Note 11) 15 13 12 10 SWITCHING CHARACTERISTICS C OMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING WAVEFORMS :D ATA I/O CLK tPWH tPWL tCYC VCA 7-0 DOUT 15-0 123456 tH0 tS0 tDtDIS HIGH IMPEDANCE tENA OUTPUT N -1 OUTPUT N HCA/VCA N HCA/VCA N+1 HCA 7-0 OE CONTROLS (Except OE) DIN11-0 DINN+1DINN xCEN, xRSL tH1 tS1 * The ‘x’ represents both horizontal and vertical signals for each case. 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 *DISCONTINUED SPEED GRADE
Horizontal / Vertical Digital Image Filter 11/08/2001-LDS.3310-H 12345678901234567890123456789 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 1 234567890123456789012345678 9 12345678901234567890123456789 LF3310– 25* 18* 15 12 Symbol Parameter Min Max Min Max Min Max Min Max tCFS Coefficient Input Setup Time 8655 tCFH Coefficient Input Hold Time 1 1 1 1.5 tLS Load Setup Time 8654 tLH Load Hold Time 1 1 1 1.5 tPS PAUSE Setup Time 8654 tPH PAUSE Hold Time 1.5 1.5 1.5 1.5 C OMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING WAVEFORMS : LF INTERFACE TM CLK tPWLtPWH tCYC tLS tCFS tCFH ADDRESS tLH HCF 11–0 HLD 12 45 3 CF 1CF 0 HPAUSE tPS tPH VLD VPAUSE VCF 11–0 CF 2 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 *DISCONTINUED SPEED GRADE
Horizontal / Vertical Digital Image Filter Video Imaging Products 11/08/2001-LDS.3310-H 1. Maximum Ratings indicate stress specifications only. Functional oper- ation of these products at values beyond those indicated in the Operating Condi- tions table is not implied. Exposure to maximum rating conditions for ex- tended periods may affect reliability. 2. The products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. Never- theless, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. This device provides hard clamping of transient undershoot. Input levels below ground will be clamped begin- ning at –0.6 V. The device can with- stand indefinite operation with inputs or outputs in the range of –0.5 V to +5.5 V. Device operation will not be adversely affected, however, input cur- rent levels will be well in excess of 100 mA. 4. Actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. Supply current for a given applica- tion can be accurately approximated by: where N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with outputs changing every cycle and no load, at a 40 MHz clock rate. 7. Tested with all inputs within 0.1 V of V CC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. NCV F NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except t DIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed. This device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The following measures are recommended: a. A 0.1 µF ceramic capacitor should be installed between V CC and Ground leads as close to the Device Under Test (DUT) as possible. Similar capacitors should be installed between device VCC and the tester common, and device ground and tester common. b. Ground and VCC supply planes must be brought directly to the DUT socket or contactor fingers. c. Input voltages on a test fixture should be adjusted to compensate for inductive ground and VCC noise to main- tain required DUT input levels relative to the DUT ground pin. 10. Each parameter is shown as a min- imum or maximum value. Input re- quirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter- nal system must supply at least that much time to meet the worst-case re- quirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. For the t ENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing volt- age, V TH, is set at 3.0 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Z- to-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. IOH IOL VTHC L DUT OE 0.2 V tDIStENA 0.2 V 1.5 V 1.5 V 3.0V Vth 1 Z 0 Z Z 1 Z 0 1.5 V 1.5 V 0V Vth VOL * VOH * VOL * VOH * Measured VOL with IOH = –10mA and IOL = 10mA Measured VOH with IOH = –10mA and IOL = 10mA FIGURE B. THRESHOLD LEVELS FIGURE A. OUTPUT LOADING CIRCUIT
Horizontal / Vertical Digital Image Filter 11/08/2001-LDS.3310-H
ORDERING INFORMATION
0°C to +70°C — COMMERCIAL SCREENING Speed 15 ns 12 ns –55°C to +125°C — MIL-STD-883 COMPLIANT –55°C to +125°C — COMMERCIAL SCREENING 144-pin Plastic Quad Flatpack (Q5) LF3310QC15 LF3310QC12 VCC GND GND GND GND VCC GND DIN DIN10 DIN9 DIN8 DIN7 DIN6 GND VCC DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 GND VCC VCA 7 VCA 6 VCA 5 VCA 4 VCA 3 VCA 2 VCA 1 VCA 0 VCEN VSHEN VCC VCC VCC GND GND GND GND GND HCF HCF 10 HCF 9 HCF 8 HCF 7 HCF 6 HCF 5 HCF 4 HCF 3 HCF 2 HCF 1 HCF 0 GND CLK VCC HLD GND VCC HPAUSE GND VCC HSHEN GND VCC TXFR VCC GND GND VCC VCC VCC GND GND HCA HCA 6 HCA 5 HCA 4 HCA 3 HCA 2 HCA 1 HCA 0 VCC GND HCEN GND VCC GND GND GND GND VCF VCF 10 VCF 9 VCF 8 VCF 7 VCF 6 VCF 5 VCF 4 VCF 3 VCF 2 VCF 1 VCF 0 VLD VPAUSE VCC VCC VCC GND VACC GND VRSL 3 VRSL 2 VRSL 1 VRSL 0 VCC GND NC NC NC NC DOUT DOUT 10 DOUT 9 DOUT 8 GND OE DOUT 7 DOUT 6 DOUT 5 DOUT 4 DOUT 3 DOUT 2 DOUT 1 DOUT 0 GND VCC GND HRSL 3 HRSL 2 HRSL 1 HRSL 0 HACC GND 108 107 106 105 104 103 102 101 100 Top View 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109