LF43168

LF43168 LODEV | Alldatasheet

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03/28/2000–LDS.43168-H qqqqq 66 MHz Data and Computation Rate qqqqq Two Independent 8-Tap or Single 16-Tap FIR Filters qqqqq 10-bit Data and Coefficient Inputs qqqqq 32 Programmable Coefficient Sets qqqqq Supports Interleaved Coefficient Sets qqqqq User Programmable Decimation up to 16:1 qqqqq Maximum of 256 FIR Filter Taps, 16 x 16 2-D Kernels, or 10 x 20-bit Data and Coefficients qqqqq Replaces Harris HSP43168 qqqqq Package Styles Available:

• 84-pin Plastic LCC, J-Lead
• 100-pin Plastic Quad Flatpack FEATURES DESCRIPTION LF43168 Dual 8-Tap FIR FilterDEVICES INCORPORATED The LF43168 is a high-speed dual FIR filter capable of filtering data at real- time video rates. The device contains two FIR filters which may be used as two separate filters or cascaded to form one filter. The input and coeffi- cient data are both 10-bits and can be in unsigned, two’s complement, or mixed mode format. The filter architecture is optimized for symmetric coefficient sets. When symmetric coefficient sets are used, each filter can be configured as an 8-tap FIR filter. If the two filters are cas- caded, a 16-tap FIR filter can be implemented. When asymmetric coefficient sets are used, each filter is configured as a 4-tap FIR filter. If both filters are cascaded, an 8-tap filter can be implemented. The LF43168 can decimate the output data by as much as 16:1. When the device is pro- grammed to decimate, the number of clock cycles available to calculate filter taps increases. When configured for 16:1 decimation, each filter can be configured as a 128-tap FIR filter (if symmetric coefficient sets are used). By cascading these two filters, the device can be configured as a 256-tap FIR filter. There is on-chip storage for 32 different sets of coefficients. Each set consists of eight coefficients. Access to more than one coefficient set facilitates adaptive filtering opera- tions. The 28-bit filter output can be rounded from 8 to 19 bits. LF43168 BLOCK DIAGRAM CIN9-0 A8-0 WR CONTROL CSEL 4-0 COEFFICIENT BANK A COEFFICIENT BANK B FILTER CELL A FILTER CELL B MUX INA9-0 INB9-0/ OUT 8-0 MUX/ADDER 9 19 MUX OEL OEH OUT 27-9

FIGURE 1. LF43168 FUNCTIONAL BLOCK DIAGRAM

for output and INB9-1 can not be used. is available for data input. register on the rising edge of WR. cycles from when WR goes HIGH. can be loaded asynchronously to CLK. delay length is set using these bits. data formats respectively for filter A. enables or disables output rounding.

4 Filter Mode Select 0 = Single Filter Mode

5 Coefficient Symmetry Select 0 = Even-Symmetric Coefficients

6 FIR Filter A: Odd/Even Taps 0 = Odd Number of Filter Taps

7 FIR Filter B: Odd/Even Taps 0 = Odd Number of Filter Taps

8 FIR Filter B Input Source 0 = Input from INA 9-0

9 Interleaved/Non-Interleaved 0 = Non-Interleaved Coefficient Sets

TABLE 1. CONTROL REGISTER 0 – ADDRESS 000H

set consists of 8 coefficient values. Each bank can hold 32 10-bit values. of the registers are fed into the ALUs. ber of filter taps needed is cut in half.

0 FIR Filter A Input Data Format 0 = Unsigned

1 FIR Filter A Coefficient Format 0 = Unsigned

2 FIR Filter B Input Data Format 0 = Unsigned

3 FIR Filter B Coefficient Format 0 = Unsigned

4 Data Order Reversal Enable 0 = Enabled

9 Output Round Enable 0 = Enabled

TABLE 2. CONTROL REGISTER 1 – ADDRESS 001H grammed to decimate by 2 to 16 (see Decimation section and Table 1). input and decimation registers is held.

data feedback decimation register. decimation register's delay length. in filters A and B are cascaded together. is sent to the reverse decimation path. tor output registers is enabled. being added to filter A’s output. Mux/Adder performs (see Table 3). ALU will perform the B – A operation.

00 Filter A + Filter B

01 Filter A + Filter B

10 Filter A

11 Filter B

TABLE 3. MUX 1-0 FUNCTION

03/28/2000–LDS.43168-H M AXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) O PERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Supply Voltage Active Operation, Commercial 0°C to +70°C 4.75 V £ VCC £ 5.25 V Active Operation, Military –55°C to +125°C 4.50 V £ VCC £ 5.50 V Symbol Parameter Test Condition Min Typ Max Unit VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.6 V VOL Output Low Voltage VCC = Min., IOL = 4.0 mA 0.4 V VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage (Note 3) 0.0 0.8 V IIX Input Current Ground £ VIN £ VCC (Note 12) –10 µA IOZ Output Leakage Current Ground £ VOUT £ VCC (Note 12) –10 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 300 mA ICC2 VCC Current, Quiescent (Note 7) 500 µA C IN Input Capacitance TA = 25°C, f = 1 MHz 12 pF C OUT Output Capacitance TA = 25°C, f = 1 MHz 12 pF ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)

03/28/2000–LDS.43168-H LF43168– 30 22 15 Symbol Parameter Min Max Min Max Min Max tCYC Cycle Time 30 22 15 tPW Clock Pulse Width 12 8 7 tS Input Setup Time 15 12 5 tH Input Hold Time 0 0 0 tWP Write Period 30 22 15 tWPW Write Pulse Width 12 10 7 tWHCH Write High to Clock High 5 3 2 tCWS CIN9-0 Setup Time 12 10 5 tCWH CIN9-0 Hold Time 0 0 0 tAWS Address Setup Time 10 8 5 tAWH Address Hold Time 0 0 0 tD Output Delay 14 12 11 tENA Three-State Output Enable Delay (Note 11) 12 12 12 tDIS Three-State Output Disable Delay (Note 11) 12 12 12 C OMMERCIAL OPERATING RANGE Notes 9, 10 (ns) SWITCHING CHARACTERISTICS SWITCHING WAVEFORMS CLK INPUTS/ CIN9-0 tPW tPW tCYC A8-0 OEL OUT 27-0 tH tS tDtDIS HIGH IMPEDANCE tENA OEH WR tAWS tAWH tCWH tCWS tWHCH *includes INA9-0, INB9-0, CSEL4-0, ACCEN, MUX 1-0, SHFTEN, FWRD, RVRS, and TXFR. CONTROLS* tWPW tWPWtWP

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03/28/2000–LDS.43168-H 1. Maximum Ratings indicate stress specifications only. Functional oper- ation of these products at values beyond those indicated in the Operating Condi- tions table is not implied. Exposure to maximum rating conditions for ex- tended periods may affect reliability. 2. The products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. Neverthe- less, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. This device provides hard clamping of transient undershoot and overshoot. In- put levels below ground or above V CC will be clamped beginning at –0.6 V and VCC + 0.6 V. The device can withstand indefinite operation with inputs in the range of –0.5 V to +7.0 V. Device opera- tion will not be adversely affected, how- ever, input current levels will be well in excess of 100 mA. 4. Actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. Supply current for a given applica- tion can be accurately approximated by: where N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing ev- ery cycle and no load, at a 20 MHz clock rate. 7. Tested with all inputs within 0.1 V of V CC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. NCV F NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except t DIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed. This device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The following measures are recommended: a. A 0.1 µF ceramic capacitor should be installed between V CC and Ground leads as close to the Device Under Test (DUT) as possible. Similar capacitors should be installed between device VCC and the tester common, and device ground and tester common. b. Ground and VCC supply planes must be brought directly to the DUT socket or contactor fingers. c. Input voltages should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT input levels relative to the DUT ground pin. 10. Each parameter is shown as a min- imum or maximum value. Input re- quirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter- nal system must supply at least that much time to meet the worst-case re- quirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. For the t ENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output volt age with ±10mA loads. The balancing volt- age, V TH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Z- to-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. IOH IOL VTHC L DUT OE 0.2 V tDIStENA 0.2 V 1.5 V 1.5 V 3.5V Vth 1 Z 0 Z Z 1 Z 0 1.5 V 1.5 V 0V Vth VOL * VOH * VOL * VOH * Measured VOL with IOH = –10mA and IOL = 10mA Measured VOH with IOH = –10mA and IOL = 10mA FIGURE B. THRESHOLD LEVELS FIGURE A. OUTPUT LOADING CIRCUIT

03/28/2000–LDS.43168-H Plastic J-Lead Chip Carrier (J3) LF43168JC30 LF43168JC22 LF43168JC15 84-pin Speed 30 ns 22 ns 15 ns

ORDERING INFORMATION

4443 45 46 47 493837 39 40 41 42 Top View 891011 78 77 76 75 36353433 50 51 52 53 CIN7 CIN6 CIN5 CIN4 GND CIN3 CIN2 CIN1 CIN0 INA9 INA8 INA7 INA6 INA5 VCC INA4 INA3 INA2 INA1 INA0 INB9 RVRS FWRD SHFTEN TXFR ACCEN V CC CLK GND OEH OUT OUT 26 OUT 25 OUT 24 OUT 23 OUT 22 OUT 21 OUT 20 OUT 19 OUT 18 OUT 17 VCC INB8 INB7 INB6 INB5 GND INB4 INB3 INB2 INB1 INB0 OEL OUT 9 OUT 10 VCC OUT 11 OUT 12 OUT 13 OUT 14 OUT 15 OUT 16 GND CIN8 CIN9 CSEL 4 CSEL 3 CSEL 2 CSEL 1 CSEL 0 VCC GND WR MUX MUX 0 –40°C to +85°C — COMMERCIAL SCREENING 0°C to +70°C — COMMERCIAL SCREENING

03/28/2000–LDS.43168-H Plastic Quad Flatpack (Q2) LF43168QC30 LF43168QC22 LF43168QC15 100-pin Speed 30 ns 22 ns 15 ns V CC VCC CLK GND GND OEH OUT OUT 26 OUT 25 OUT 24 OUT 23 OUT 22 OUT 21 OUT 20 OUT 19 OUT 18 OUT 17 NC V CC VCC GND GND INB6 INB5 GND GND INB INB3 INB2 INB1 INB0 OEL OUT 9 OUT 10 VCC VCC OUT 11 OUT 12 OUT 13 OUT 14 OUT 15 OUT 16 Top View 100 –40°C to +85°C — COMMERCIAL SCREENING 0°C to +70°C — COMMERCIAL SCREENING

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Ceramic Pin Grid Array (G6) 84-pin Speed 0°C to +70°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT –55°C to +125°C — COMMERCIAL SCREENING A B C D E F G H J K L Top View Through Package (i.e., Component Side Pinout) 12345 6 7 8 9 10 11 CSEL4 CIN7 CIN6 GND CIN1 INA9 INA5 INA3 INA0 INB8 INB6 CSEL3 CIN9 CIN2 INA8 INA7 INB7 INB5 CSEL1 CSEL2 GND INB4 VCC CSEL0 INB3 INB2 INB1 OEL INB0 OUT11 OUT9 VCC OUT10 OUT13 OUT12 CIN8 CIN5 CIN4 CIN3 CIN0 VCC INA6 INA4 INA2 INA1 INB9 GND MUX1 CLK OUT26 OUT25 OUT16 OUT14 WR MUX0 FWRD ACCEN GND OUT22 OUT23 OUT20 OUT17 VCC OUT15 RVRS SHFTEN TXFR VCC OEH OUT27 OUT24 OUT21 OUT19 OUT18 GND Discontinued Package