LF48212

LF48212 LODEV | Alldatasheet

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08/16/2000–LDS.48212-F ❑❑❑❑❑ 50 MHz Data and Computation Rate ❑❑❑❑❑ Two’s Complement or Unsigned Operands ❑❑❑❑❑ On-board Programmable Delay Stages ❑❑❑❑❑ Programmable Output Rounding ❑❑❑❑❑ Replaces Harris HSP48212 ❑❑❑❑❑ Package Styles Available:

• 68-pin PLCC, J-Lead
• 64-pin PQFP FEATURES DESCRIPTION LF48212 12 x 12-bit Alpha MixerDEVICES INCORPORATED The LF48212 is a high-speed video alpha mixer capable of mixing video signals at real-time video rates. It takes two 12-bit video signals and mixes them together using an alpha mix factor. Alpha determines the weighting that each video signal receives during the mix operation. The input video data can be in either unsigned or two’s complement format, but both inputs must be in the same format. Independently con- trolled programmable delay stages are provided for the input and control signals to allow for allignment of input data if necessary. The delay stages can be programmed to have from 0 to 7 delays. The 13-bit output of the alpha mixer is registered with three-state drivers and may be rounded to 8, 10, 12, or 13-bits. LF48212 BLOCK DIAGRAM DINA 11-0α 11-0 DINB 11-0 FORMAT FORMAT 0-7 α 1.0 – α 0-7 0-7 ADJUST FORMAT DOUT 12-0 0-70-7 TC RND 1-0 DELAY CONTROL REGISTER BYPASS DEL LD CLK MIXEN OE NOTE: NUMBERS IN REGISTERS INDICATE NUMBER OF PIPELINE DELAYS. 12 12 12

latched on the rising edge of CLK. added to the input and control signals. latched on the rising edge of LD. FIGURE 1. ALPHA MIX INPUT FORMAT HIGH, the data is in unsigned format. internal data already in the pipeline. held as the alpha mix value. on DEL into the Delay Control Register. automatically be loaded with a “0”.

00 Round to 8-bits

01 Round to 10-bits

10 Round to 12-bits

11 Round to 13-bits

TABLE 1. OUTPUT ROUNDING may be rounded to 8, 10, 12, or 13-bits. data latched in at the same time.

08/16/2000–LDS.48212-F O PERATING CONDITIONS To meet specified electrical and switching characteristics Mode Temperature Range (Ambient) Supply Voltage Active Operation, Commercial 0°C to +70°C 4.75 V ≤ VCC ≤ 5.25 V M AXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Symbol Parameter Test Condition Min Typ Max Unit VOH Output High Voltage VCC = Min., IOH = –400 µA 2.6 V VOL Output Low Voltage VCC = Min., IOL = 2.0 mA 0.4 V VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage (Note 3) 0.0 0.8 V IIX Input Current Ground ≤ VIN ≤ VCC (Note 12) ±10 µA IOZ Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±10 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 120 mA ICC2 VCC Current, Quiescent (Note 7) 500 µA C IN Input Capacitance TA = 25°C, f = 1 MHz 10 pF C OUT Output Capacitance TA = 25°C, f = 1 MHz 10 pF ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)

08/16/2000–LDS.48212-F LF48212– 25 20 Symbol Parameter Min Max Min Max tCYC Cycle Time 25 20 tPW Clock Pulse Width 10 10 tS Input Setup Time 11 11 tH Input Hold Time 0 0 tD Output Delay 14 14 tENA Three-State Output Enable Delay (Note 11) 13 13 tDIS Three-State Output Disable Delay (Note 11) 13 13 C OMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING CHARACTERISTICS SWITCHING WAVEFORMS :D ATA I/O CLK tCYC tPW tPW DINA 11-0 DINB 11-0 tS tH DOUT 12-0 α 11-0 tS tH CONTROLS* tS tH OE tD tDIS tENA HIGH IMPEDANCE *includes MIXEN, TC, and RND1-0.

08/16/2000–LDS.48212-F LF48212– 25 20 Symbol Parameter Min Max Min Max tLC LD Cycle Time 25 20 tLPW LD Pulse Width 10 10 tDS DEL Setup Time 12 12 tDH DEL Hold Time 0 0 C OMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) SWITCHING WAVEFORMS :D ELAY CONTROL REGISTER DATA LD tLC tLPW tLPW DEL tDS tDH

08/16/2000–LDS.48212-F 1. Maximum Ratings indicate stress specifications only. Functional oper- ation of these products at values beyond those indicated in the Operating Condi- tions table is not implied. Exposure to maximum rating conditions for ex- tended periods may affect reliability. 2. The products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. Neverthe- less, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. This device provides hard clamping of transient undershoot and overshoot. In- put levels below ground or above V CC will be clamped beginning at –0.6 V and VCC + 0.6 V. The device can withstand indefinite operation with inputs in the range of –0.5 V to +7.0 V. Device opera- tion will not be adversely affected, how- ever, input current levels will be well in excess of 100 mA. 4. Actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. Supply current for a given applica- tion can be accurately approximated by: where N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing ev- ery cycle and no load, at a 40 MHz clock rate. 7. Tested with all inputs within 0.1 V of V CC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. NCV F NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except t DIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30 pF minimum, and may be distributed. This device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The following measures are recommended: a. A 0.1 µF ceramic capacitor should be installed between V CC and Ground leads as close to the Device Under Test (DUT) as possible. Similar capacitors should be installed between device VCC and the tester common, and device ground and tester common. b. Ground and VCC supply planes must be brought directly to the DUT socket or contactor fingers. c. Input voltages should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT input levels relative to the DUT ground pin. 10. Each parameter is shown as a min- imum or maximum value. Input re- quirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter- nal system must supply at least that much time to meet the worst-case re- quirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 11. For the t ENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing volt- age, V TH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Z- to-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. IOH IOL VTHC L DUT OE 0.2 V tDIStENA 0.2 V 1.5 V 1.5 V 3.5V Vth 1 Z 0 Z Z 1 Z 0 1.5 V 1.5 V 0V Vth VOL * VOH * VOL * VOH * Measured VOL with IOH = –10mA and IOL = 10mA Measured VOH with IOH = –10mA and IOL = 10mA FIGURE B. THRESHOLD LEVELS FIGURE A. OUTPUT LOADING CIRCUIT

08/16/2000–LDS.48212-F Plastic J-Lead Chip Carrier (J2) LF48212JC25 LF48212JC20

ORDERING INFORMATION

0°C to +70°C — COMMERCIAL SCREENING Speed 25 ns 20 ns 68-pin 1234567 68 67 66 65 64 63 3635 37 38 39 413029 31 32 33 34 Top View 896 2 6 1 2827 42 43 DINB 11 DINB 10 DINB 9 DINB 8 DINB 7 DINB 6 GND DINB 5 NC DINB 4 DINB 3 DINB 2 DINB 1 DINB 0 RND 1 RND 0 DEL OE DOUT 12 DOUT 11 DOUT 10 DOUT 9 GND DOUT DOUT 7 NC DOUT DOUT 5 VCC DOUT 4 DOUT 3 DOUT 2 DOUT 1 DOUT 0 LD TC DINA 11 DINA 10 DINA 9 VCC DINA 8 DINA 7 NC DINA 6 DINA 5 DINA 4 GND DINA 3 DINA 2 DINA 1 DINA 0 CLK MIXEN α 0 α 1 α 2 α 3 α 4 α 5 NC α 6 α 7 VCC α 8 α 9 α 10 α 11 BYPASS

08/16/2000–LDS.48212-F Plastic Quad Flatpack (Q3) LF48212QC25 LF48212QC20 0°C to +70°C — COMMERCIAL SCREENING Speed 25 ns 20 ns 64-pin DINB 11 DINB 10 DINB 9 DINB 8 DINB 7 DINB 6 GND DINB 5 DINB 4 DINB 3 DINB 2 DINB 1 DINB 0 RND 1 RND 0 DEL CLK MIXEN α 0 α 1 α 2 α 3 α 4 α 5 α 6 α 7 VCC α 8 α 9 α 10 α 11 BYPASS OE DOUT DOUT 11 DOUT 10 DOUT 9 GND DOUT DOUT 7 DOUT 6 DOUT 5 VCC DOUT 4 DOUT 3 DOUT 2 DOUT 1 DOUT 0 LD TC DINA 11 DINA 10 DINA 9 VCC DINA 8 DINA 7 DINA 6 DINA 5 DINA 4 GND DINA 3 DINA 2 DINA 1 DINA 0 Top View